This register configures the contents of the 22-bit output data word (D[21:0]).
|LEGEND: R/W = Read/Write; R = Read only; -n = value after reset|
|7-4||0||R||0000b||Reserved bits. Reads return 0000b.|
|3-2||FPAR_LOC[1:0]||R/W||00b||These bits control the data span for calculating the FTPAR bit (bit D in the output data word).
00b = D reflects even parity calculated for 4 MSB
01b = D reflects even parity calculated for 8 MSB
10b = D reflects even parity calculated for 12 MSB
11b = D reflects even parity calculated for 16 MSB
|1||PAR_EN||R/W||0b||0b = Output data does not contain any parity information
D = 0
D = 0
1b = Parity information is appended to the LSB of the output data
D = Even parity calculated on bits D[21:4]
D = Even parity computed on selected number of MSB of D[21:4]
as per FPAR_LOC[1:0] setting
See Figure 42 for further details of parity computation.
|0||DATA_VAL||R/W||0b||These bits control bits D[21:4] of the output data word.
0b = 18-bit conversion output
1b = 18-bit contents of the fixed-pattern registers
See PATN CNTL for more details.