The RST pin is an asynchronous digital input for the device. To enter RST state, the host controller pulls the RST pin low and keeps it low for the twl_RST duration (as specified in the Timing Requirements table).
In RST state, all configuration registers (see the Register Maps section) are reset to their default values, the RVS pin remains low, and the SDO-x pins are Hi-Z.
To exit RST state, the host controller pulls the RST pin high, with CONVST and SCLK held low and CS held high, as shown in Figure 39. After a delay of td_rst, the device enters ACQ state and the RVS pin goes high.
To operate the device in either ACQ or CNV state, RST must be held high. With RST held high, transitions on the CONVST pin determine the functional state of the device.
Figure 40 shows a typical conversion process. The internal ADCST signal goes low during conversion and goes high at the end of conversion. With CS held high, RVS reflects the status of ADCST.