These devices support unipolar, fully differential, analog input signals. Figure 35 shows a small-signal equivalent circuit of the sample-and-hold circuit. Each sampling switch is represented by a resistance (RS1 and RS2, typically 50 Ω) in series with an ideal switch (SW1 and SW2). The sampling capacitors, CS1 and CS2, are typically 60 pF.
During the acquisition process (ACQ state), both positive and negative inputs are individually sampled on CS1 and CS2, respectively. During the conversion process (CNV state), the device converts for the voltage difference between the two sampled values: VAINP – VAINM.
Each analog input pin has electrostatic discharge (ESD) protection diodes to REFBUFOUT and GND. Keep the analog inputs within the specified range to avoid turning the diodes on.
Equation 1 and Equation 2 show the full-scale input range (FSR) and common-mode voltage (VCM), respectively, supported at the analog inputs for any external reference voltage provided on the REFIN pin (VREF).