SBAS650C May   2014  – April 2021 AFE4403

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Family Options
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Timing Requirements: Supply Ramp and Power-Down
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Receiver Channel
        1. 8.3.1.1 Receiver Front-End
        2. 8.3.1.2 Ambient Cancellation Scheme and Second Stage Gain Block
        3. 8.3.1.3 Receiver Control Signals
        4. 8.3.1.4 Receiver Timing
      2. 8.3.2 Clocking and Timing Signal Generation
      3. 8.3.3 Timer Module
        1. 8.3.3.1 Using the Timer Module
      4. 8.3.4 Receiver Subsystem Power Path
      5. 8.3.5 Transmit Section
        1. 8.3.5.1 Third LED Support
        2. 8.3.5.2 Transmitter Power Path
        3. 8.3.5.3 LED Power Reduction During Periods of Inactivity
        4. 8.3.5.4 LED Configurations
    4. 8.4 Device Functional Modes
      1. 8.4.1 ADC Operation and Averaging Module
        1. 8.4.1.1 Operation Without Averaging
        2. 8.4.1.2 Operation With Averaging
        3. 8.4.1.3 Dynamic Power-Down Mode
      2. 8.4.2 Diagnostics
        1. 8.4.2.1 Photodiode-Side Fault Detection
        2. 8.4.2.2 Transmitter-Side Fault Detection
        3. 8.4.2.3 Diagnostics Module
    5. 8.5 Programming
      1. 8.5.1 Serial Programming Interface
      2. 8.5.2 Reading and Writing Data
        1. 8.5.2.1 Writing Data
        2. 8.5.2.2 Reading Data
        3. 8.5.2.3 Multiple Data Reads and Writes
        4. 8.5.2.4 Register Initialization
        5. 8.5.2.5 AFE SPI Interface Design Considerations
    6. 8.6 Register Maps
      1. 8.6.1 AFE Register Map
      2. 8.6.2 AFE Register Description
  9. 9 Application Information Disclaimer
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Consumption Considerations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 Electrostatic Discharge Caution
    3. 12.3 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5 Electrical Characteristics

Minimum and maximum specifications are at TA = –20°C to 70°C, typical specifications are at 25°C. Crystal mode enabled, detector capacitor = 50 pF differential, ADC averaging set to maximum allowed for each PRF, TX_REF voltage set to 0.5 V, and CLKOUT tri-stated, at RX_ANA_SUP = RX_DIG_SUP = 3 V, TX_CTRL_SUP = LED_DRV_SUP = 3.3 V, stage 2 amplifier disabled, and fCLK = 8 MHz, unless otherwise noted.
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
PERFORMANCE (Full-Signal Chain)
IIN_FSFull-scale input currentRF = 10 kΩ50µA
RF = 25 kΩ20µA
RF = 50 kΩ10µA
RF = 100 kΩ5µA
RF = 250 kΩ2µA
RF = 500 kΩ1µA
RF = 1 MΩ0.5µA
PRFPulse repetition frequency62.52000SPS
DCPRFPRF duty cycle25%
CMRRCommon-mode rejection ratiofCM = 50 Hz and 60 Hz, LED1 and LED2 with
RSERIES = 500 kΩ, RF = 500 kΩ		75dB
fCM = 50 Hz and 60 Hz, LED1-AMB and LED2-AMB with RSERIES = 500 kΩ, RF = 500 kΩ95dB
PSRRLEDPSRR, transmit LED driverWith respect to ripple on LED_DRV_SUP75dB
PSRRTxPSRR, transmit controlWith respect to ripple on TX_CTRL_SUP60dB
PSRRRxPSRR, receiverWith respect to ripple on RX_ANA_SUP and RX_DIG_SUP60dB
Total integrated noise current, input-referred (receiver with transmitter loop back, 0.1-Hz to 20-Hz bandwidth)RF = 100 kΩ, PRF = 600 Hz, duty cycle = 5%25pARMS
RF = 500 kΩ, PRF = 600 Hz, duty cycle = 5%6pARMS
RECEIVER FUNCTIONAL BLOCK LEVEL SPECIFICATION
Total integrated noise current, input referred (receiver alone) over 0.1-Hz to 20-Hz bandwidthRF = 500 kΩ, ambient cancellation enabled,
stage 2 gain = 4, PRF = 1200 Hz, LED duty cycle = 25%		3.2pARMS
RF = 500 kΩ, ambient cancellation enabled,
stage 2 gain = 4, PRF = 1200 Hz, LED duty cycle = 5%		5.3pARMS
I-V TRANSIMPEDANCE AMPLIFIER
GGainRF = 10 kΩ to 1 MΩSee the Receiver Channel section for detailsV/µA
Gain accuracy±7%
Feedback resistanceRF10k, 25k, 50k, 100k, 250k,
500k, and 1M		Ω
Feedback resistor toleranceRF±20%
Feedback capacitanceCF5, 10, 25, 50, 100, and 250pF
Feedback capacitor toleranceCF±20%
Full-scale differential output voltage1V
Common-mode voltage on input pinsSet internally0.9V
External differential input capacitanceIncludes equivalent capacitance of photodiode, cables,
EMI filter, and so forth		101000pF
Shield output voltage, VCMWith a 1-kΩ series resistor and a 10-nF decoupling capacitor to ground0.80.91V
AMBIENT CANCELLATION STAGE
Gain0, 3.5, 6, 9.5, and 12dB
Current DAC range010µA
Current DAC step size1µA
LOW-PASS FILTER
Low-pass corner frequency3-dB attenuation500Hz
Pass-band attenuation, 2 Hz to 10 HzDuty cycle = 25%0.004dB
Duty cycle = 10%0.041dB
Filter settling timeAfter diagnostics mode28ms
ANALOG-TO-DIGITAL CONVERTER
Resolution22Bits
Sample rateSee the ADC Operation and Averaging Module section4 × PRFSPS
ADC full-scale voltage±1.2V
ADC conversion timeSee the ADC Operation and Averaging Module sectionPRF / 4µs
ADC reset time(2)2tCLK
TRANSMITTER
Output current rangeSelectable, 0 to 100
(see the LEDCNTRL: LED Control Register for details)		mA
LED current DAC error±10%
Output current resolution8Bits
Transmitter noise dynamic range,
over 0.1-Hz to 20-Hz bandwidth,
TX_REF set to 0.5 V		At 25-mA output current110dB
At 50-mA output current110dB
Minimum sample time of LED1 and LED2 pulses50µs
LED current DAC leakage currentLED_ON = 01µA
LED_ON = 150µA
LED current DAC linearityPercent of full-scale current0.50%
Output current settling time
(with resistive load)		From zero current to 50 mA7µs
From 50 mA to zero current7µs
DIAGNOSTICS
Duration of diagnostics state machineStart of diagnostics after the DIAG_EN register bit is set.
End of diagnostic is indicated by DIAG_END going high.		16ms
Open fault resistance> 100kΩ
Short fault resistance< 10kΩ
INTERNAL OSCILLATOR
fCLKOUTCLKOUT frequencyWith an 8-MHz crystal connected to the XIN, XOUT pins4MHz
CLKOUT duty cycle50%
Crystal oscillator start-up timeWith an 8-MHz crystal connected to the XIN, XOUT pins200µs
EXTERNAL CLOCK
Maximum allowable external clock jitterFor SPO2 applications50ps
For optical heart rate only1000ps
External clock input frequency (1)±2%4860MHz
External clock input voltageVoltage input high (VIH)0.75 × RX_DIG_SUPV
Voltage input low (VIL)0.25 × RX_DIG_SUPV
TIMING
Wake-up time from complete
power-down		1000ms
Wake-up time from Rx power-down100µs
Wake-up time from Tx power-down1000ms
tRESETActive low RESET pulse duration1ms
tDIAGENDDIAG_END pulse duration at the completion of diagnostics4CLKOUT cycles
tADCRDYADC_RDY pulse duration1CLKOUT cycle
DIGITAL SIGNAL CHARACTERISTICS
VIHLogic high input voltageAFE_ PDN, SCLK, SPISIMO, SPISTE, RESET0.8 DVDD> 1.3DVDD + 0.1V
VILLogic low input voltageAFE_ PDN, SCLK, SPISIMO, SPISTE, RESET–0.1< 0.40.2 DVDDV
IINLogic input current0 V < VDigitalInput < DVDD–1010µA
VOHLogic high output voltageDIAG_END, SPISOMI, ADC_RDY, CLKOUT0.9 DVDD> (RX_DIG_SUP –
0.2 V)		V
VOLLogic low output voltageDIAG_END, SPISOMI, ADC_RDY, CLKOUT< 0.40.1 DVDDV
SUPPLY CURRENT
Receiver analog supply currentRX_ANA_SUP = 3.0 V, with 8-MHz clock running,
Rx stage 2 disabled		0.6mA
RX_ANA_SUP = 3.0 V, with 8-MHz clock running,
Rx stage 2 enabled		0.7mA
RX_ANA_SUP = 3.0 V, with 8-MHz clock running,
Rx stage 2 disabled, external clock mode		0.49mA
Receiver digital supply currentRX_DIG_SUP = 3.0 V0.15mA
LED driver supply currentWith zero LED current setting30µA
Transmitter control supply current15µA
Complete power-down
(using the AFE_ PDN pin)		Receiver current only (RX_ANA_SUP)3µA
Receiver current only (RX_DIG_SUP)3µA
Transmitter current only (LED_DRV_SUP)1µA
Transmitter current only (TX_CTRL_SUP)1µA
Power-down Rx aloneReceiver current only (RX_ANA_SUP)200µA
Receiver current only (RX_DIG_SUP)150µA
Power-down Tx aloneTransmitter current only (LED_DRV_SUP)2µA
Transmitter current only (TX_CTRL_SUP)2µA
POWER DISSIPATION
Power-down with the AFE_PDN pinLED_DRV_SUPDoes not include LED current.1µA
TX_CTRL_SUP1µA
RX_ANA_SUP5µA
RX_DIG_SUP0.1µA
Power-down with the PDNAFE register bitLED_DRV_SUPDoes not include LED current.1µA
TX_CTRL_SUP1µA
RX_ANA_SUP15µA
RX_DIG_SUP20µA
Power-down RxLED_DRV_SUPDoes not include LED current.30µA
TX_CTRL_SUP15µA
RX_ANA_SUP200µA
RX_DIG_SUP150µA
Power-down TxLED_DRV_SUPDoes not include LED current.2µA
TX_CTRL_SUP2µA
RX_ANA_SUP600µA
RX_DIG_SUP150µA
After reset, with 8-MHz clock runningLED_DRV_SUPDoes not include LED current.30µA
TX_CTRL_SUP15µA
RX_ANA_SUP600µA
RX_DIG_SUP150µA
With stage 2 mode enabled and 8-MHz clock runningLED_DRV_SUPDoes not include LED current.30µA
TX_CTRL_SUP15µA
RX_ANA_SUP700µA
RX_DIG_SUP150µA
Dynamic power-down mode enabledLED_DRV_SUPDoes not include LED current.PRF = 100 Hz,
PDN_CYCLE duration = 8 ms		7µA
TX_CTRL_SUP5µA
RX_ANA_SUP205µA
RX_DIG_SUP150µA
(1) Refer to the CLKDIV[2:0] register bits for a detailed list of input clock frequencies that are supported.
(2) A low ADC reset time can result in a small component of the LED signal leaking into the ambient phase. With an ADC reset of two clock cycles, a –60-dB leakage is expected. In many cases, this leakage does not affect system performance. However, if this crosstalk must be completely eliminated, a longer ADC reset time of approximately six clock cycles is recommended for t22, t24, t26, and t28 in Figure 8-13.