SPRS851E June   2014  – January 2019 AM4372 , AM4376 , AM4377 , AM4378 , AM4379

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
      1. Table 4-1 ZDN Ball Map [Section Top Left - Top View]
      2. Table 4-2 ZDN Ball Map [Section Top Middle - Top View]
      3. Table 4-3 ZDN Ball Map [Section Top Right - Top View]
      4. Table 4-4 ZDN Ball Map [Section Middle Left - Top View]
      5. Table 4-5 ZDN Ball Map [Section Middle Middle - Top View]
      6. Table 4-6 ZDN Ball Map [Section Middle Right - Top View]
      7. Table 4-7 ZDN Ball Map [Section Bottom Left - Top View]
      8. Table 4-8 ZDN Ball Map [Section Bottom Middle - Top View]
      9. Table 4-9 ZDN Ball Map [Section Bottom Right - Top View]
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. 4.3.1  ADC Interfaces
      2. 4.3.2  CAN Interfaces
      3. 4.3.3  Camera (VPFE) Interfaces
      4. 4.3.4  Debug Subsystem Interface
      5. 4.3.5  Display Subsystem (DSS) Interface
      6. 4.3.6  Ethernet (GEMAC_CPSW) Interfaces
      7. 4.3.7  External Memory Interfaces
      8. 4.3.8  General Purpose IOs
      9. 4.3.9  HDQ Interface
      10. 4.3.10 I2C Interfaces
      11. 4.3.11 McASP Interfaces
      12. 4.3.12 Miscellaneous
      13. 4.3.13 PRU-ICSS0 Interface
      14. 4.3.14 PRU-ICSS1 Interface
      15. 4.3.15 QSPI Interface
      16. 4.3.16 RTC Subsystem Interface
      17. 4.3.17 Removable Media Interfaces
      18. 4.3.18 SPI Interfaces
      19. 4.3.19 Timer Interfaces
      20. 4.3.20 UART Interfaces
      21. 4.3.21 USB Interfaces
      22. 4.3.22 eCAP Interfaces
      23. 4.3.23 eHRPWM Interfaces
      24. 4.3.24 eQEP Interfaces
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Power-On Hours (POH)
    4. 5.4  Operating Performance Points
    5. 5.5  Recommended Operating Conditions
    6. 5.6  Power Consumption Summary
    7. 5.7  DC Electrical Characteristics
    8. 5.8  ADC0: Touch Screen Controller and Analog-to-Digital Subsystem Electrical Parameters
    9. 5.9  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. Table 5-6 Recommended Operating Conditions for OTP eFuse Programming
      2. 5.9.1     Hardware Requirements
      3. 5.9.2     Programming Sequence
      4. 5.9.3     Impact to Your Hardware Warranty
    10. 5.10 Thermal Resistance Characteristics
      1. Table 5-7 Thermal Resistance Characteristics (NFBGA Package) [ZDN]
    11. 5.11 External Capacitors
      1. 5.11.1 Voltage Decoupling Capacitors
        1. 5.11.1.1 Core Voltage Decoupling Capacitors
        2. 5.11.1.2 IO and Analog Voltage Decoupling Capacitors
      2. 5.11.2 Output Capacitors
    12. 5.12 Timing and Switching Characteristics
      1. 5.12.1  Power Supply Sequencing
        1. 5.12.1.1 Power Supply Slew Rate Requirement
        2. 5.12.1.2 Power-Up Sequencing
        3. 5.12.1.3 Power-Down Sequencing
      2. 5.12.2  Clock
        1. 5.12.2.1 PLLs
          1. 5.12.2.1.1 Digital Phase-Locked Loop Power Supply Requirements
        2. 5.12.2.2 Input Clock Specifications
        3. 5.12.2.3 Input Clock Requirements
          1. 5.12.2.3.1 OSC0 Internal Oscillator Clock Source
            1. Table 5-12 OSC0 Crystal Circuit Requirements
            2. Table 5-13 OSC0 Crystal Circuit Characteristics
          2. 5.12.2.3.2 OSC0 LVCMOS Digital Clock Source
          3. 5.12.2.3.3 OSC1 Internal Oscillator Clock Source
            1. Table 5-15 OSC1 Crystal Circuit Requirements
            2. Table 5-16 OSC1 Crystal Circuit Characteristics
          4. 5.12.2.3.4 OSC1 LVCMOS Digital Clock Source
          5. 5.12.2.3.5 OSC1 Not Used
        4. 5.12.2.4 Output Clock Specifications
        5. 5.12.2.5 Output Clock Characteristics
          1. 5.12.2.5.1 CLKOUT1
          2. 5.12.2.5.2 CLKOUT2
      3. 5.12.3  Timing Parameters and Board Routing Analysis
      4. 5.12.4  Recommended Clock and Control Signal Transition Behavior
      5. 5.12.5  Controller Area Network (CAN)
        1. 5.12.5.1 DCAN Electrical Data and Timing
          1. Table 5-18 Timing Requirements for DCANx Receive
          2. Table 5-19 Switching Characteristics for DCANx Transmit
      6. 5.12.6  DMTimer
        1. 5.12.6.1 DMTimer Electrical Data and Timing
          1. Table 5-20 Timing Requirements for DMTimer [1-11]
          2. Table 5-21 Switching Characteristics for DMTimer [4-7]
      7. 5.12.7  Ethernet Media Access Controller (EMAC) and Switch
        1. 5.12.7.1 Ethernet MAC and Switch Electrical Data and Timing
          1. Table 5-22 Ethernet MAC and Switch Timing Conditions
          2. 5.12.7.1.1 Ethernet MAC/Switch MDIO Electrical Data and Timing
            1. Table 5-23 Timing Requirements for MDIO_DATA
            2. Table 5-24 Switching Characteristics for MDIO_CLK
            3. Table 5-25 MDIO Switching Characteristics - MDIO_DATA
          3. 5.12.7.1.2 Ethernet MAC and Switch MII Electrical Data and Timing
            1. Table 5-26 Timing Requirements for GMII[x]_RXCLK - MII Mode
            2. Table 5-27 Timing Requirements for GMII[x]_TXCLK - MII Mode
            3. Table 5-28 Timing Requirements for GMII[x]_RXD[3:0], GMII[x]_RXDV, and GMII[x]_RXER - MII Mode
            4. Table 5-29 Switching Characteristics for GMII[x]_TXD[3:0], and GMII[x]_TXEN - MII Mode
          4. 5.12.7.1.3 Ethernet MAC and Switch RMII Electrical Data and Timing
            1. Table 5-30 Timing Requirements for RMII[x]_REFCLK - RMII Mode
            2. Table 5-31 Timing Requirements for RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RXER - RMII Mode
            3. Table 5-32 Switching Characteristics for RMII[x]_TXD[1:0], and RMII[x]_TXEN - RMII Mode
          5. 5.12.7.1.4 Ethernet MAC and Switch RGMII Electrical Data and Timing
            1. Table 5-33 Timing Requirements for RGMII[x]_RCLK - RGMII Mode
            2. Table 5-34 Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL - RGMII Mode
            3. Table 5-35 Switching Characteristics for RGMII[x]_TCLK - RGMII Mode
            4. Table 5-36 Switching Characteristics for RGMII[x]_TD[3:0], and RGMII[x]_TCTL - RGMII Mode
      8. 5.12.8  External Memory Interfaces
        1. 5.12.8.1 General-Purpose Memory Controller (GPMC)
          1. 5.12.8.1.1 GPMC and NOR Flash—Synchronous Mode
            1. Table 5-37 GPMC and NOR Flash Timing Conditions—Synchronous Mode
            2. Table 5-38 GPMC and NOR Flash Timing Requirements—Synchronous Mode
            3. Table 5-39 GPMC and NOR Flash Switching Characteristics—Synchronous Mode
          2. 5.12.8.1.2 GPMC and NOR Flash—Asynchronous Mode
            1. Table 5-40 GPMC and NOR Flash Timing Conditions—Asynchronous Mode
            2. Table 5-41 GPMC and NOR Flash Internal Timing Parameters—Asynchronous Mode
            3. Table 5-42 GPMC and NOR Flash Timing Requirements—Asynchronous Mode
            4. Table 5-43 GPMC and NOR Flash Switching Characteristics—Asynchronous Mode
          3. 5.12.8.1.3 GPMC and NAND Flash—Asynchronous Mode
            1. Table 5-44 GPMC and NAND Flash Timing Conditions—Asynchronous Mode
            2. Table 5-45 GPMC and NAND Flash Internal Timing Parameters—Asynchronous Mode
            3. Table 5-46 GPMC and NAND Flash Timing Requirements—Asynchronous Mode
            4. Table 5-47 GPMC and NAND Flash Switching Characteristics—Asynchronous Mode
        2. 5.12.8.2 Memory Interface
          1. 5.12.8.2.1 DDR3 and DDR3L Routing Guidelines
            1. 5.12.8.2.1.1 Board Designs
            2. 5.12.8.2.1.2 DDR3 Device Combinations
            3. 5.12.8.2.1.3 DDR3 Interface
              1. 5.12.8.2.1.3.1  DDR3 Interface Schematic
              2. 5.12.8.2.1.3.2  Compatible JEDEC DDR3 Devices
              3. 5.12.8.2.1.3.3  DDR3 PCB Stackup
              4. 5.12.8.2.1.3.4  DDR3 Placement
              5. 5.12.8.2.1.3.5  DDR3 Keepout Region
              6. 5.12.8.2.1.3.6  DDR3 Bulk Bypass Capacitors
              7. 5.12.8.2.1.3.7  DDR3 High-Speed Bypass Capacitors
                1. 5.12.8.2.1.3.7.1 Return Current Bypass Capacitors
              8. 5.12.8.2.1.3.8  DDR3 Net Classes
              9. 5.12.8.2.1.3.9  DDR3 Signal Termination
              10. 5.12.8.2.1.3.10 DDR3 DDR_VREF Routing
              11. 5.12.8.2.1.3.11 DDR3 VTT
            4. 5.12.8.2.1.4 DDR3 CK and ADDR_CTRL Topologies and Routing Definition
              1. 5.12.8.2.1.4.1 Using Two DDR3 Devices (x8 or x16)
                1. 5.12.8.2.1.4.1.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
                2. 5.12.8.2.1.4.1.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
              2. 5.12.8.2.1.4.2 Using Four 8-Bit DDR3 Devices
                1. 5.12.8.2.1.4.2.1 CK and ADDR_CTRL Topologies, Four DDR3 Devices
                2. 5.12.8.2.1.4.2.2 CK and ADDR_CTRL Routing, Four DDR3 Devices
              3. 5.12.8.2.1.4.3 One 16-Bit DDR3 Device
                1. 5.12.8.2.1.4.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device
                2. 5.12.8.2.1.4.3.2 CK and ADDR_CTRL Routing, One DDR3 Device
            5. 5.12.8.2.1.5 Data Topologies and Routing Definition
              1. 5.12.8.2.1.5.1 DQS[x] and DQ[x] Topologies, Any Number of Allowed DDR3 Devices
              2. 5.12.8.2.1.5.2 DQS[x] and DQ[x] Routing, Any Number of Allowed DDR3 Devices
            6. 5.12.8.2.1.6 Routing Specification
              1. 5.12.8.2.1.6.1 CK and ADDR_CTRL Routing Specification
              2. 5.12.8.2.1.6.2 DQS[x] and DQ[x] Routing Specification
          2. 5.12.8.2.2 LPDDR2 Routing Guidelines
            1. 5.12.8.2.2.1 LPDDR2 Board Designs
            2. 5.12.8.2.2.2 LPDDR2 Device Configurations
            3. 5.12.8.2.2.3 LPDDR2 Interface
              1. 5.12.8.2.2.3.1 LPDDR2 Interface Schematic
              2. 5.12.8.2.2.3.2 Compatible JEDEC LPDDR2 Devices
              3. 5.12.8.2.2.3.3 LPDDR2 PCB Stackup
              4. 5.12.8.2.2.3.4 LPDDR2 Placement
              5. 5.12.8.2.2.3.5 LPDDR2 Keepout Region
              6. 5.12.8.2.2.3.6 LPDDR2 Net Classes
              7. 5.12.8.2.2.3.7 LPDDR2 Signal Termination
              8. 5.12.8.2.2.3.8 LPDDR2 DDR_VREF Routing
            4. 5.12.8.2.2.4 Routing Specification
              1. 5.12.8.2.2.4.1 DQS[x] and DQ[x] Routing Specification
              2. 5.12.8.2.2.4.2 CK and ADDR_CTRL Routing Specification
      9. 5.12.9  Display Subsystem (DSS)
        1. 5.12.9.1 DSS—Parallel Interface
          1. 5.12.9.1.1 DSS—Parallel Interface—Bypass Mode
            1. 5.12.9.1.1.1 DSS—Parallel Interface—Bypass Mode—TFT Mode
            2. 5.12.9.1.1.2 DSS—Parallel Interface—Bypass Mode—STN Mode
          2. 5.12.9.1.2 DSS—Parallel Interface—RFBI Mode—Applications
            1. 5.12.9.1.2.1 DSS—Parallel Interface—RFBI Mode—MIPI DBI 2.0—LCD Panel
            2. 5.12.9.1.2.2 DSS—Parallel Interface—RFBI Mode—Pico DLP
      10. 5.12.10 Camera (VPFE)
        1. 5.12.10.1 Camera (VPFE) Timing
          1. Table 5-80 VPFE Timing Requirements
          2. Table 5-81 VPFE Output Switching Characteristics
      11. 5.12.11 Inter-Integrated Circuit (I2C)
        1. 5.12.11.1 I2C Electrical Data and Timing
          1. Table 5-82 I2C Timing Conditions - Slave Mode
          2. Table 5-83 Timing Requirements for I2C Input Timings
          3. Table 5-84 Switching Characteristics for I2C Output Timings
      12. 5.12.12 Multichannel Audio Serial Port (McASP)
        1. 5.12.12.1 McASP Device-Specific Information
        2. 5.12.12.2 McASP Electrical Data and Timing
          1. Table 5-85 McASP Timing Conditions
          2. Table 5-86 Timing Requirements for McASP
          3. Table 5-87 Switching Characteristics for McASP
      13. 5.12.13 Multichannel Serial Port Interface (McSPI)
        1. 5.12.13.1 McSPI Electrical Data and Timing
          1. 5.12.13.1.1 McSPI—Slave Mode
            1. Table 5-88 McSPI Timing Conditions—Slave Mode
            2. Table 5-89 Timing Requirements for McSPI Input Timings—Slave Mode
            3. Table 5-90 Switching Characteristics for McSPI Output Timings—Slave Mode
          2. 5.12.13.1.2 McSPI—Master Mode
            1. Table 5-91 McSPI Timing Conditions—Master Mode
            2. Table 5-92 Timing Requirements for McSPI Input Timings—Master Mode
            3. Table 5-93 Switching Characteristics for McSPI Output Timings—Master Mode
      14. 5.12.14 Quad Serial Port Interface (QSPI)
        1. Table 5-94 QSPI Switching Characteristics
      15. 5.12.15 HDQ/1-Wire Interface (HDQ/1-Wire)
        1. 5.12.15.1 HDQ Protocol
        2. 5.12.15.2 1-Wire Protocol
      16. 5.12.16 Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS)
        1. 5.12.16.1 Programmable Real-Time Unit (PRU-ICSS PRU)
          1. Table 5-99  PRU-ICSS PRU Timing Conditions
          2. 5.12.16.1.1 PRU-ICSS PRU Direct Input/Output Mode Electrical Data and Timing
            1. Table 5-100 PRU-ICSS PRU Timing Requirements - Direct Input Mode
            2. Table 5-101 PRU-ICSS PRU Switching Requirements - Direct Output Mode
          3. 5.12.16.1.2 PRU-ICSS PRU Parallel Capture Mode Electrical Data and Timing
            1. Table 5-102 PRU-ICSS PRU Timing Requirements - Parallel Capture Mode
          4. 5.12.16.1.3 PRU-ICSS PRU Shift Mode Electrical Data and Timing
            1. Table 5-103 PRU-ICSS PRU Timing Requirements - Shift In Mode
            2. Table 5-104 PRU-ICSS PRU Switching Requirements - Shift Out Mode
          5. 5.12.16.1.4 PRU-ICSS Sigma Delta Electrical Data and Timing
            1. Table 5-105 PRU-ICSS Timing Requirements - Sigma Delta Mode
          6. 5.12.16.1.5 PRU-ICSS ENDAT Electrical Data and Timing
            1. Table 5-106 PRU-ICSS Timing Requirements - ENDAT Mode
            2. Table 5-107 PRU-ICSS Switching Requirements - ENDAT Mode
        2. 5.12.16.2 PRU-ICSS EtherCAT (PRU-ICSS ECAT)
          1. Table 5-108 PRU-ICSS ECAT Timing Conditions
          2. 5.12.16.2.1 PRU-ICSS ECAT Electrical Data and Timing
            1. Table 5-109 PRU-ICSS ECAT Timing Requirements - Input Validated With LATCH_IN
            2. Table 5-110 PRU-ICSS ECAT Timing Requirements - Input Validated With SYNCx
            3. Table 5-111 PRU-ICSS ECAT Timing Requirements - Input Validated With Start of Frame (SOF)
            4. Table 5-112 PRU-ICSS ECAT Timing Requirements - LATCHx_IN
            5. Table 5-113 PRU-ICSS ECAT Switching Requirements - Digital IOs
        3. 5.12.16.3 PRU-ICSS MII_RT and Switch
          1. Table 5-114 PRU-ICSS MII_RT Switch Timing Conditions
          2. 5.12.16.3.1 PRU-ICSS MDIO Electrical Data and Timing
            1. Table 5-115 PRU-ICSS MDIO Timing Requirements - MDIO_DATA
            2. Table 5-116 PRU-ICSS MDIO Switching Characteristics - MDIO_CLK
            3. Table 5-117 PRU-ICSS MDIO Switching Characteristics - MDIO_DATA
          3. 5.12.16.3.2 PRU-ICSS MII_RT Electrical Data and Timing
            1. Table 5-118 PRU-ICSS MII_RT Timing Requirements - MII_RXCLK
            2. Table 5-119 PRU-ICSS MII_RT Timing Requirements - MII[x]_TXCLK
            3. Table 5-120 PRU-ICSS MII_RT Timing Requirements - MII_RXD[3:0], MII_RXDV, and MII_RXER
            4. Table 5-121 PRU-ICSS MII_RT Switching Characteristics - MII_TXD[3:0] and MII_TXEN
        4. 5.12.16.4 PRU-ICSS Universal Asynchronous Receiver Transmitter (PRU-ICSS UART)
          1. Table 5-122 Timing Requirements for PRU-ICSS UART Receive
          2. Table 5-123 Switching Characteristics Over Recommended Operating Conditions for PRU-ICSS UART Transmit
      17. 5.12.17 Multimedia Card (MMC) Interface
        1. 5.12.17.1 MMC Electrical Data and Timing
          1. Table 5-124 MMC Timing Conditions
          2. Table 5-125 Timing Requirements for MMC[0]_CMD and MMC[0]_DAT[7:0]
          3. Table 5-126 Timing Requirements for MMC[1/2]_CMD and MMC[1/2]_DAT[7:0]
          4. Table 5-127 Switching Characteristics for MMC[x]_CLK
          5. Table 5-128 Switching Characteristics for MMC[x]_CMD and MMC[x]_DAT[7:0]—HSPE=0
          6. Table 5-129 Switching Characteristics for MMC[x]_CMD and MMC[x]_DAT[7:0]—HSPE=1
      18. 5.12.18 Universal Asynchronous Receiver/Transmitter (UART)
        1. 5.12.18.1 UART Electrical Data and Timing
          1. Table 5-130 Timing Requirements for UARTx Receive
          2. Table 5-131 for UARTx Transmit
        2. 5.12.18.2 UART IrDA Interface
    13. 5.13 Emulation and Debug
      1. 5.13.1 IEEE 1149.1 JTAG
        1. 5.13.1.1 JTAG Electrical Data and Timing
          1. Table 5-134 Timing Requirements for JTAG
          2. Table 5-135 Switching Characteristics for JTAG
  6. 6Device and Documentation Support
    1. 6.1 Device Nomenclature
    2. 6.2 Tools and Software
    3. 6.3 Documentation Support
    4. 6.4 Related Links
    5. 6.5 Community Resources
    6. 6.6 Trademarks
    7. 6.7 Electrostatic Discharge Caution
    8. 6.8 Glossary
  7. 7Mechanical, Packaging, and Orderable Information
    1. 7.1 Via Channel
    2. 7.2 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ZDN|491
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4.3.8 General Purpose IOs

Table 4-29 GPIO0 Signal Descriptions

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZDN [4]
gpio0_0 GPIO IO A17, D16
gpio0_1 GPIO IO A15, B17
gpio0_2 GPIO IO M25, P23
gpio0_3 GPIO IO L24, T22
gpio0_4 GPIO IO A12, T21
gpio0_5 GPIO IO T20
gpio0_6 GPIO IO R25
gpio0_7 GPIO IO G24
gpio0_8 GPIO IO C19, D14
gpio0_9 GPIO IO D13, D19
gpio0_10 GPIO IO C14, C17
gpio0_11 GPIO IO D17, E16
gpio0_12 GPIO IO K22
gpio0_13 GPIO IO L22
gpio0_14 GPIO IO K21
gpio0_15 GPIO IO L21
gpio0_16 GPIO IO C16
gpio0_17 GPIO IO C13
gpio0_18 GPIO IO G21, L23
gpio0_19 GPIO IO D24, K23
gpio0_20 GPIO IO C24, P22
gpio0_21 GPIO IO A14, P20
gpio0_22 GPIO IO B10, N20
gpio0_23 GPIO IO A10, T23
gpio0_24 GPIO IO H20
gpio0_25 GPIO IO F25
gpio0_26 GPIO IO F11
gpio0_27 GPIO IO D11
gpio0_28 GPIO IO B15
gpio0_29 GPIO IO A16
gpio0_30 GPIO IO A2
gpio0_31 GPIO IO B3

Table 4-30 GPIO1 Signal Descriptions

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZDN [4]
gpio1_0 GPIO IO B5
gpio1_1 GPIO IO A5
gpio1_2 GPIO IO B6
gpio1_3 GPIO IO A6
gpio1_4 GPIO IO B7
gpio1_5 GPIO IO A7
gpio1_6 GPIO IO C8
gpio1_7 GPIO IO B8
gpio1_8 GPIO IO L25
gpio1_9 GPIO IO J25
gpio1_10 GPIO IO K25
gpio1_11 GPIO IO J24
gpio1_12 GPIO IO E11
gpio1_13 GPIO IO C11
gpio1_14 GPIO IO B11
gpio1_15 GPIO IO A11
gpio1_16 GPIO IO C3
gpio1_17 GPIO IO C5
gpio1_18 GPIO IO C6
gpio1_19 GPIO IO A4
gpio1_20 GPIO IO D7
gpio1_21 GPIO IO E7
gpio1_22 GPIO IO E8
gpio1_23 GPIO IO F6
gpio1_24 GPIO IO F7
gpio1_25 GPIO IO B4
gpio1_26 GPIO IO G8
gpio1_27 GPIO IO D8
gpio1_28 GPIO IO A3
gpio1_29 GPIO IO A8
gpio1_30 GPIO IO B9
gpio1_31 GPIO IO F10

Table 4-31 GPIO2 Signal Descriptions

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZDN [4]
gpio2_0 GPIO IO B12
gpio2_1 GPIO IO A12
gpio2_2 GPIO IO A9
gpio2_3 GPIO IO E10
gpio2_4 GPIO IO D10
gpio2_5 GPIO IO C10
gpio2_6 GPIO IO B22
gpio2_7 GPIO IO A21
gpio2_8 GPIO IO B21
gpio2_9 GPIO IO C21
gpio2_10 GPIO IO A20
gpio2_11 GPIO IO B20
gpio2_12 GPIO IO C20
gpio2_13 GPIO IO E19
gpio2_14 GPIO IO A19
gpio2_15 GPIO IO B19
gpio2_16 GPIO IO A18
gpio2_17 GPIO IO B18
gpio2_18 GPIO IO C14
gpio2_19 GPIO IO E16
gpio2_20 GPIO IO B16
gpio2_21 GPIO IO F17
gpio2_22 GPIO IO B23
gpio2_23 GPIO IO A23
gpio2_24 GPIO IO A22
gpio2_25 GPIO IO A24
gpio2_26 GPIO IO B1
gpio2_27 GPIO IO B2
gpio2_28 GPIO IO C2
gpio2_29 GPIO IO C1
gpio2_30 GPIO IO D1
gpio2_31 GPIO IO D2

Table 4-32 GPIO3 Signal Descriptions

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZDN [4]
gpio3_0 GPIO IO D16
gpio3_1 GPIO IO B14
gpio3_2 GPIO IO B13
gpio3_3 GPIO IO A13
gpio3_4 GPIO IO A15
gpio3_5 GPIO IO AB24
gpio3_6 GPIO IO Y22
gpio3_7 GPIO IO N23
gpio3_8 GPIO IO T24
gpio3_9 GPIO IO D14
gpio3_10 GPIO IO D13
gpio3_11 GPIO IO C16
gpio3_12 GPIO IO C13
gpio3_13 GPIO IO F25
gpio3_14 GPIO IO N24
gpio3_15 GPIO IO N22
gpio3_16 GPIO IO H23
gpio3_17 GPIO IO M24
gpio3_18 GPIO IO L23
gpio3_19 GPIO IO K23
gpio3_20 GPIO IO M25
gpio3_21 GPIO IO L24
gpio3_22 GPIO IO P22
gpio3_23 GPIO IO P20
gpio3_24 GPIO IO N20
gpio3_25 GPIO IO T23

Table 4-33 GPIO4 Signal Descriptions

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZDN [4]
gpio4_0 GPIO IO AE17
gpio4_1 GPIO IO AD18
gpio4_2 GPIO IO AC18
gpio4_3 GPIO IO AD17
gpio4_4 GPIO IO AC20
gpio4_5 GPIO IO AB19
gpio4_6 GPIO IO AA19
gpio4_7 GPIO IO AC24
gpio4_8 GPIO IO AD24
gpio4_9 GPIO IO AD25
gpio4_10 GPIO IO AC23
gpio4_11 GPIO IO AE21
gpio4_12 GPIO IO AC25
gpio4_13 GPIO IO AB25
gpio4_14 GPIO IO AB20
gpio4_15 GPIO IO AC21
gpio4_16 GPIO IO AD21
gpio4_17 GPIO IO AE22
gpio4_18 GPIO IO AD22
gpio4_19 GPIO IO AE23
gpio4_20 GPIO IO AD23
gpio4_21 GPIO IO AE24
gpio4_24 GPIO IO Y18
gpio4_25 GPIO IO AA18
gpio4_26 GPIO IO AE19
gpio4_27 GPIO IO AD19
gpio4_28 GPIO IO AE20
gpio4_29 GPIO IO AD20

Table 4-34 GPIO5 Signal Descriptions

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZDN [4]
gpio5_0 GPIO IO H22
gpio5_1 GPIO IO K24
gpio5_2 GPIO IO H25
gpio5_3 GPIO IO H24
gpio5_4 GPIO IO P25
gpio5_5 GPIO IO R24
gpio5_6 GPIO IO P24
gpio5_7 GPIO IO N25
gpio5_8 GPIO IO D25
gpio5_9 GPIO IO F24
gpio5_10 GPIO IO G20
gpio5_11 GPIO IO F23
gpio5_12 GPIO IO E25
gpio5_13 GPIO IO E24
gpio5_19 GPIO IO AE18
gpio5_20 GPIO IO AB18
gpio5_23 GPIO IO D11
gpio5_24 GPIO IO F11
gpio5_25 GPIO IO A10
gpio5_26 GPIO IO B10
gpio5_27 GPIO IO G21
gpio5_28 GPIO IO D24
gpio5_29 GPIO IO C24
gpio5_30 GPIO IO A2
gpio5_31 GPIO IO B3