SPRS982H December 2016 – December 2019 AM5746 , AM5748 , AM5749
Refer to the PDF data sheet for device specific package drawings
TI only supports board designs using DDR3 memory that follow the guidelines in this document. The switching characteristics and timing diagram for the DDR3 memory controller are shown in Table 7-2 and Figure 7-1.
|RAM1||tc(DDR_CLK)||Cycle time, DDR_CLK||1.5||2.5(1)||ns|