Refer to the PDF data sheet for device specific package drawings
The device contains five multimaster high speed (HS) inter-integrated circuit (I2C) controllers (I2Ci modules, where i = 1, 2, 3, 4, 5) each of which provides an interface between a local host (LH), such as a digital signal processor (DSP), and any I2C-bus-compatible device that connects through the I2C serial bus. External components attached to the I2C bus can serially transmit and receive up to 8 bits of data to and from the LH device through the 2-wire I2C interface.
Each multimaster HS I2C controller can be configured to act like a slave or master I2C-compatible device.
I2C1 and I2C2 controllers have dedicated I2C compliant open drain buffers, and support Fast mode (up to 400Kbps). I2C3, I2C4 and I2C5 controllers are multiplexed with standard LVCMOS IO and connected to emulate open drain. I2C emulation is achieved by configuring the LVCMOS buffers to output Hi-Z instead of driving high when transmitting logic 1. These controllers support HS mode (up to 3.4Mbps).
For more information, see Multimaster High Speed I2C Controller (I2C) section in the device TRM.