SPRS982H December   2016  – December 2019 AM5746 , AM5748 , AM5749

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. 4.3.1  VIP
      2. 4.3.2  DSS
      3. 4.3.3  HDMI
      4. 4.3.4  EMIF
      5. 4.3.5  GPMC
      6. 4.3.6  Timer
      7. 4.3.7  I2C
      8. 4.3.8  HDQ1W
      9. 4.3.9  UART
      10. 4.3.10 McSPI
      11. 4.3.11 QSPI
      12. 4.3.12 McASP
      13. 4.3.13 USB
      14. 4.3.14 SATA
      15. 4.3.15 PCIe
      16. 4.3.16 DCAN and MCAN
      17. 4.3.17 GMAC_SW
      18. 4.3.18 MLB
      19. 4.3.19 eMMC/SD/SDIO
      20. 4.3.20 GPIO
      21. 4.3.21 KBD
      22. 4.3.22 PWM
      23. 4.3.23 PRU-ICSS
      24. 4.3.24 Test Interfaces
      25. 4.3.25 System and Miscellaneous
        1. 4.3.25.1 Sysboot
        2. 4.3.25.2 PRCM
        3. 4.3.25.3 RTCSS
        4. 4.3.25.4 SDMA
        5. 4.3.25.5 INTC
        6. 4.3.25.6 Observability
        7. 4.3.25.7 Power Supplies
    4. 4.4 Pin Multiplexing
    5. 4.5 Connections for Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Power-On Hours (POH) Limits
      1. Table 5-1 Power-On Hours (POH) Limits
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Operating Performance Points
      1. 5.5.1 AVS and ABB Requirements
      2. 5.5.2 Voltage And Core Clock Specifications
      3. 5.5.3 Maximum Supported Frequency
    6. 5.6  Power Consumption Summary
    7. 5.7  Electrical Characteristics
      1. Table 5-7  LVCMOS DDR DC Electrical Characteristics
      2. Table 5-8  Dual Voltage LVCMOS I2C DC Electrical Characteristics
      3. Table 5-9  IQ1833 Buffers DC Electrical Characteristics
      4. Table 5-10 IHHV1833 Buffers DC Electrical Characteristics
      5. Table 5-11 LVCMOS OSC Buffers DC Electrical Characteristics
      6. Table 5-12 BC1833IHHV Buffers DC Electrical Characteristics
      7. Table 5-13 Dual Voltage SDIO1833 DC Electrical Characteristics
      8. Table 5-14 Dual Voltage LVCMOS DC Electrical Characteristics
      9. 5.7.1      HDMIPHY DC Electrical Characteristics
      10. 5.7.2      USBPHY DC Electrical Characteristics
      11. 5.7.3      SATAPHY DC Electrical Characteristics
      12. 5.7.4      PCIEPHY DC Electrical Characteristics
    8. 5.8  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. Table 5-15 Recommended Operating Conditions for OTP eFuse Programming
      2. 5.8.1      Hardware Requirements
      3. 5.8.2      Programming Sequence
      4. 5.8.3      Impact to Your Hardware Warranty
    9. 5.9  Thermal Characteristics
      1. 5.9.1 Package Thermal Characteristics
    10. 5.10 Timing Requirements and Switching Characteristics
      1. 5.10.1 Timing Parameters and Information
        1. 5.10.1.1 Parameter Information
          1. 5.10.1.1.1 1.8V and 3.3V Signal Transition Levels
          2. 5.10.1.1.2 1.8V and 3.3V Signal Transition Rates
          3. 5.10.1.1.3 Timing Parameters and Board Routing Analysis
      2. 5.10.2 Interface Clock Specifications
        1. 5.10.2.1 Interface Clock Terminology
        2. 5.10.2.2 Interface Clock Frequency
      3. 5.10.3 Power Supply Sequences
      4. 5.10.4 Clock Specifications
        1. 5.10.4.1 Input Clocks / Oscillators
          1. 5.10.4.1.1 OSC0 External Crystal
          2. 5.10.4.1.2 OSC0 Input Clock
          3. 5.10.4.1.3 Auxiliary Oscillator OSC1 Input Clock
            1. 5.10.4.1.3.1 OSC1 External Crystal
            2. 5.10.4.1.3.2 OSC1 Input Clock
          4. 5.10.4.1.4 RTC Oscillator Input Clock
            1. 5.10.4.1.4.1 RTC Oscillator External Crystal
            2. 5.10.4.1.4.2 RTC Oscillator Input Clock
        2. 5.10.4.2 RC On-die Oscillator Clock
        3. 5.10.4.3 Output Clocks
        4. 5.10.4.4 DPLLs, DLLs
          1. 5.10.4.4.1 DPLL Characteristics
          2. 5.10.4.4.2 DLL Characteristics
      5. 5.10.5 Recommended Clock and Control Signal Transition Behavior
      6. 5.10.6 Peripherals
        1. 5.10.6.1  Timing Test Conditions
        2. 5.10.6.2  Virtual and Manual I/O Timing Modes
        3. 5.10.6.3  VIP
        4. 5.10.6.4  DSS
        5. 5.10.6.5  HDMI
        6. 5.10.6.6  EMIF
        7. 5.10.6.7  GPMC
          1. 5.10.6.7.1 GPMC/NOR Flash Interface Synchronous Timing
          2. 5.10.6.7.2 GPMC/NOR Flash Interface Asynchronous Timing
          3. 5.10.6.7.3 GPMC/NAND Flash Interface Asynchronous Timing
        8. 5.10.6.8  I2C
          1. Table 5-65 Timing Requirements for I2C Input Timings
          2. Table 5-66 Timing Requirements for I2C HS-Mode (I2C3/4/5 Only)
          3. Table 5-67 Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings
        9. 5.10.6.9  HDQ1W
          1. 5.10.6.9.1 HDQ / 1-Wire — HDQ Mode
          2. 5.10.6.9.2 HDQ/1-Wire—1-Wire Mode
        10. 5.10.6.10 UART
          1. Table 5-72 Timing Requirements for UART
          2. Table 5-73 Switching Characteristics Over Recommended Operating Conditions for UART
        11. 5.10.6.11 McSPI
        12. 5.10.6.12 QSPI
        13. 5.10.6.13 McASP
          1. Table 5-80 Timing Requirements for McASP1
          2. Table 5-81 Timing Requirements for McASP2
          3. Table 5-82 Timing Requirements for McASP3/4/5/6/7/8
          4. Table 5-83 Switching Characteristics Over Recommended Operating Conditions for McASP1
          5. Table 5-84 Switching Characteristics Over Recommended Operating Conditions for McASP2
          6. Table 5-85 Switching Characteristics Over Recommended Operating Conditions for McASP3/4/5/6/7/8
        14. 5.10.6.14 USB
          1. 5.10.6.14.1 USB1 DRD PHY
          2. 5.10.6.14.2 USB2 PHY
        15. 5.10.6.15 SATA
        16. 5.10.6.16 PCIe
        17. 5.10.6.17 CAN
          1. 5.10.6.17.1 DCAN
          2. 5.10.6.17.2 MCAN-FD
          3. Table 5-97  Timing Requirements for CANx Receive
          4. Table 5-98  Switching Characteristics Over Recommended Operating Conditions for CANx Transmit
        18. 5.10.6.18 GMAC_SW
          1. 5.10.6.18.1 GMAC MII Timings
            1. Table 5-99  Timing Requirements for miin_rxclk - MII Operation
            2. Table 5-100 Timing Requirements for miin_txclk - MII Operation
            3. Table 5-101 Timing Requirements for GMAC MIIn Receive 10/100 Mbit/s
            4. Table 5-102 Switching Characteristics Over Recommended Operating Conditions for GMAC MIIn Transmit 10/100 Mbits/s
          2. 5.10.6.18.2 GMAC MDIO Interface Timings
          3. 5.10.6.18.3 GMAC RMII Timings
            1. Table 5-107 Timing Requirements for GMAC REF_CLK - RMII Operation
            2. Table 5-108 Timing Requirements for GMAC RMIIn Receive
            3. Table 5-109 Switching Characteristics Over Recommended Operating Conditions for GMAC REF_CLK - RMII Operation
            4. Table 5-110 Switching Characteristics Over Recommended Operating Conditions for GMAC RMIIn Transmit 10/100 Mbits/s
          4. 5.10.6.18.4 GMAC RGMII Timings
            1. Table 5-114 Timing Requirements for rgmiin_rxc - RGMIIn Operation
            2. Table 5-115 Timing Requirements for GMAC RGMIIn Input Receive for 10/100/1000 Mbps
            3. Table 5-116 Switching Characteristics Over Recommended Operating Conditions for rgmiin_txctl - RGMIIn Operation for 10/100/1000 Mbit/s
            4. Table 5-117 Switching Characteristics for GMAC RGMIIn Output Transmit for 10/100/1000 Mbps
        19. 5.10.6.19 eMMC/SD/SDIO
          1. 5.10.6.19.1 MMC1—SD Card Interface
            1. 5.10.6.19.1.1 Default speed, 4-bit data, SDR, half-cycle
            2. 5.10.6.19.1.2 High speed, 4-bit data, SDR, half-cycle
            3. 5.10.6.19.1.3 SDR12, 4-bit data, half-cycle
            4. 5.10.6.19.1.4 SDR25, 4-bit data, half-cycle
            5. 5.10.6.19.1.5 UHS-I SDR50, 4-bit data, half-cycle
            6. 5.10.6.19.1.6 UHS-I SDR104, 4-bit data, half-cycle
            7. 5.10.6.19.1.7 UHS-I DDR50, 4-bit data
          2. 5.10.6.19.2 MMC2 — eMMC
            1. 5.10.6.19.2.1 Standard JC64 SDR, 8-bit data, half cycle
            2. 5.10.6.19.2.2 High Speed JC64 SDR, 8-bit data, half cycle
            3. 5.10.6.19.2.3 High Speed HS200 JC64 SDR, 8-bit data, half cycle
            4. 5.10.6.19.2.4 High Speed JC64 DDR, 8-bit data
          3. 5.10.6.19.3 MMC3 and MMC4—SDIO/SD
            1. 5.10.6.19.3.1 MMC3 and MMC4, SD Default Speed
            2. 5.10.6.19.3.2 MMC3 and MMC4, SD High Speed
            3. 5.10.6.19.3.3 MMC3 and MMC4, SD and SDIO SDR12 Mode
            4. 5.10.6.19.3.4 MMC3 and MMC4, SD SDR25 Mode
            5. 5.10.6.19.3.5 MMC3 SDIO High Speed UHS-I SDR50 Mode, Half Cycle
        20. 5.10.6.20 PRU-ICSS
          1. 5.10.6.20.1 Programmable Real-Time Unit (PRU-ICSS PRU)
            1. 5.10.6.20.1.1 PRU-ICSS PRU Direct Input/Output Mode Electrical Data and Timing
              1. Table 5-166 PRU-ICSS PRU Timing Requirements - Direct Input Mode
              2. Table 5-167 PRU-ICSS PRU Switching Requirements – Direct Output Mode
            2. 5.10.6.20.1.2 PRU-ICSS PRU Parallel Capture Mode Electrical Data and Timing
              1. Table 5-168 PRU-ICSS PRU Timing Requirements - Parallel Capture Mode
            3. 5.10.6.20.1.3 PRU-ICSS PRU Shift Mode Electrical Data and Timing
              1. Table 5-169 PRU-ICSS PRU Timing Requirements – Shift In Mode
              2. Table 5-170 PRU-ICSS PRU Switching Requirements - Shift Out Mode
            4. 5.10.6.20.1.4 PRU-ICSS PRU Sigma Delta and EnDAT Modes
              1. Table 5-171 PRU-ICSS PRU Timing Requirements - Sigma Delta Mode
              2. Table 5-172 PRU-ICSS PRU Timing Requirements - EnDAT Mode
              3. Table 5-173 PRU-ICSS PRU Switching Requirements - EnDAT Mode
          2. 5.10.6.20.2 PRU-ICSS EtherCAT (PRU-ICSS ECAT)
            1. 5.10.6.20.2.1 PRU-ICSS ECAT Electrical Data and Timing
              1. Table 5-174 PRU-ICSS ECAT Timing Requirements – Input Validated With LATCH_IN
              2. Table 5-175 PRU-ICSS ECAT Timing Requirements – Input Validated With SYNCx
              3. Table 5-176 PRU-ICSS ECAT Timing Requirements – Input Validated With Start of Frame (SOF)
              4. Table 5-177 PRU-ICSS ECAT Timing Requirements - LATCHx_IN
              5. Table 5-178 PRU-ICSS ECAT Switching Requirements - Digital IOs
          3. 5.10.6.20.3 PRU-ICSS MII_RT and Switch
            1. 5.10.6.20.3.1 PRU-ICSS MDIO Electrical Data and Timing
              1. Table 5-179 PRU-ICSS MDIO Timing Requirements – MDIO_DATA
              2. Table 5-180 PRU-ICSS MDIO Switching Characteristics - MDIO_CLK
              3. Table 5-181 PRU-ICSS MDIO Switching Characteristics – MDIO_DATA
            2. 5.10.6.20.3.2 PRU-ICSS MII_RT Electrical Data and Timing
              1. Table 5-182 PRU-ICSS MII_RT Timing Requirements – MII[x]_RXCLK
              2. Table 5-183 PRU-ICSS MII_RT Timing Requirements - MII[x]_TXCLK
              3. Table 5-184 PRU-ICSS MII_RT Timing Requirements - MII_RXD[3:0], MII_RXDV, and MII_RXER
              4. Table 5-185 PRU-ICSS MII_RT Switching Characteristics - MII_TXD[3:0] and MII_TXEN
          4. 5.10.6.20.4 PRU-ICSS Universal Asynchronous Receiver Transmitter (PRU-ICSS UART)
            1. Table 5-186 Timing Requirements for PRU-ICSS UART Receive
            2. Table 5-187 Switching Characteristics Over Recommended Operating Conditions for PRU-ICSS UART Transmit
          5. 5.10.6.20.5 PRU-ICSS IOSETs
          6. 5.10.6.20.6 PRU-ICSS Manual Functional Mapping
        21. 5.10.6.21 System and Miscellaneous interfaces
      7. 5.10.7 Emulation and Debug Subsystem
        1. 5.10.7.1 JTAG
          1. 5.10.7.1.1 JTAG Electrical Data/Timing
            1. Table 5-210 Timing Requirements for IEEE 1149.1 JTAG
            2. Table 5-211 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
            3. Table 5-212 Timing Requirements for IEEE 1149.1 JTAG With RTCK
            4. Table 5-213 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG With RTCK
        2. 5.10.7.2 TPIU
          1. 5.10.7.2.1 TPIU PLL DDR Mode
  6. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 Processor Subsystems
      1. 6.2.1 MPU
      2. 6.2.2 DSP Subsystem
      3. 6.2.3 IPU
      4. 6.2.4 Interrupt Controller
      5. 6.2.5 VPE
    3. 6.3 Accelerators and Coprocessors
      1. 6.3.1 IVA
      2. 6.3.2 GPU
      3. 6.3.3 PRU-ICSS
      4. 6.3.4 EVE
    4. 6.4 Other Subsystems
      1. 6.4.1 Memory Subsystem
        1. 6.4.1.1 EMIF
        2. 6.4.1.2 GPMC
        3. 6.4.1.3 ELM
        4. 6.4.1.4 OCMC
        5. 6.4.1.5 Interprocessor Communication
          1. 6.4.1.5.1 Mailbox
          2. 6.4.1.5.2 Spinlock
      2. 6.4.2 EDMA
      3. 6.4.3 Peripherals
        1. 6.4.3.1  VIP
        2. 6.4.3.2  DSS
        3. 6.4.3.3  Timers
        4. 6.4.3.4  I2C
        5. 6.4.3.5  HDQ1W
        6. 6.4.3.6  UART
          1. 6.4.3.6.1 UART Features
          2. 6.4.3.6.2 IrDA Features
          3. 6.4.3.6.3 CIR Features
        7. 6.4.3.7  McSPI
        8. 6.4.3.8  QSPI
        9. 6.4.3.9  McASP
        10. 6.4.3.10 USB
        11. 6.4.3.11 SATA
        12. 6.4.3.12 PCIe
        13. 6.4.3.13 CAN
          1. 6.4.3.13.1 DCAN
          2. 6.4.3.13.2 MCAN-FD
        14. 6.4.3.14 GMAC_SW
        15. 6.4.3.15 eMMC/SD/SDIO
        16. 6.4.3.16 GPIO
        17. 6.4.3.17 ePWM
        18. 6.4.3.18 eCAP
        19. 6.4.3.19 eQEP
      4. 6.4.4 On-Chip Debug
    5. 6.5 Identification
      1. 6.5.1 Revision Identification
      2. 6.5.2 Die Identification
      3. 6.5.3 JTAG Identification
      4. 6.5.4 ROM Code Identification
    6. 6.6 Boot Modes
      1. 6.6.1 Boot Mode List
      2. 6.6.2 Boot Mode Pin Usage
        1. 6.6.2.1 GPMC Configuration for XIP/NAND
        2. 6.6.2.2 System Clock Speed Selection
        3. 6.6.2.3 QSPI Redundant SBL Images Offset
      3. 6.6.3 Boot Mode Selection
        1. 6.6.3.1 Booting Device Order Selection
  7. 7Applications, Implementation, and Layout
    1. 7.1 Power Supply Mapping
    2. 7.2 DDR3 Board Design and Layout Guidelines
      1. 7.2.1 DDR3 General Board Layout Guidelines
      2. 7.2.2 DDR3 Board Design and Layout Guidelines
        1. 7.2.2.1  Board Designs
        2. 7.2.2.2  DDR3 EMIFs
        3. 7.2.2.3  DDR3 Device Combinations
        4. 7.2.2.4  DDR3 Interface Schematic
          1. 7.2.2.4.1 32-Bit DDR3 Interface
          2. 7.2.2.4.2 16-Bit DDR3 Interface
        5. 7.2.2.5  Compatible JEDEC DDR3 Devices
        6. 7.2.2.6  PCB Stackup
        7. 7.2.2.7  Placement
        8. 7.2.2.8  DDR3 Keepout Region
        9. 7.2.2.9  Bulk Bypass Capacitors
        10. 7.2.2.10 High Speed Bypass Capacitors
          1. 7.2.2.10.1 Return Current Bypass Capacitors
        11. 7.2.2.11 Net Classes
        12. 7.2.2.12 DDR3 Signal Termination
        13. 7.2.2.13 VREF_DDR Routing
        14. 7.2.2.14 VTT
        15. 7.2.2.15 CK and ADDR_CTRL Topologies and Routing Definition
          1. 7.2.2.15.1 Four DDR3 Devices
            1. 7.2.2.15.1.1 CK and ADDR_CTRL Topologies, Four DDR3 Devices
            2. 7.2.2.15.1.2 CK and ADDR_CTRL Routing, Four DDR3 Devices
          2. 7.2.2.15.2 Two DDR3 Devices
            1. 7.2.2.15.2.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
            2. 7.2.2.15.2.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
          3. 7.2.2.15.3 One DDR3 Device
            1. 7.2.2.15.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device
            2. 7.2.2.15.3.2 CK and ADDR/CTRL Routing, One DDR3 Device
        16. 7.2.2.16 Data Topologies and Routing Definition
          1. 7.2.2.16.1 DQS and DQ/DM Topologies, Any Number of Allowed DDR3 Devices
          2. 7.2.2.16.2 DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices
        17. 7.2.2.17 Routing Specification
          1. 7.2.2.17.1 CK and ADDR_CTRL Routing Specification
          2. 7.2.2.17.2 DQS and DQ Routing Specification
    3. 7.3 High Speed Differential Signal Routing Guidance
    4. 7.4 Power Distribution Network Implementation Guidance
    5. 7.5 Thermal Solution Guidance
    6. 7.6 Single-Ended Interfaces
      1. 7.6.1 General Routing Guidelines
      2. 7.6.2 QSPI Board Design and Layout Guidelines
    7. 7.7 LJCB_REFN/P Connections
    8. 7.8 Clock Routing Guidelines
      1. 7.8.1 32-kHz Oscillator Routing
      2. 7.8.2 Oscillator Ground Connection
  8. 8Device and Documentation Support
    1. 8.1 Device Nomenclature
      1. 8.1.1 Standard Package Symbolization
      2. 8.1.2 Device Naming Convention
    2. 8.2 Tools and Software
    3. 8.3 Documentation Support
    4. 8.4 Related Links
    5. 8.5 Support Resources
    6. 8.6 Trademarks
    7. 8.7 Electrostatic Discharge Caution
    8. 8.8 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ABZ|760
Thermal pad, mechanical data (Package|Pins)
Orderable Information
NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT
ASP9 tc(AHCLKX) Cycle time, AHCLKX 20 ns
ASP10 tw(AHCLKX) Pulse duration, AHCLKX high or low 0.5P - 2.5 (2) ns
ASP11 tc(ACLKRX) Cycle time, ACLKR/X 20 ns
ASP12 tw(ACLKRX) Pulse duration, ACLKR/X high or low 0.5R(3) - 2.5 ns
ASP13 td(ACLK-AFSXR) Delay time, ACLKR/X transmit edge to AFSX/R output valid ACLKR/X int -0.74 6 ns
ACLKR/X ext in
ACLKR/X ext out		 2 26.4 ns
ASP14 td(ACLK-AXR) Delay time, ACLKR/X transmit edge to AXR output valid ACLKR/X int -1.68 6.97 ns
ACLKR/X ext in
ACLKR/X ext out		 1.07 25.9 ns
AM5749 AM5748 AM5746 SPRS8xx_McASP_01.gif
A. For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP receiver is configured for rising edge (to shift data in).
B. For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP receiver is configured for falling edge (to shift data in).
Figure 5-59 McASP Output TimingAB

NOTE

To configure the desired virtual mode the user must set MODESELECT bit and DELAYMODE bit field for each corresponding pad control register.

The pad control registers are presented in Table 4-33 and described in chapter Control Module in the device TRM.

Table 5-86 through Table 5-93 explain all cases with Virtual Mode Details for McASP1/2/3/4/5/6/7/8 (see Figure 5-60 through Figure 5-67).

Table 5-86 Virtual Mode Case Details for McASP1

No. CASE CASE Description Virtual Mode Settings Notes
Signals Virtual Mode Value
IP Mode : ASYNC
1 COIFOI CLKX / FSX: Output CLKR / FSR: Input AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 5-60
AXR(Inputs)/CLKR/FSR MCASP1_VIRTUAL3_ASYNC_RX
2 COIFIO CLKX / FSR: Output CLKR / FSX: Input AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 5-61
AXR(Inputs)/CLKR/FSR MCASP1_VIRTUAL3_ASYNC_RX
3 CIOFIO CLKR / FSR: Output CLKX / FSX: Input AXR(Outputs)/CLKX/FSX MCASP1_VIRTUAL3_ASYNC_RX See Figure 5-62
AXR(Inputs)/CLKR/FSR MCASP1_VIRTUAL1_ASYNC_TX
4 CIOFOI CLKR / FSX: Output CLKX / FSR: Input AXR(Outputs)/CLKX/FSX MCASP1_VIRTUAL3_ASYNC_RX See Figure 5-63
AXR(Inputs)/CLKR/FSR MCASP1_VIRTUAL1_ASYNC_TX
IP Mode : SYNC (CLKR / FSR internally generated from CLKX / FSX)
5 CO-FO- CLKX / FSX: Output AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 5-64
AXR(Inputs)/CLKX/FSX Default (No Virtual Mode)
6 CI-FO- FSX: Output CLKX: Input AXR(Outputs)/CLKX/FSX MCASP1_VIRTUAL2_SYNC_RX See Figure 5-65
AXR(Inputs)/CLKX/FSX MCASP1_VIRTUAL2_SYNC_RX
7 CI-FI- CLKX / FSX: Input AXR(Outputs)/CLKX/FSX MCASP1_VIRTUAL2_SYNC_RX See Figure 5-66
AXR(Inputs)/CLKX/FSX MCASP1_VIRTUAL2_SYNC_RX
8 CO-FI- CLKX: Output FSX: Input AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 5-67
AXR(Inputs)/CLKX/FSX Default (No Virtual Mode)

Table 5-87 Virtual Mode Case Details for McASP2

No. CASE CASE Description Virtual Mode Settings Notes
Signals Virtual Mode Value
IP Mode : ASYNC
1 COIFOI CLKX / FSX: Output CLKR / FSR: Input AXR(Outputs)/CLKX/FSX Default (No Virtual Mode)(1) See Figure 5-60
AXR(Inputs)/CLKR/FSR Default (No Virtual Mode)(1)
AXR(Inputs)/CLKR/FSR MCASP2_VIRTUAL1_ASYNC_RX_80M(2)
2 COIFIO CLKX / FSR: Output CLKR / FSX: Input AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 5-61
AXR(Inputs)/CLKR/FSR MCASP2_VIRTUAL2_ASYNC_RX
3 CIOFIO CLKR / FSR: Output CLKX / FSX: Input AXR(Outputs)/CLKX/FSX MCASP2_VIRTUAL2_ASYNC_RX See Figure 5-62
AXR(Inputs)/CLKR/FSR MCASP2_VIRTUAL3_ASYNC_TX
4 CIOFOI CLKR / FSX: Output CLKX / FSR: Input AXR(Outputs)/CLKX/FSX MCASP2_VIRTUAL2_ASYNC_RX See Figure 5-63
AXR(Inputs)/CLKR/FSR MCASP2_VIRTUAL3_ASYNC_TX
IP Mode : SYNC (CLKR / FSR internally generated from CLKX / FSX)
5 CO-FO- CLKX / FSX: Output AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 5-64
AXR(Inputs)/CLKX/FSX Default (No Virtual Mode)
6 CI-FO- FSX: Output CLKX: Input AXR(Outputs)/CLKX/FSX MCASP2_VIRTUAL4_SYNC_RX See Figure 5-65
AXR(Inputs)/CLKX/FSX MCASP2_VIRTUAL4_SYNC_RX
7 CI-FI- CLKX / FSX: Input AXR(Outputs)/CLKX/FSX MCASP2_VIRTUAL4_SYNC_RX(1) See Figure 5-66
AXR(Inputs)/CLKX/FSX MCASP2_VIRTUAL4_SYNC_RX(1)
AXR(Inputs)/CLKX/FSX MCASP2_VIRTUAL5_SYNC_RX_80M(2)
8 CO-FI- CLKX: Output FSX: Input AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 5-67
AXR(Inputs)/CLKX/FSX Default (No Virtual Mode)
  1. Used up to 50 MHz. Should also be used in a CI-FI- mixed case where AXR operate as both inputs and outputs (that is, AXR are bidirectional).
  2. Used in 80 MHz input only mode when AXR, CLKX and FSX are all inputs.

Table 5-88 Virtual Mode Case Details for McASP3

No. CASE CASE Description Virtual Mode Settings Notes
Signals Virtual Mode Value
IP Mode : ASYNC
1 COIFOI CLKX / FSX: Output CLKR / FSR: Input AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 5-60
AXR(Inputs)/CLKR/FSR MCASP3_VIRTUAL2_SYNC_RX
2 COIFIO CLKX / FSR: Output CLKR / FSX: Input AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 5-61
AXR(Inputs)/CLKR/FSR MCASP3_VIRTUAL2_SYNC_RX
3 CIOFIO CLKR / FSR: Output CLKX / FSX: Input AXR(Outputs)/CLKX/FSX MCASP3_VIRTUAL2_SYNC_RX See Figure 5-62
AXR(Inputs)/CLKR/FSR MCASP3_VIRTUAL2_SYNC_RX
4 CIOFOI CLKR / FSX: Output CLKX / FSR: Input AXR(Outputs)/CLKX/FSX MCASP3_VIRTUAL2_SYNC_RX See Figure 5-63
AXR(Inputs)/CLKR/FSR MCASP3_VIRTUAL2_SYNC_RX
IP Mode : SYNC (CLKR / FSR internally generated from CLKX / FSX)
5 CO-FO- CLKX / FSX: Output AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 5-64
AXR(Inputs)/CLKX/FSX Default (No Virtual Mode)
6 CI-FO- FSX: Output CLKX: Input AXR(Outputs)/CLKX/FSX MCASP3_VIRTUAL2_SYNC_RX See Figure 5-65
AXR(Inputs)/CLKX/FSX MCASP3_VIRTUAL2_SYNC_RX
7 CI-FI- CLKX / FSX: Input AXR(Outputs)/CLKX/FSX MCASP3_VIRTUAL2_SYNC_RX See Figure 5-66
AXR(Inputs)/CLKX/FSX MCASP3_VIRTUAL2_SYNC_RX
8 CO-FI- CLKX: Output FSX: Input AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 5-67
AXR(Inputs)/CLKX/FSX Default (No Virtual Mode)

Table 5-89 Virtual Mode Case Details for McASP4

No. CASE CASE Description Virtual Mode Settings Notes
Signals Virtual Mode Value
IP Mode : ASYNC
1 COIFOI CLKX / FSX: Output CLKR / FSR: Input AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 5-60
AXR(Inputs)/CLKR/FSR MCASP4_VIRTUAL1_SYNC_RX
2 COIFIO CLKX / FSR: Output CLKR / FSX: Input AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 5-61
AXR(Inputs)/CLKR/FSR MCASP4_VIRTUAL1_SYNC_RX
3 CIOFIO CLKR / FSR: Output CLKX / FSX: Input AXR(Outputs)/CLKX/FSX MCASP4_VIRTUAL1_SYNC_RX See Figure 5-62
AXR(Inputs)/CLKR/FSR MCASP4_VIRTUAL1_SYNC_RX
4 CIOFOI CLKR / FSX: Output CLKX / FSR: Input AXR(Outputs)/CLKX/FSX MCASP4_VIRTUAL1_SYNC_RX See Figure 5-63
AXR(Inputs)/CLKR/FSR MCASP4_VIRTUAL1_SYNC_RX
IP Mode : SYNC (CLKR / FSR internally generated from CLKX / FSX)
5 CO-FO- CLKX / FSX: Output AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 5-64
AXR(Inputs)/CLKX/FSX Default (No Virtual Mode)
6 CI-FO- FSX: Output CLKX: Input AXR(Outputs)/CLKX/FSX MCASP4_VIRTUAL1_SYNC_RX See Figure 5-65
AXR(Inputs)/CLKX/FSX MCASP4_VIRTUAL1_SYNC_RX
7 CI-FI- CLKX / FSX: Input AXR(Outputs)/CLKX/FSX MCASP4_VIRTUAL1_SYNC_RX See Figure 5-66
AXR(Inputs)/CLKX/FSX MCASP4_VIRTUAL1_SYNC_RX
8 CO-FI- CLKX: Output FSX: Input AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 5-67
AXR(Inputs)/CLKX/FSX Default (No Virtual Mode)

Table 5-90 Virtual Mode Case Details for McASP5

No. CASE CASE Description Virtual Mode Settings Notes
Signals Virtual Mode Value
IP Mode : ASYNC
1 COIFOI CLKX / FSX: Output CLKR / FSR: Input AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 5-60
AXR(Inputs)/CLKR/FSR MCASP5_VIRTUAL1_SYNC_RX
2 COIFIO CLKX / FSR: Output CLKR / FSX: Input AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 5-61
AXR(Inputs)/CLKR/FSR MCASP5_VIRTUAL1_SYNC_RX
3 CIOFIO CLKR / FSR: Output CLKX / FSX: Input AXR(Outputs)/CLKX/FSX MCASP5_VIRTUAL1_SYNC_RX See Figure 5-62
AXR(Inputs)/CLKR/FSR MCASP5_VIRTUAL1_SYNC_RX
4 CIOFOI CLKR / FSX: Output CLKX / FSR: Input AXR(Outputs)/CLKX/FSX MCASP5_VIRTUAL1_SYNC_RX See Figure 5-63
AXR(Inputs)/CLKR/FSR MCASP5_VIRTUAL1_SYNC_RX
IP Mode : SYNC (CLKR / FSR internally generated from CLKX / FSX)
5 CO-FO- CLKX / FSX: Output AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 5-64
AXR(Inputs)/CLKX/FSX Default (No Virtual Mode)
6 CI-FO- FSX: Output CLKX: Input AXR(Outputs)/CLKX/FSX MCASP5_VIRTUAL1_SYNC_RX See Figure 5-65
AXR(Inputs)/CLKX/FSX MCASP5_VIRTUAL1_SYNC_RX
7 CI-FI- CLKX / FSX: Input AXR(Outputs)/CLKX/FSX MCASP5_VIRTUAL1_SYNC_RX See Figure 5-66
AXR(Inputs)/CLKX/FSX MCASP5_VIRTUAL1_SYNC_RX
8 CO-FI- CLKX: Output FSX: Input AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 5-67
AXR(Inputs)/CLKX/FSX Default (No Virtual Mode)

Table 5-91 Virtual Mode Case Details for McASP6

No. CASE CASE Description Virtual Mode Settings Notes
Signals Virtual Mode Value
IP Mode : ASYNC
1 COIFOI CLKX / FSX: Output CLKR / FSR: Input AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 5-60
AXR(Inputs)/CLKR/FSR MCASP6_VIRTUAL1_SYNC_RX
2 COIFIO CLKX / FSR: Output CLKR / FSX: Input AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 5-61
AXR(Inputs)/CLKR/FSR MCASP6_VIRTUAL1_SYNC_RX
3 CIOFIO CLKR / FSR: Output CLKX / FSX: Input AXR(Outputs)/CLKX/FSX MCASP6_VIRTUAL1_SYNC_RX See Figure 5-62
AXR(Inputs)/CLKR/FSR MCASP6_VIRTUAL1_SYNC_RX
4 CIOFOI CLKR / FSX: Output CLKX / FSR: Input AXR(Outputs)/CLKX/FSX MCASP6_VIRTUAL1_SYNC_RX See Figure 5-63
AXR(Inputs)/CLKR/FSR MCASP6_VIRTUAL1_SYNC_RX
IP Mode : SYNC (CLKR / FSR internally generated from CLKX / FSX)
5 CO-FO- CLKX / FSX: Output AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 5-64
AXR(Inputs)/CLKX/FSX Default (No Virtual Mode)
6 CI-FO- FSX: Output CLKX: Input AXR(Outputs)/CLKX/FSX MCASP6_VIRTUAL1_SYNC_RX See Figure 5-65
AXR(Inputs)/CLKX/FSX MCASP6_VIRTUAL1_SYNC_RX
7 CI-FI- CLKX / FSX: Input AXR(Outputs)/CLKX/FSX MCASP6_VIRTUAL1_SYNC_RX See Figure 5-66
AXR(Inputs)/CLKX/FSX MCASP6_VIRTUAL1_SYNC_RX
8 CO-FI- CLKX: Output FSX: Input AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 5-67
AXR(Inputs)/CLKX/FSX Default (No Virtual Mode)

Table 5-92 Virtual Mode Case Details for McASP7

No. CASE CASE Description Virtual Mode Settings Notes
Signals Virtual Mode Value
IP Mode : ASYNC
1 COIFOI CLKX / FSX: Output CLKR / FSR: Input AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 5-60
AXR(Inputs)/CLKR/FSR MCASP7_VIRTUAL2_SYNC_RX
2 COIFIO CLKX / FSR: Output CLKR / FSX: Input AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 5-61
AXR(Inputs)/CLKR/FSR MCASP7_VIRTUAL2_SYNC_RX
3 CIOFIO CLKR / FSR: Output CLKX / FSX: Input AXR(Outputs)/CLKX/FSX MCASP7_VIRTUAL2_SYNC_RX See Figure 5-62
AXR(Inputs)/CLKR/FSR MCASP7_VIRTUAL2_SYNC_RX
4 CIOFOI CLKR / FSX: Output CLKX / FSR: Input AXR(Outputs)/CLKX/FSX MCASP7_VIRTUAL2_SYNC_RX See Figure 5-63
AXR(Inputs)/CLKR/FSR MCASP7_VIRTUAL2_SYNC_RX
IP Mode : SYNC (CLKR / FSR internally generated from CLKX / FSX)
5 CO-FO- CLKX / FSX: Output AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 5-64
AXR(Inputs)/CLKX/FSX Default (No Virtual Mode)
6 CI-FO- FSX: Output CLKX: Input AXR(Outputs)/CLKX/FSX MCASP7_VIRTUAL2_SYNC_RX See Figure 5-65
AXR(Inputs)/CLKX/FSX MCASP7_VIRTUAL2_SYNC_RX
7 CI-FI- CLKX / FSX: Input AXR(Outputs)/CLKX/FSX MCASP7_VIRTUAL2_SYNC_RX See Figure 5-66
AXR(Inputs)/CLKX/FSX MCASP7_VIRTUAL2_SYNC_RX
8 CO-FI- CLKX: Output FSX: Input AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 5-67
AXR(Inputs)/CLKX/FSX Default (No Virtual Mode)

Table 5-93 Virtual Mode Case Details for McASP8

No. CASE CASE Description Virtual Mode Settings Notes
Signals Virtual Mode Value
IP Mode : ASYNC
1 COIFOI CLKX / FSX: Output CLKR / FSR: Input AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 5-60
AXR(Inputs)/CLKR/FSR MCASP8_VIRTUAL1_SYNC_RX
2 COIFIO CLKX / FSR: Output CLKR / FSX: Input AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 5-61
AXR(Inputs)/CLKR/FSR MCASP8_VIRTUAL1_SYNC_RX
3 CIOFIO CLKR / FSR: Output CLKX / FSX: Input AXR(Outputs)/CLKX/FSX MCASP8_VIRTUAL1_SYNC_RX See Figure 5-62
AXR(Inputs)/CLKR/FSR MCASP8_VIRTUAL1_SYNC_RX
4 CIOFOI CLKR / FSX: Output CLKX / FSR: Input AXR(Outputs)/CLKX/FSX MCASP8_VIRTUAL1_SYNC_RX See Figure 5-63
AXR(Inputs)/CLKR/FSR MCASP8_VIRTUAL1_SYNC_RX
IP Mode : SYNC (CLKR / FSR internally generated from CLKX / FSX)
5 CO-FO- CLKX / FSX: Output AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 5-64
AXR(Inputs)/CLKX/FSX Default (No Virtual Mode)
6 CI-FO- FSX: Output CLKX: Input AXR(Outputs)/CLKX/FSX MCASP8_VIRTUAL1_SYNC_RX See Figure 5-65
AXR(Inputs)/CLKX/FSX MCASP8_VIRTUAL1_SYNC_RX
7 CI-FI- CLKX / FSX: Input AXR(Outputs)/CLKX/FSX MCASP8_VIRTUAL1_SYNC_RX See Figure 5-66
AXR(Inputs)/CLKX/FSX MCASP8_VIRTUAL1_SYNC_RX
8 CO-FI- CLKX: Output FSX: Input AXR(Outputs)/CLKX/FSX Default (No Virtual Mode) See Figure 5-67
AXR(Inputs)/CLKX/FSX Default (No Virtual Mode)
AM5749 AM5748 AM5746 SPRS915_MCASP_uc_01.gifFigure 5-60 McASP1-8 COIFOI – ASYNC Mode
AM5749 AM5748 AM5746 SPRS915_MCASP_uc_02.gifFigure 5-61 McASP1-8 COIFIO – ASYNC Mode
AM5749 AM5748 AM5746 SPRS915_MCASP_uc_03.gifFigure 5-62 McASP1-8 CIOFIO – ASYNC Mode
AM5749 AM5748 AM5746 SPRS915_MCASP_uc_04.gifFigure 5-63 McASP1-8 CIOFOI – ASYNC Mode
AM5749 AM5748 AM5746 SPRS915_MCASP_uc_05.gifFigure 5-64 McASP1-8 CO-FO- – SYNC Mode
AM5749 AM5748 AM5746 SPRS915_MCASP_uc_06.gifFigure 5-65 McASP1-8 CI-FO- – SYNC Mode
AM5749 AM5748 AM5746 SPRS915_MCASP_uc_07.gifFigure 5-66 McASP1-8 CI-FI- – SYNC Mode
AM5749 AM5748 AM5746 SPRS915_MCASP_uc_08.gifFigure 5-67 McASP1-8 CO-FI- – SYNC Mode

Virtual IO Timings Modes must be used to ensure some IO timings for McASP1. See Table 5-33, Modes Summary for a list of IO timings requiring the use of Virtual IO Timings Modes. See Table 5-94, Virtual Functions Mapping for McASP1 for a definition of the Virtual modes.

Table 5-94 presents the values for DELAYMODE bit field.

Table 5-94 Virtual Functions Mapping for McASP1(1)

BALL BALL NAME Delay Mode Value MUXMODE[15:0]
MCASP1_VIRTUAL1
_ASYNC_TX		 MCASP1_VIRTUAL2
_SYNC_RX		 MCASP1_VIRTUAL3
_ASYNC_RX		 0 1 2
E21 gpio6_14 11 15 14 mcasp1_axr8
F20 gpio6_15 11 15 14 mcasp1_axr9
F21 gpio6_16 11 15 14 mcasp1_axr10
D18 xref_clk0 0 15 14 mcasp1_axr4
E17 xref_clk1 0 15 14 mcasp1_axr5
B26 xref_clk2 5 15 14 mcasp1_axr6
C23 xref_clk3 5 15 14 mcasp1_axr7
C14 mcasp1_aclkx 8 15 14 mcasp1_aclkx
D14 mcasp1_fsx 12 15 14 mcasp1_fsx
B14 mcasp1_aclkr 11 N/A 15 mcasp1_aclkr
J14 mcasp1_fsr 11 N/A 15 mcasp1_fsr
G12 mcasp1_axr0 8 15 14 mcasp1_axr0
F12 mcasp1_axr1 8 15 14 mcasp1_axr1
G13 mcasp1_axr2 10 15 14 mcasp1_axr2
J11 mcasp1_axr3 10 15 14 mcasp1_axr3
E12 mcasp1_axr4 10 15 14 mcasp1_axr4
F13 mcasp1_axr5 10 15 14 mcasp1_axr5
C12 mcasp1_axr6 10 15 14 mcasp1_axr6
D12 mcasp1_axr7 10 15 14 mcasp1_axr7
B12 mcasp1_axr8 6 15 14 mcasp1_axr8
A11 mcasp1_axr9 6 15 14 mcasp1_axr9
B13 mcasp1_axr10 6 15 14 mcasp1_axr10
A12 mcasp1_axr11 6 15 14 mcasp1_axr11
E14 mcasp1_axr12 6 15 14 mcasp1_axr12
A13 mcasp1_axr13 6 15 14 mcasp1_axr13
G14 mcasp1_axr14 6 15 14 mcasp1_axr14
F14 mcasp1_axr15 6 15 14 mcasp1_axr15
  1. NA stands for Not Applicable

Virtual IO Timings Modes must be used to ensure some IO timings for McASP2. See Table 5-33, Modes Summary for a list of IO timings requiring the use of Virtual IO Timings Modes. See Table 5-95, Virtual Functions Mapping for McASP2 for a definition of the Virtual modes.

Table 5-95 presents the values for DELAYMODE bit field.

Table 5-95 Virtual Functions Mapping for McASP2(1)

BALL BALL NAME Delay Mode Value MUXMODE[15:0]
MCASP2_
VIRTUAL1_
ASYNC_RX_80M		 MCASP2_
VIRTUAL2_
ASYNC_RX		 MCASP2_
VIRTUAL3_
ASYNC_TX		 MCASP2_
VIRTUAL4_
SYNC_RX		 MCASP2_
VIRTUAL5_
SYNC_RX_80M		 0 1 2
D18 xref_clk0 10 9 4 8 6 mcasp2_axr8
E17 xref_clk1 10 9 4 8 6 mcasp2_axr9
B26 xref_clk2 13 12 0 11 10 mcasp2_axr10
C23 xref_clk3 13 12 0 11 10 mcasp2_axr11
A19 mcasp2_aclkx 15 14 5 10 9 mcasp2_aclkx
A18 mcasp2_fsx 15 14 5 10 9 mcasp2_fsx
E15 mcasp2_aclkr 15 14 10 N/A N/A mcasp2_aclkr
A20 mcasp2_fsr 15 14 10 N/A N/A mcasp2_fsr
B15 mcasp2_axr0 15 14 9 13 12 mcasp2_axr0
A15 mcasp2_axr1 15 14 9 13 12 mcasp2_axr1
C15 mcasp2_axr2 15 14 4 10 9 mcasp2_axr2
A16 mcasp2_axr3 15 14 4 10 9 mcasp2_axr3
D15 mcasp2_axr4 15 14 7 13 12 mcasp2_axr4
B16 mcasp2_axr5 15 14 7 13 12 mcasp2_axr5
B17 mcasp2_axr6 15 14 7 13 12 mcasp2_axr6
A17 mcasp2_axr7 15 14 7 13 12 mcasp2_axr7
B18 mcasp3_aclkx 15 14 5 10 9 mcasp2_axr12
F15 mcasp3_fsx 15 14 4 10 9 mcasp2_axr13
B19 mcasp3_axr0 15 14 4 10 9 mcasp2_axr14
C17 mcasp3_axr1 15 14 3 10 8 mcasp2_axr15
  1. NA stands for Not Applicable.

Virtual IO Timings Modes must be used to ensure some IO timings for McASP3/4/5/6/7/8. See Table 5-33, Modes Summary for a list of IO timings requiring the use of Virtual IO Timings Modes. See Table 5-96, Virtual Functions Mapping for McASP3/4/5/6/7/8 for a definition of the Virtual modes.

Table 5-96 presents the values for DELAYMODE bit field.

Table 5-96 Virtual Functions Mapping for McASP3/4/5/6/7/8

BALL BALL NAME Delay Mode Value MUXMODE[15:0]
0 1 2
MCASP3_VIRTUAL2_SYNC_RX
C15 mcasp2_axr2 8 mcasp3_axr2
A16 mcasp2_axr3 8 mcasp3_axr3
B18 mcasp3_aclkx 8 mcasp3_aclkx mcasp3_aclkr
F15 mcasp3_fsx 8 mcasp3_fsx mcasp3_fsr
B19 mcasp3_axr0 8 mcasp3_axr0
C17 mcasp3_axr1 6 mcasp3_axr1
MCASP4_VIRTUAL1_SYNC_RX
E12 mcasp1_axr4 13 mcasp4_axr2
F13 mcasp1_axr5 13 mcasp4_axr3
C18 mcasp4_aclkx 15 mcasp4_aclkx mcasp4_aclkr
A21 mcasp4_fsx 15 mcasp4_fsx mcasp4_fsr
G16 mcasp4_axr0 15 mcasp4_axr0
D17 mcasp4_axr1 15 mcasp4_axr1
MCASP5_VIRTUAL1_SYNC_RX
C12 mcasp1_axr6 13 mcasp5_axr2
D12 mcasp1_axr7 13 mcasp5_axr3
AA3 mcasp5_aclkx 15 mcasp5_aclkx mcasp5_aclkr
AB9 mcasp5_fsx 15 mcasp5_fsx mcasp5_fsr
AB3 mcasp5_axr0 15 mcasp5_axr0
AA4 mcasp5_axr1 15 mcasp5_axr1
MCASP6_VIRTUAL1_SYNC_RX
G13 mcasp1_axr2 13 mcasp6_axr2
J11 mcasp1_axr3 13 mcasp6_axr3
B12 mcasp1_axr8 10 mcasp6_axr0
A11 mcasp1_axr9 10 mcasp6_axr1
B13 mcasp1_axr10 10 mcasp6_aclkx mcasp6_aclkr
A12 mcasp1_axr11 10 mcasp6_fsx mcasp6_fsr
MCASP7_VIRTUAL2_SYNC_RX
B14 mcasp1_aclkr 14 mcasp7_axr2
J14 mcasp1_fsr 14 mcasp7_axr3
E14 mcasp1_axr12 10 mcasp7_axr0
A13 mcasp1_axr13 10 mcasp7_axr1
G14 mcasp1_axr14 10 mcasp7_aclkx mcasp7_aclkr
F14 mcasp1_axr15 10 mcasp7_fsx mcasp7_fsr
MCASP8_VIRTUAL1_SYNC_RX
E15 mcasp2_aclkr 13 mcasp8_axr2
A20 mcasp2_fsr 13 mcasp8_axr3
D15 mcasp2_axr4 11 mcasp8_axr0
B16 mcasp2_axr5 11 mcasp8_axr1
B17 mcasp2_axr6 11 mcasp8_aclkx mcasp8_aclkr
A17 mcasp2_axr7 11 mcasp8_fsx mcasp8_fsr