SPRSP58C June   2022  – October 2025 AM620-Q1 , AM623 , AM625 , AM625-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Terminal Configuration and Functions
    1. 5.1 Pin Diagrams
    2. 5.2 Pin Attributes
      1.      11
      2.      12
    3. 5.3 Signal Descriptions
      1.      14
      2. 5.3.1  CPSW3G
        1. 5.3.1.1 MAIN Domain
          1.        17
          2.        18
          3.        19
          4.        20
      3. 5.3.2  CPTS
        1. 5.3.2.1 MAIN Domain
          1.        23
      4. 5.3.3  CSI-2
        1. 5.3.3.1 MAIN Domain
          1.        26
      5. 5.3.4  DDRSS
        1. 5.3.4.1 MAIN Domain
          1.        29
      6. 5.3.5  DSS
        1. 5.3.5.1 MAIN Domain
          1.        32
      7. 5.3.6  ECAP
        1. 5.3.6.1 MAIN Domain
          1.        35
          2.        36
          3.        37
      8. 5.3.7  Emulation and Debug
        1. 5.3.7.1 MAIN Domain
          1.        40
        2. 5.3.7.2 MCU Domain
          1.        42
      9. 5.3.8  EPWM
        1. 5.3.8.1 MAIN Domain
          1.        45
          2.        46
          3.        47
          4.        48
      10. 5.3.9  EQEP
        1. 5.3.9.1 MAIN Domain
          1.        51
          2.        52
          3.        53
      11. 5.3.10 GPIO
        1. 5.3.10.1 MAIN Domain
          1.        56
          2.        57
        2. 5.3.10.2 MCU Domain
          1.        59
      12. 5.3.11 GPMC
        1. 5.3.11.1 MAIN Domain
          1.        62
      13. 5.3.12 I2C
        1. 5.3.12.1 MAIN Domain
          1.        65
          2.        66
          3.        67
          4.        68
        2. 5.3.12.2 MCU Domain
          1.        70
        3. 5.3.12.3 WKUP Domain
          1.        72
      14. 5.3.13 MCAN
        1. 5.3.13.1 MAIN Domain
          1.        75
        2. 5.3.13.2 MCU Domain
          1.        77
          2.        78
      15. 5.3.14 MCASP
        1. 5.3.14.1 MAIN Domain
          1.        81
          2.        82
          3.        83
      16. 5.3.15 MCSPI
        1. 5.3.15.1 MAIN Domain
          1.        86
          2.        87
          3.        88
        2. 5.3.15.2 MCU Domain
          1.        90
          2.        91
      17. 5.3.16 MDIO
        1. 5.3.16.1 MAIN Domain
          1.        94
      18. 5.3.17 MMC
        1. 5.3.17.1 MAIN Domain
          1.        97
          2.        98
          3.        99
      19. 5.3.18 OLDI
        1. 5.3.18.1 MAIN Domain
          1.        102
      20. 5.3.19 OSPI
        1. 5.3.19.1 MAIN Domain
          1.        105
      21. 5.3.20 Power Supply
        1.       107
      22. 5.3.21 PRUSS
        1. 5.3.21.1 MAIN Domain
          1.        110
          2.        111
      23. 5.3.22 Reserved
        1.       113
      24. 5.3.23 System and Miscellaneous
        1. 5.3.23.1 Boot Mode Configuration
          1. 5.3.23.1.1 MAIN Domain
            1.         117
        2. 5.3.23.2 Clock
          1. 5.3.23.2.1 MCU Domain
            1.         120
          2. 5.3.23.2.2 WKUP Domain
            1.         122
        3. 5.3.23.3 System
          1. 5.3.23.3.1 MAIN Domain
            1.         125
          2. 5.3.23.3.2 MCU Domain
            1.         127
          3. 5.3.23.3.3 WKUP Domain
            1.         129
        4. 5.3.23.4 VMON
          1.        131
      25. 5.3.24 TIMER
        1. 5.3.24.1 MAIN Domain
          1.        134
        2. 5.3.24.2 MCU Domain
          1.        136
        3. 5.3.24.3 WKUP Domain
          1.        138
      26. 5.3.25 UART
        1. 5.3.25.1 MAIN Domain
          1.        141
          2.        142
          3.        143
          4.        144
          5.        145
          6.        146
          7.        147
        2. 5.3.25.2 MCU Domain
          1.        149
        3. 5.3.25.3 WKUP Domain
          1.        151
      27. 5.3.26 USB
        1. 5.3.26.1 MAIN Domain
          1.        154
          2.        155
    4. 5.4 Pin Connectivity Requirements
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings for Devices which are not AEC - Q100 Qualified
    3. 6.3  ESD Ratings for AEC - Q100 Qualified Devices
    4. 6.4  Power-On Hours (POH)
    5. 6.5  Recommended Operating Conditions
    6. 6.6  Operating Performance Points
    7. 6.7  Power Consumption Summary
    8. 6.8  Electrical Characteristics
      1. 6.8.1  I2C Open-Drain, and Fail-Safe (I2C OD FS) Electrical Characteristics
      2. 6.8.2  Fail-Safe Reset (FS RESET) Electrical Characteristics
      3. 6.8.3  High-Frequency Oscillator (HFOSC) Electrical Characteristics
      4. 6.8.4  Low-Frequency Oscillator (LFXOSC) Electrical Characteristics
      5. 6.8.5  SDIO Electrical Characteristics
      6. 6.8.6  LVCMOS Electrical Characteristics
      7. 6.8.7  OLDI LVDS (OLDI) Electrical Characteristics
      8. 6.8.8  CSI-2 (D-PHY) Electrical Characteristics
      9. 6.8.9  USB2PHY Electrical Characteristics
      10. 6.8.10 DDR Electrical Characteristics
    9. 6.9  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 6.9.1 Recommended Operating Conditions for OTP eFuse Programming
      2. 6.9.2 Hardware Requirements
      3. 6.9.3 Programming Sequence
      4. 6.9.4 Impact to Your Hardware Warranty
    10. 6.10 Thermal Resistance Characteristics
      1. 6.10.1 Thermal Resistance Characteristics for ALW and AMC Packages
    11. 6.11 Temperature Sensor Characteristics
    12. 6.12 Timing and Switching Characteristics
      1. 6.12.1 Timing Parameters and Information
      2. 6.12.2 Power Supply Requirements
        1. 6.12.2.1 Power Supply Slew Rate Requirement
        2. 6.12.2.2 Power Supply Sequencing
          1. 6.12.2.2.1 Power-Up Sequencing
          2. 6.12.2.2.2 Power-Down Sequencing
          3. 6.12.2.2.3 Partial IO Power Sequencing
      3. 6.12.3 System Timing
        1. 6.12.3.1 Reset Timing
        2. 6.12.3.2 Error Signal Timing
        3. 6.12.3.3 Clock Timing
      4. 6.12.4 Clock Specifications
        1. 6.12.4.1 Input Clocks / Oscillators
          1. 6.12.4.1.1 MCU_OSC0 Internal Oscillator Clock Source
            1. 6.12.4.1.1.1 Load Capacitance
            2. 6.12.4.1.1.2 Shunt Capacitance
          2. 6.12.4.1.2 MCU_OSC0 LVCMOS Digital Clock Source
          3. 6.12.4.1.3 WKUP_LFOSC0 Internal Oscillator Clock Source
          4. 6.12.4.1.4 WKUP_LFOSC0 LVCMOS Digital Clock Source
          5. 6.12.4.1.5 WKUP_LFOSC0 Not Used
        2. 6.12.4.2 Output Clocks
        3. 6.12.4.3 PLLs
        4. 6.12.4.4 Recommended System Precautions for Clock and Control Signal Transitions
      5. 6.12.5 Peripherals
        1. 6.12.5.1  CPSW3G
          1. 6.12.5.1.1 CPSW3G MDIO Timing
          2. 6.12.5.1.2 CPSW3G RMII Timing
          3. 6.12.5.1.3 CPSW3G RGMII Timing
        2. 6.12.5.2  CPTS
        3. 6.12.5.3  CSI-2
        4. 6.12.5.4  DDRSS
        5. 6.12.5.5  DSS
        6. 6.12.5.6  ECAP
        7. 6.12.5.7  Emulation and Debug
          1. 6.12.5.7.1 Trace
          2. 6.12.5.7.2 JTAG
        8. 6.12.5.8  EPWM
        9. 6.12.5.9  EQEP
        10. 6.12.5.10 GPIO
        11. 6.12.5.11 GPMC
          1. 6.12.5.11.1 GPMC and NOR Flash — Synchronous Mode
          2. 6.12.5.11.2 GPMC and NOR Flash — Asynchronous Mode
          3. 6.12.5.11.3 GPMC and NAND Flash — Asynchronous Mode
        12. 6.12.5.12 I2C
        13. 6.12.5.13 MCAN
        14. 6.12.5.14 MCASP
        15. 6.12.5.15 MCSPI
          1. 6.12.5.15.1 MCSPI — Controller Mode
          2. 6.12.5.15.2 MCSPI — Peripheral Mode
        16. 6.12.5.16 MMCSD
          1. 6.12.5.16.1 MMC0 - eMMC/SD/SDIO Interface
            1. 6.12.5.16.1.1  Legacy SDR Mode
            2. 6.12.5.16.1.2  High Speed SDR Mode
            3. 6.12.5.16.1.3  HS200 Mode
            4. 6.12.5.16.1.4  Default Speed Mode
            5. 6.12.5.16.1.5  High Speed Mode
            6. 6.12.5.16.1.6  UHS–I SDR12 Mode
            7. 6.12.5.16.1.7  UHS–I SDR25 Mode
            8. 6.12.5.16.1.8  UHS–I SDR50 Mode
            9. 6.12.5.16.1.9  UHS–I DDR50 Mode
            10. 6.12.5.16.1.10 UHS–I SDR104 Mode
          2. 6.12.5.16.2 MMC1/MMC2 - SD/SDIO Interface
            1. 6.12.5.16.2.1 Default Speed Mode
            2. 6.12.5.16.2.2 High Speed Mode
            3. 6.12.5.16.2.3 UHS–I SDR12 Mode
            4. 6.12.5.16.2.4 UHS–I SDR25 Mode
            5. 6.12.5.16.2.5 UHS–I SDR50 Mode
            6. 6.12.5.16.2.6 UHS–I DDR50 Mode
            7. 6.12.5.16.2.7 UHS–I SDR104 Mode
        17. 6.12.5.17 OLDI
          1. 6.12.5.17.1 OLDI0 Switching Characteristics
        18. 6.12.5.18 OSPI
          1. 6.12.5.18.1 OSPI0 PHY Mode
            1. 6.12.5.18.1.1 OSPI0 With PHY Data Training
            2. 6.12.5.18.1.2 OSPI0 Without Data Training
              1. 6.12.5.18.1.2.1 OSPI0 PHY SDR Timing
              2. 6.12.5.18.1.2.2 OSPI0 PHY DDR Timing
          2. 6.12.5.18.2 OSPI0 Tap Mode
            1. 6.12.5.18.2.1 OSPI0 Tap SDR Timing
            2. 6.12.5.18.2.2 OSPI0 Tap DDR Timing
        19. 6.12.5.19 PRUSS
          1. 6.12.5.19.1 PRUSS Programmable Real-Time Unit (PRU)
            1. 6.12.5.19.1.1 PRUSS PRU Direct Output Mode Timing
            2. 6.12.5.19.1.2 PRUSS PRU Parallel Capture Mode Timing
            3. 6.12.5.19.1.3 PRUSS PRU Shift Mode Timing
          2. 6.12.5.19.2 PRUSS Industrial Ethernet Peripheral (IEP)
            1. 6.12.5.19.2.1 PRUSS IEP Timing
          3. 6.12.5.19.3 PRUSS Universal Asynchronous Receiver Transmitter (UART)
            1. 6.12.5.19.3.1 PRUSS UART Timing
          4. 6.12.5.19.4 PRUSS Enhanced Capture Peripheral (ECAP)
            1. 6.12.5.19.4.1 PRUSS ECAP Timing
        20. 6.12.5.20 Timers
        21. 6.12.5.21 UART
        22. 6.12.5.22 USB
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Processor Subsystems
      1. 7.2.1 Arm Cortex-A53 Subsystem (A53SS)
      2. 7.2.2 Device/Power Manager
      3. 7.2.3 Arm Cortex-M4F
    3. 7.3 Accelerators and Coprocessors
      1. 7.3.1 Graphics Processing Unit (GPU)
      2. 7.3.2 Programmable Real-Time Unit Subsystem (PRUSS)
    4. 7.4 Other Subsystems
      1. 7.4.1 Dual Clock Comparator (DCC)
      2. 7.4.2 Data Movement Subsystem (DMSS)
      3. 7.4.3 Memory Cyclic Redundancy Check (MCRC)
      4. 7.4.4 Peripheral DMA Controller (PDMA)
      5. 7.4.5 Real-Time Clock (RTC)
    5. 7.5 Peripherals
      1. 7.5.1  Gigabit Ethernet Switch (CPSW3G)
      2. 7.5.2  Camera Serial Interface Receiver (CSI_RX_IF)
      3. 7.5.3  DDR Subsystem (DDRSS)
      4. 7.5.4  Display Subsystem (DSS)
      5. 7.5.5  Enhanced Capture (ECAP)
      6. 7.5.6  Error Location Module (ELM)
      7. 7.5.7  Enhanced Pulse Width Modulation (EPWM)
      8. 7.5.8  Error Signaling Module (ESM)
      9. 7.5.9  Enhanced Quadrature Encoder Pulse (EQEP)
      10. 7.5.10 General-Purpose Interface (GPIO)
      11. 7.5.11 General-Purpose Memory Controller (GPMC)
      12. 7.5.12 Global Timebase Counter (GTC)
      13. 7.5.13 Inter-Integrated Circuit (I2C)
      14. 7.5.14 Modular Controller Area Network (MCAN)
      15. 7.5.15 Multichannel Audio Serial Port (MCASP)
      16. 7.5.16 Multichannel Serial Peripheral Interface (MCSPI)
      17. 7.5.17 Multi-Media Card Secure Digital (MMCSD)
      18. 7.5.18 Octal Serial Peripheral Interface (OSPI)
      19. 7.5.19 Timers
      20. 7.5.20 Universal Asynchronous Receiver/Transmitter (UART)
      21. 7.5.21 Universal Serial Bus Subsystem (USBSS)
  9. 8 Applications, Implementation, and Layout
    1. 8.1 Device Connection and Layout Fundamentals
      1. 8.1.1 Power Supply
        1. 8.1.1.1 Power Supply Designs
        2. 8.1.1.2 Power Distribution Network Implementation Guidance
      2. 8.1.2 External Oscillator
      3. 8.1.3 JTAG, EMU, and TRACE
      4. 8.1.4 Unused Pins
    2. 8.2 Peripheral- and Interface-Specific Design Information
      1. 8.2.1 DDR Board Design and Layout Guidelines
      2. 8.2.2 OSPI/QSPI/SPI Board Design and Layout Guidelines
        1. 8.2.2.1 No Loopback, Internal PHY Loopback, and Internal Pad Loopback
        2. 8.2.2.2 External Board Loopback
        3. 8.2.2.3 DQS (only available in Octal SPI devices)
      3. 8.2.3 USB VBUS Design Guidelines
      4. 8.2.4 System Power Supply Monitor Design Guidelines
      5. 8.2.5 High Speed Differential Signal Routing Guidance
      6. 8.2.6 Thermal Solution Guidance
    3. 8.3 Clock Routing Guidelines
      1. 8.3.1 Oscillator Routing
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
      1. 9.1.1 Standard Package Symbolization
      2. 9.1.2 Device Naming Convention
    2. 9.2 Tools and Software
    3. 9.3 Documentation Support
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • AMC|441
  • ALW|425
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Revision History

Changes from June 15, 2023 to October 31, 2025 (from Revision B (JUNE 2023) to Revision C (OCTOBER 2025))

  • Global: Removed references to Industrial functional safetyGo
  • Global: Updated the introductory sentence in 10 timing sections.Go
  • (Features): Added "/SDIO" to the Multi-Media Card/Secure Digital bullet in Media and Data StorageGo
  • (Features): Removed the "Trace over USB supported" bullet from High-Speed InterfacesGo
  • Global: Moved the Revision History section to the back of the documentGo
  • (Description): Removed the list of applications and corrected typographical errorsGo
  • (Description): Removed sentence describing package optionsGo
  • (Package Information): Added 13mm×13mm ALW package options for AM625-Q1 and AM620-Q1.Go
  • (Device Comparison): Updated total number of available external General-Purpose I/Os in the device from 170 to 168Go
  • (Device Comparison): Updated the name of the JTAG User ID registerGo
  • (Device Comparison): Changed "Up to 1GB" to "Up to 128MB" in the General-Purpose Memory Controller descriptionGo
  • (Device Comparison): Changed "LVDS" to "OLDI (LVDS)" in the Display Subsystem descriptionGo
  • (Device Comparison): Added row to indicate GTC supportGo
  • (Related Products): Added links to products for design completionGo
  • (ALW FCCSP Pin Diagram): Changed the figure from a bottom view a top viewGo
  • (AMC FCBGA Pin Diagram): Changed the figure from a bottom view a top viewGo
  • (EPWM0 Signal Descriptions): Updated the EHRPWM0_SYNCO descriptionGo
  • (MMC2 Signal Descriptions): Added Note 2 to the MMC2_SDCD and MMC2_SDWP signalsGo
  • (Power Supply Signal Descriptions): Updated the table notes associated with the CAP_VDDSx pins to clarify the need for capacitance derating and describe additional connectivity options Go
  • (Power Supply Signal Descriptions): Updated the description of several power rails to clarify their functionGo
  • (MCU System Signal Descriptions): Updated the description of the MCU_PORz signal functionGo
  • (UART1 Signal Descriptions): Corrected the description for UART1_DCDnGo
  • (Pin Connectivity Requirements): Updated the connectivity requirements description for MCU_I2C0 and WKUP_I2C0 balls to allow connecting external pull-down resistors when selecting a GPIO signal functionGo
  • (Connectivity Requirements): Updated the Connection Requirements descriptions for CSI0 balls to clarify connectivity expectations when not using all four lanesGo
  • (Pin Connectivity Requirements): Updated the VMON_3P3_SOC connectivity requirementsGo
  • (Absolute Maximum Ratings): Updated the description of several power rails to clarify their functionGo
  • (ESD Ratings): Added ALW corner pins to ESD Ratings section for AEC-Q100 qualified devicesGo
  • (Recommended Operating Conditions): Updated the description of several power rails to clarify their functionGo
  • (I2C Open-Drain, and Fail-Safe Electrical Characteristics) Added a table note to the Input Leakage Current parameterGo
  • (I2C Open-Drain, and Fail-Safe Electrical Characteristics) Separated the Input Leakage Current Test Conditions into two rowsGo
  • (Fail-Safe Reset Electrical Characteristics) Added a table note to the Input Leakage Current parameterGo
  • (Fail-Safe Reset Electrical Characteristics) Separated the Input Leakage Current Test Conditions into two rowsGo
  • (High-Frequency Oscillator Electrical Characteristics) Added a table note to the Input Leakage Current parameterGo
  • (High-Frequency Oscillator Electrical Characteristics) Separated the Input Leakage Current Test Conditions into two rowsGo
  • (Low-Frequency Oscillator Electrical Characteristics) Added a table note to the Input Leakage Current parameterGo
  • (Low-Frequency Oscillator Electrical Characteristics) Separated the Input Leakage Current Test Conditions into two rowsGo
  • (SDIO Electrical Characteristics) Added a table note to the Input Leakage Current parameterGo
  • (SDIO Electrical Characteristics) Separated the Input Leakage Current Test Conditions into two rowsGo
  • (SDIO Electrical Characteristics): Changed VDDSHV5 power rail name used to define the VIL/VILSS/VIH/VIHSS/VOL/VOH parameter values by referencing a generic power rail name (VDD), where applicable, and added an associated table noteGo
  • (LVCMOS Electrical Characteristics) Added a table note to the Input Leakage Current parameterGo
  • (LVCMOS Electrical Characteristics) Separated the Input Leakage Current Test Conditions into two rowsGo
  • (Recommended Operating Conditions for OTP eFuse Programming): Removed the OPP NOM (BOOT) reference from the VDD_CORE parameter description, and changed the VPP Slew Rate description to clarify it only applies to power-upGo
  • (Impact to Your Hardware Warranty): Updated/Changed the "Consequently, TI will have no …" sentence in the paragraphGo
  • (Thermal Resistance Characteristics): Added NoteGo
  • (Thermal Resistance Characteristics for ALW and AMC Package): Updated the thermal parameter values for the ALW package that is not AEC - Q100 qualified, and added thermal parameter values for the ALW package that is AEC - Q100 qualifiedGo
  • (Temperature Sensor Characteristics): Added new section to define Voltage and Temperature Module (VTM) on die temperature sensor characteristicsGo
  • (Power-Up Sequencing): Added note to clarify power rails must decay below 300mv before initiating a new power-up sequenceGo
  • (Power-Up Sequencing): Added the missing VDDA_1P8_OLDI0 power rail to Waveform C in the Power-Up Sequencing - Supply / Signal Assignments tableGo
  • (Power-Down Sequencing): Added note to clarify power rails must decay below 300mv before initiating a new power-up sequenceGo
  • (Power-Down Sequencing): Added the missing VDDA_1P8_OLDI0 power rail to Waveform C in the Power-Down Sequencing - Supply / Signal Assignments tableGo
  • (Power-Down Sequencing – Supply / Signal Assignments): Changed VDDSHV_CANUART to VDD_CANUART in table note 4Go
  • (Power-Down Sequencing): Updated the Power-Down Sequence diagram to account for a use case where the system power remains turned on while the device power management solution is turned off. Also included an option that allows the ramp-down of IO power rails to be extended until the last core power rail ramps down and it is possible for MCU_PORz to be asserted before the supplies begin to sequence offGo
  • (Reset Timing Conditions): Changed the Input slew rate minimum values for VDD = 1.8V and VDD = 3.3V (original values were swapped)Go
  • (BOOTMODE Timing Requirements): Updated the description for parameters RST23 and RST24Go
  • (Input Clocks / Oscillators): Added VOUT0_EXTPCLKINGo
  • (MCU_OSC0 LVCMOS Digital Clock Source): Added additional notes and the new MCU_OSC0 LVCMOS Digital Clock Source Requirements tableGo
  • (WKUP_LFOSC0 Crystal Electrical Characteristics) Included a new parameter that defines the maximum Crystal Frequency Stability and Tolerance.Go
  • (PLLs): Updated the PLL names to include it's number reference used in the TRMGo
  • (CPSW3G MDIO Timing): Changed the minimum setup time value (parameter MDIO1) from "90" to "45". Also changed the minimum and maximum output delay time values (parameter MDIO7) from "-150" and "150" to "-10" and "10" respectivelyGo
  • (CPSW3G MDIO Timing Conditions): Added propagation delay and propagation delay mismatch timing parametersGo
  • (CPSW3G RMII Timing Conditions): Changed the maximum input slew rate for both operating voltagesGo
  • (CPSW3G RGMII Timing Conditions): Added operating voltage conditions to the Input Slew Rate parameter to allow a relaxed slew rate when operating at 1.8VGo
  • (CPTS): Updated reference name for the TRM section under the timing tables.Go
  • (CSI-2): Included a comment in the note that explains port instance name relationship and removed the first paragraph since it didn't contain any information related to Timing and Switching CharacteristicsGo
  • (ECAP – Timing Requirements and Switching Characteristics): Updated the clock source referenced in table note 1Go
  • (EPWM – Timing Requirements and Switching Characteristics): Updated the clock source referenced in table note 1Go
  • (EQEP – Timing Requirements): Updated the clock source referenced in table note 1Go
  • (GPIO Timing Conditions): Updated the Input slew rate parameter to include operating voltage with relaxed minimum values and corrected a typographical error on the maximum value of the I2C OD FS buffer type operating at 3.3V. The previous maximum value of 0.8V/ns should have been 0.08V/ns for it to be equivalent to the maximum value of 8E+7 defined in the Electrical Characteristics table for the I2C OD FS bufferGo
  • (GPIO Timing Requirements): Removed the voltage conditions in the MODE column and changed the minimum value to accommodate the reduced minimum Input Slew Rate values in the GPIO Timing Conditions tableGo
  • (GPMC and NOR Flash Timing Requirements — Synchronous Mode): Removed the GPMC_FCLK=100MHz column timing values and the associated not_div_by_1_mode timing values for GPMC_FCLK=133MHz. Simplified several parameter descriptions. Also removed two table notes, one that described register configuration for GPMC_FCLK selection, and another that described register configuration for div_by_1_modeGo
  • (GPMC and NOR Flash Switching Characteristics – Synchronous Mode): Removed the GPMC_FCLK=100MHz column timing values and the associated not_div_by_1_mode timing values for GPMC_FCLK=133MHz. Simplified several parameter descriptions. Changed the timing variable in parameters F3 and F11 to "D". Removed the "J" timing variable from the F15 and F17 parameters. Updated the table notesGo
  • (GPMC and NOR Flash Timing Requirements – Asynchronous Mode): Removed the MODE column and the table note that described register configuration for div_by_1_mode. Added the correct table note for parameter FA21 Go
  • (GPMC and NOR Flash Switching Characteristics – Asynchronous Mode): Removed the MODE column and redundant rows. Also removed the table note that described register configuration for div_by_1_modeGo
  • (GPMC and NAND Flash Timing Requirements – Asynchronous Mode): Removed the MODE column and the table note that described register configuration for div_by_1_modeGo
  • (GPMC and NAND Flash Switching Characteristics – Asynchronous Mode): Removed the MODE column and the table note that described register configuration for div_by_1_mode. Added table notes and associated reference links for timing variables B, C, D, E, F, G, H, I, K, L, and MGo
  • (I2C): Changed the maximum slew rate value from 0.8V/ns to 0.08V/ns and added "when operating at 3.3V" to clarify the exception is not applicable to 1.8V operationGo
  • (I2C): Changed the supported speeds and exception descriptions so they are organized based on IO buffer type rather than I2C port instanceGo
  • (MCAN): Updated reference name for the TRM section under the timing tables.Go
  • (MCASP): Changed the IOSET note that explains timing limitations associated with valid pin combinationsGo
  • (MCSPI): Changed the IOSET note that explains timing limitations associated with valid pin combinationsGo
  • (MCSPI Switching Characteristics - Controller Mode): Replaced previous table notes 2 and 3 with new table notes 2, 3, 4, and 5Go
  • (MMC0 - eMMC/SD/SDIO Interface): Clarified the Default Speed, High Speed, UHS-I SDR12, and UHS-I SDR25 modes are only available for connectivity to embedded SDIO devices, and removed the UHS-I SDR50, UHS-I DDR50, and UHS-I SDR104 modesGo
  • (MMC0 DLL Delay Mapping for all Timing Modes): Changed the register name, changed the OTAPDLYENA and OTAPDLYSEL values for Legacy SDR, High Speed SDR, Default Speed, and High Speed modes, and removed the CLKBUFSEL column because this register bit field doesn't provide any functionGo
  • (HS200 Mode): Added "MMC0 Timing RequirementsGo
  • (MMC1/MMC2 DLL Delay Mapping for all Timing Modes): Changed the register names, and changed the OTAPDLYENA and OTAPDLYSEL values for Default Speed and High Speed modesGo
  • (MMC1/MMC2 DLL Delay Mapping for all Timing Modes): Removed the CLKBUFSEL column because this register bit field doesn't provide any functionGo
  • (OLDI0 Switching Characteristics): Changed the formulas in parameters OLDI5 through OLDI11Go
  • (OSPI0 DLL Delay Mapping for PHY Data Training): Added a delay value for the "PHY_MASTER_PHASE_DETECT_SELECTOR_FLD" register bit fieldGo
  • (OSPI0 Timing Requirements – PHY Data Training): Added three new timing parameters. Two that define timing parameters associated with SRD with External Board Loopback, and one that defines the minimum input data valid window for each mode. Also updated Note 1 to clarify the purpose of the new data valid window parameterGo
  • (OSPI0 Timing Requirements – PHY Data Training, SDR with External Board Loopback): Added a new timing requirements diagram for SDR with External Board LoopbackGo
  • (OSPI Switching Characteristics – PHY Data Training): Added seven new timing parameters. Six that define timing parameters associated with SRD with External Board Loopback, and one that defines the maximum output data valid window for each modeGo
  • (OSPI Switching Characteristics – PHY Data Training): Corrected the formulas associated with timing parameters O5 and O11Go
  • (OSPI0 Switching Characteristics – PHY SDR Data Training): Added a new switching characteristics diagram for SDR with External Board LoopbackGo
  • (OSPI0 DLL Delay Mapping for PHY SDR Timing Modes): Added a delay value for the "PHY_MASTER_PHASE_DETECT_SELECTOR_FLD" register bit fieldGo
  • (OSPI0 Switching Characteristics – PHY SDR Mode): Corrected the formulas associated with timing parameters O10 and O11Go
  • (OSPI0 DLL Delay Mapping for PHY DDR Timing Modes): Added a delay value for the "PHY_MASTER_PHASE_DETECT_SELECTOR_FLD" register bit fieldGo
  • (OSPI0 Switching Characteristics – PHY DDR Mode): Corrected the formulas associated with timing parameters O4 and O5Go
  • (Overview): Removed the list of applications and corrected typographical errorsGo
  • (Overview): Removed sentence describing package optionsGo
  • (Detailed Description – A53SS): Added clarification regarding the A53SS features supported by the device.Go
  • (Detailed Description – DMSS): Added reference to the TRM to ensure consistency with the structure and formatting of other sections in the datasheet.Go
  • (Detailed Description – PDMA): Added clarification regarding the PDMA features supported by the deviceGo
  • (Detailed Description – CPSW3G): Added clarification regarding the CPSW3G features supported by the device.Go
  • (Detailed Description – DDRSS): Added clarification regarding the DDRSS features supported by the device.Go
  • (Detailed Description – ECAP): Added clarification regarding the ECAP features supported by the device.Go
  • (Detailed Description – ELM): Added clarification regarding the ELM features supported by the device.Go
  • (Detailed Description – EPWM): Added clarification regarding the EPWM features supported by the device.Go
  • (Detailed Description – EQEP): Added clarification regarding the EQEP features supported by the deviceGo
  • (Detailed Description – GPIO): Added clarification regarding the GPIO features supported by the device.Go
  • (Detailed Description – GTC): Added clarification regarding the GTC features supported by the deviceGo
  • (Detailed Description – I2C): Updated the first sentence to ensure consistency with the structure and formatting of other sections in the datasheet and updated the I/O buffer referencesGo
  • (Detailed Description – MCAN): Added clarification regarding the MCAN features supported by the device.Go
  • (Detailed Description – McASP): Removed the first sentence to ensure consistency with the structure and formatting of other sections in the documentGo
  • (Detailed Description – MCSPI): Added clarification regarding the MCSPI features supported by the deviceGo
  • (Detailed Description – MMCSD): Added clarification regarding the MMCSD features supported by the device.Go
  • (Detailed Descriprion - OSPI): Added clarification regarding the OSPI features supported by the device.Go
  • (Detailed Description – Timers): Added clarification regarding the Timers features supported by the deviceGo
  • (Detailed Description – UART): Added clarification regarding the UART features supported by the deviceGo
  • (Detailed Description – USBSS): Added clarification regarding the USBSS features supported by the deviceGo
  • (USB VBUS Design Guidelines): Changed the 3.5kΩ resistor value to 3.48kΩ since 3.5kΩ is not a standard value for 1% resistorsGo
  • (Clock Routing Guidelines): Added new sectionGo
  • (Device Naming Convention): Added Device revision BGo
  • (Tools and Software): Added clarification regarding the SysConfig featuresGo