SPRSP58C June   2022  – October 2025 AM620-Q1 , AM623 , AM625 , AM625-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Terminal Configuration and Functions
    1. 5.1 Pin Diagrams
    2. 5.2 Pin Attributes
      1.      11
      2.      12
    3. 5.3 Signal Descriptions
      1.      14
      2. 5.3.1  CPSW3G
        1. 5.3.1.1 MAIN Domain
          1.        17
          2.        18
          3.        19
          4.        20
      3. 5.3.2  CPTS
        1. 5.3.2.1 MAIN Domain
          1.        23
      4. 5.3.3  CSI-2
        1. 5.3.3.1 MAIN Domain
          1.        26
      5. 5.3.4  DDRSS
        1. 5.3.4.1 MAIN Domain
          1.        29
      6. 5.3.5  DSS
        1. 5.3.5.1 MAIN Domain
          1.        32
      7. 5.3.6  ECAP
        1. 5.3.6.1 MAIN Domain
          1.        35
          2.        36
          3.        37
      8. 5.3.7  Emulation and Debug
        1. 5.3.7.1 MAIN Domain
          1.        40
        2. 5.3.7.2 MCU Domain
          1.        42
      9. 5.3.8  EPWM
        1. 5.3.8.1 MAIN Domain
          1.        45
          2.        46
          3.        47
          4.        48
      10. 5.3.9  EQEP
        1. 5.3.9.1 MAIN Domain
          1.        51
          2.        52
          3.        53
      11. 5.3.10 GPIO
        1. 5.3.10.1 MAIN Domain
          1.        56
          2.        57
        2. 5.3.10.2 MCU Domain
          1.        59
      12. 5.3.11 GPMC
        1. 5.3.11.1 MAIN Domain
          1.        62
      13. 5.3.12 I2C
        1. 5.3.12.1 MAIN Domain
          1.        65
          2.        66
          3.        67
          4.        68
        2. 5.3.12.2 MCU Domain
          1.        70
        3. 5.3.12.3 WKUP Domain
          1.        72
      14. 5.3.13 MCAN
        1. 5.3.13.1 MAIN Domain
          1.        75
        2. 5.3.13.2 MCU Domain
          1.        77
          2.        78
      15. 5.3.14 MCASP
        1. 5.3.14.1 MAIN Domain
          1.        81
          2.        82
          3.        83
      16. 5.3.15 MCSPI
        1. 5.3.15.1 MAIN Domain
          1.        86
          2.        87
          3.        88
        2. 5.3.15.2 MCU Domain
          1.        90
          2.        91
      17. 5.3.16 MDIO
        1. 5.3.16.1 MAIN Domain
          1.        94
      18. 5.3.17 MMC
        1. 5.3.17.1 MAIN Domain
          1.        97
          2.        98
          3.        99
      19. 5.3.18 OLDI
        1. 5.3.18.1 MAIN Domain
          1.        102
      20. 5.3.19 OSPI
        1. 5.3.19.1 MAIN Domain
          1.        105
      21. 5.3.20 Power Supply
        1.       107
      22. 5.3.21 PRUSS
        1. 5.3.21.1 MAIN Domain
          1.        110
          2.        111
      23. 5.3.22 Reserved
        1.       113
      24. 5.3.23 System and Miscellaneous
        1. 5.3.23.1 Boot Mode Configuration
          1. 5.3.23.1.1 MAIN Domain
            1.         117
        2. 5.3.23.2 Clock
          1. 5.3.23.2.1 MCU Domain
            1.         120
          2. 5.3.23.2.2 WKUP Domain
            1.         122
        3. 5.3.23.3 System
          1. 5.3.23.3.1 MAIN Domain
            1.         125
          2. 5.3.23.3.2 MCU Domain
            1.         127
          3. 5.3.23.3.3 WKUP Domain
            1.         129
        4. 5.3.23.4 VMON
          1.        131
      25. 5.3.24 TIMER
        1. 5.3.24.1 MAIN Domain
          1.        134
        2. 5.3.24.2 MCU Domain
          1.        136
        3. 5.3.24.3 WKUP Domain
          1.        138
      26. 5.3.25 UART
        1. 5.3.25.1 MAIN Domain
          1.        141
          2.        142
          3.        143
          4.        144
          5.        145
          6.        146
          7.        147
        2. 5.3.25.2 MCU Domain
          1.        149
        3. 5.3.25.3 WKUP Domain
          1.        151
      27. 5.3.26 USB
        1. 5.3.26.1 MAIN Domain
          1.        154
          2.        155
    4. 5.4 Pin Connectivity Requirements
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings for Devices which are not AEC - Q100 Qualified
    3. 6.3  ESD Ratings for AEC - Q100 Qualified Devices
    4. 6.4  Power-On Hours (POH)
    5. 6.5  Recommended Operating Conditions
    6. 6.6  Operating Performance Points
    7. 6.7  Power Consumption Summary
    8. 6.8  Electrical Characteristics
      1. 6.8.1  I2C Open-Drain, and Fail-Safe (I2C OD FS) Electrical Characteristics
      2. 6.8.2  Fail-Safe Reset (FS RESET) Electrical Characteristics
      3. 6.8.3  High-Frequency Oscillator (HFOSC) Electrical Characteristics
      4. 6.8.4  Low-Frequency Oscillator (LFXOSC) Electrical Characteristics
      5. 6.8.5  SDIO Electrical Characteristics
      6. 6.8.6  LVCMOS Electrical Characteristics
      7. 6.8.7  OLDI LVDS (OLDI) Electrical Characteristics
      8. 6.8.8  CSI-2 (D-PHY) Electrical Characteristics
      9. 6.8.9  USB2PHY Electrical Characteristics
      10. 6.8.10 DDR Electrical Characteristics
    9. 6.9  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 6.9.1 Recommended Operating Conditions for OTP eFuse Programming
      2. 6.9.2 Hardware Requirements
      3. 6.9.3 Programming Sequence
      4. 6.9.4 Impact to Your Hardware Warranty
    10. 6.10 Thermal Resistance Characteristics
      1. 6.10.1 Thermal Resistance Characteristics for ALW and AMC Packages
    11. 6.11 Temperature Sensor Characteristics
    12. 6.12 Timing and Switching Characteristics
      1. 6.12.1 Timing Parameters and Information
      2. 6.12.2 Power Supply Requirements
        1. 6.12.2.1 Power Supply Slew Rate Requirement
        2. 6.12.2.2 Power Supply Sequencing
          1. 6.12.2.2.1 Power-Up Sequencing
          2. 6.12.2.2.2 Power-Down Sequencing
          3. 6.12.2.2.3 Partial IO Power Sequencing
      3. 6.12.3 System Timing
        1. 6.12.3.1 Reset Timing
        2. 6.12.3.2 Error Signal Timing
        3. 6.12.3.3 Clock Timing
      4. 6.12.4 Clock Specifications
        1. 6.12.4.1 Input Clocks / Oscillators
          1. 6.12.4.1.1 MCU_OSC0 Internal Oscillator Clock Source
            1. 6.12.4.1.1.1 Load Capacitance
            2. 6.12.4.1.1.2 Shunt Capacitance
          2. 6.12.4.1.2 MCU_OSC0 LVCMOS Digital Clock Source
          3. 6.12.4.1.3 WKUP_LFOSC0 Internal Oscillator Clock Source
          4. 6.12.4.1.4 WKUP_LFOSC0 LVCMOS Digital Clock Source
          5. 6.12.4.1.5 WKUP_LFOSC0 Not Used
        2. 6.12.4.2 Output Clocks
        3. 6.12.4.3 PLLs
        4. 6.12.4.4 Recommended System Precautions for Clock and Control Signal Transitions
      5. 6.12.5 Peripherals
        1. 6.12.5.1  CPSW3G
          1. 6.12.5.1.1 CPSW3G MDIO Timing
          2. 6.12.5.1.2 CPSW3G RMII Timing
          3. 6.12.5.1.3 CPSW3G RGMII Timing
        2. 6.12.5.2  CPTS
        3. 6.12.5.3  CSI-2
        4. 6.12.5.4  DDRSS
        5. 6.12.5.5  DSS
        6. 6.12.5.6  ECAP
        7. 6.12.5.7  Emulation and Debug
          1. 6.12.5.7.1 Trace
          2. 6.12.5.7.2 JTAG
        8. 6.12.5.8  EPWM
        9. 6.12.5.9  EQEP
        10. 6.12.5.10 GPIO
        11. 6.12.5.11 GPMC
          1. 6.12.5.11.1 GPMC and NOR Flash — Synchronous Mode
          2. 6.12.5.11.2 GPMC and NOR Flash — Asynchronous Mode
          3. 6.12.5.11.3 GPMC and NAND Flash — Asynchronous Mode
        12. 6.12.5.12 I2C
        13. 6.12.5.13 MCAN
        14. 6.12.5.14 MCASP
        15. 6.12.5.15 MCSPI
          1. 6.12.5.15.1 MCSPI — Controller Mode
          2. 6.12.5.15.2 MCSPI — Peripheral Mode
        16. 6.12.5.16 MMCSD
          1. 6.12.5.16.1 MMC0 - eMMC/SD/SDIO Interface
            1. 6.12.5.16.1.1  Legacy SDR Mode
            2. 6.12.5.16.1.2  High Speed SDR Mode
            3. 6.12.5.16.1.3  HS200 Mode
            4. 6.12.5.16.1.4  Default Speed Mode
            5. 6.12.5.16.1.5  High Speed Mode
            6. 6.12.5.16.1.6  UHS–I SDR12 Mode
            7. 6.12.5.16.1.7  UHS–I SDR25 Mode
            8. 6.12.5.16.1.8  UHS–I SDR50 Mode
            9. 6.12.5.16.1.9  UHS–I DDR50 Mode
            10. 6.12.5.16.1.10 UHS–I SDR104 Mode
          2. 6.12.5.16.2 MMC1/MMC2 - SD/SDIO Interface
            1. 6.12.5.16.2.1 Default Speed Mode
            2. 6.12.5.16.2.2 High Speed Mode
            3. 6.12.5.16.2.3 UHS–I SDR12 Mode
            4. 6.12.5.16.2.4 UHS–I SDR25 Mode
            5. 6.12.5.16.2.5 UHS–I SDR50 Mode
            6. 6.12.5.16.2.6 UHS–I DDR50 Mode
            7. 6.12.5.16.2.7 UHS–I SDR104 Mode
        17. 6.12.5.17 OLDI
          1. 6.12.5.17.1 OLDI0 Switching Characteristics
        18. 6.12.5.18 OSPI
          1. 6.12.5.18.1 OSPI0 PHY Mode
            1. 6.12.5.18.1.1 OSPI0 With PHY Data Training
            2. 6.12.5.18.1.2 OSPI0 Without Data Training
              1. 6.12.5.18.1.2.1 OSPI0 PHY SDR Timing
              2. 6.12.5.18.1.2.2 OSPI0 PHY DDR Timing
          2. 6.12.5.18.2 OSPI0 Tap Mode
            1. 6.12.5.18.2.1 OSPI0 Tap SDR Timing
            2. 6.12.5.18.2.2 OSPI0 Tap DDR Timing
        19. 6.12.5.19 PRUSS
          1. 6.12.5.19.1 PRUSS Programmable Real-Time Unit (PRU)
            1. 6.12.5.19.1.1 PRUSS PRU Direct Output Mode Timing
            2. 6.12.5.19.1.2 PRUSS PRU Parallel Capture Mode Timing
            3. 6.12.5.19.1.3 PRUSS PRU Shift Mode Timing
          2. 6.12.5.19.2 PRUSS Industrial Ethernet Peripheral (IEP)
            1. 6.12.5.19.2.1 PRUSS IEP Timing
          3. 6.12.5.19.3 PRUSS Universal Asynchronous Receiver Transmitter (UART)
            1. 6.12.5.19.3.1 PRUSS UART Timing
          4. 6.12.5.19.4 PRUSS Enhanced Capture Peripheral (ECAP)
            1. 6.12.5.19.4.1 PRUSS ECAP Timing
        20. 6.12.5.20 Timers
        21. 6.12.5.21 UART
        22. 6.12.5.22 USB
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Processor Subsystems
      1. 7.2.1 Arm Cortex-A53 Subsystem (A53SS)
      2. 7.2.2 Device/Power Manager
      3. 7.2.3 Arm Cortex-M4F
    3. 7.3 Accelerators and Coprocessors
      1. 7.3.1 Graphics Processing Unit (GPU)
      2. 7.3.2 Programmable Real-Time Unit Subsystem (PRUSS)
    4. 7.4 Other Subsystems
      1. 7.4.1 Dual Clock Comparator (DCC)
      2. 7.4.2 Data Movement Subsystem (DMSS)
      3. 7.4.3 Memory Cyclic Redundancy Check (MCRC)
      4. 7.4.4 Peripheral DMA Controller (PDMA)
      5. 7.4.5 Real-Time Clock (RTC)
    5. 7.5 Peripherals
      1. 7.5.1  Gigabit Ethernet Switch (CPSW3G)
      2. 7.5.2  Camera Serial Interface Receiver (CSI_RX_IF)
      3. 7.5.3  DDR Subsystem (DDRSS)
      4. 7.5.4  Display Subsystem (DSS)
      5. 7.5.5  Enhanced Capture (ECAP)
      6. 7.5.6  Error Location Module (ELM)
      7. 7.5.7  Enhanced Pulse Width Modulation (EPWM)
      8. 7.5.8  Error Signaling Module (ESM)
      9. 7.5.9  Enhanced Quadrature Encoder Pulse (EQEP)
      10. 7.5.10 General-Purpose Interface (GPIO)
      11. 7.5.11 General-Purpose Memory Controller (GPMC)
      12. 7.5.12 Global Timebase Counter (GTC)
      13. 7.5.13 Inter-Integrated Circuit (I2C)
      14. 7.5.14 Modular Controller Area Network (MCAN)
      15. 7.5.15 Multichannel Audio Serial Port (MCASP)
      16. 7.5.16 Multichannel Serial Peripheral Interface (MCSPI)
      17. 7.5.17 Multi-Media Card Secure Digital (MMCSD)
      18. 7.5.18 Octal Serial Peripheral Interface (OSPI)
      19. 7.5.19 Timers
      20. 7.5.20 Universal Asynchronous Receiver/Transmitter (UART)
      21. 7.5.21 Universal Serial Bus Subsystem (USBSS)
  9. 8 Applications, Implementation, and Layout
    1. 8.1 Device Connection and Layout Fundamentals
      1. 8.1.1 Power Supply
        1. 8.1.1.1 Power Supply Designs
        2. 8.1.1.2 Power Distribution Network Implementation Guidance
      2. 8.1.2 External Oscillator
      3. 8.1.3 JTAG, EMU, and TRACE
      4. 8.1.4 Unused Pins
    2. 8.2 Peripheral- and Interface-Specific Design Information
      1. 8.2.1 DDR Board Design and Layout Guidelines
      2. 8.2.2 OSPI/QSPI/SPI Board Design and Layout Guidelines
        1. 8.2.2.1 No Loopback, Internal PHY Loopback, and Internal Pad Loopback
        2. 8.2.2.2 External Board Loopback
        3. 8.2.2.3 DQS (only available in Octal SPI devices)
      3. 8.2.3 USB VBUS Design Guidelines
      4. 8.2.4 System Power Supply Monitor Design Guidelines
      5. 8.2.5 High Speed Differential Signal Routing Guidance
      6. 8.2.6 Thermal Solution Guidance
    3. 8.3 Clock Routing Guidelines
      1. 8.3.1 Oscillator Routing
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
      1. 9.1.1 Standard Package Symbolization
      2. 9.1.2 Device Naming Convention
    2. 9.2 Tools and Software
    3. 9.3 Documentation Support
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • AMC|441
  • ALW|425
Thermal pad, mechanical data (Package|Pins)
Orderable Information
6.12.2.2.2 Power-Down Sequencing

Table 6-6 and Figure 6-6 describes the device power-down sequencing.

Note: The power supply sequencing requirements defined in this section does not include entry or exit from low power modes. See Section 6.12.2.2.3, Partial IO Power Sequencing for more information on power supply sequence requirements when entering or exiting low power modes.
Note: All power rails must be turned off and decay below 300mV before initiating a new power-up sequence anytime a power rail drops below the minimum value defined in Recommended Operating Conditions. The only exception is when entering/exiting Partial IO low power mode with VDDSHV_CANUART and VDD_CANUART sourced from an always on power source. For this use case the VDDSHV_CANUART and VDD_CANUART power rails are allowed to remain on.
Table 6-6 Power-Down Sequencing – Supply / Signal Assignments See: Figure 6-6
WAVEFORM SUPPLY / SIGNAL NAME
A VSYS, VMON_VSYS
B VDDSHV_CANUART(1), VDDSHV_MCU(1), VDDSHV0(1), VDDSHV1(1), VDDSHV2(1), VDDSHV3(1), VDDA_3P3_USB, VMON_3P3_SOC
C VDDSHV_CANUART(2), VDDSHV_MCU(2), VDDSHV0(2), VDDSHV1(2), VDDSHV2(2), VDDSHV3(2), VDDA_MCU, VDDS_OSC0, VDDA_PLL0, VDDA_PLL1, VDDA_PLL2, VDDA_1P8_CSIRX0, VDDA_1P8_OLDI0, VDDA_1P8_USB, VDDA_TEMP0, VDDA_TEMP1, VMON_1P8_SOC
D VDDSHV4(3), VDDSHV5(3), VDDSHV6(3)
E VDDS_DDR, VDDS_DDR_C
F VDD_CANUART(4)
G VDD_CANUART(5), VDD_CORE(5), VDDA_CORE_CSIRX0(5), VDDA_CORE_USB0(5), VDDA_DDR_PLL0(5)
H VDD_CANUART(6), VDD_CORE(6), VDDA_CORE_CSIRX0(6), VDDA_CORE_USB0(6), VDDA_DDR_PLL0(6), VDDR_CORE
I VPP
J MCU_PORz
K MCU_OSC0_XI, MCU_OSC0_XO
(1) VDDSHV_CANUART, VDDSHV_MCU, and VDDSHVx [x=0-3] when operating at 3.3V.
(2) VDDSHV_CANUART, VDDSHV_MCU, and VDDSHVx [x=0-3] when operating at 1.8V.
(3) VDDSHV4, VDDSHV5, and VDDSHV6 were designed to support power-up, power-down, or dynamic voltage change without any dependency on other power rails. This capability is required to support UHS-I SD Cards.
(4) VDD_CANUART when connected to an always-on power source for Partial IO low power mode.
(5) VDD_CANUART, VDD_CORE, VDDA_CORE_CSIRX0, VDDA_CORE_USB0, and VDDA_DDR_PLL0 when operating at 0.75V
(6) VDD_CANUART, VDD_CORE, VDDA_CORE_CSIRX0, VDDA_CORE_USB0, and VDDA_DDR_PLL0 when operating at 0.85V
AM625 AM625-Q1 AM623 AM620-Q1 Power-Down Sequencing Figure 6-6 Power-Down Sequencing