SPRSP56B January   2021  – August 2021 AM6411 , AM6412 , AM6421 , AM6441 , AM6442

ADVANCE INFORMATION  

  1. Features
  2. Applications
  3. Description
    1. 3.1 Functional Block Diagram
  4. Revision History
  5. Device Comparison
    1. 5.1 Related Products
  6. Terminal Configuration and Functions
    1. 6.1 Pin Diagram
    2. 6.2 Pin Attributes
    3. 6.3 Signal Descriptions
      1. 6.3.1  ADC
        1. 6.3.1.1 MAIN Domain
      2. 6.3.2  DDRSS
        1. 6.3.2.1 MAIN Domain
      3. 6.3.3  GPIO
        1. 6.3.3.1 MAIN Domain
        2. 6.3.3.2 MCU Domain
      4. 6.3.4  I2C
        1. 6.3.4.1 MAIN Domain
        2. 6.3.4.2 MCU Domain
      5. 6.3.5  MCAN
        1. 6.3.5.1 MAIN Domain
      6. 6.3.6  MCSPI
        1. 6.3.6.1 MAIN Domain
        2. 6.3.6.2 MCU Domain
      7. 6.3.7  UART
        1. 6.3.7.1 MAIN Domain
        2. 6.3.7.2 MCU Domain
      8. 6.3.8  MDIO
        1. 6.3.8.1 MAIN Domain
      9. 6.3.9  CPSW3G
        1. 6.3.9.1 MAIN Domain
      10. 6.3.10 ECAP
        1. 6.3.10.1 MAIN Domain
      11. 6.3.11 EQEP
        1. 6.3.11.1 MAIN Domain
      12. 6.3.12 EPWM
        1. 6.3.12.1 MAIN Domain
      13. 6.3.13 SERDES
        1. 6.3.13.1 MAIN Domain
      14. 6.3.14 USB
        1. 6.3.14.1 MAIN Domain
      15. 6.3.15 OSPI
        1. 6.3.15.1 MAIN Domain
      16. 6.3.16 GPMC
        1. 6.3.16.1 MAIN Domain
      17. 6.3.17 MMC
        1. 6.3.17.1 MAIN Domain
      18. 6.3.18 FSI
        1. 6.3.18.1 MAIN Domain
      19. 6.3.19 CPTS
        1. 6.3.19.1 MAIN Domain
      20. 6.3.20 PRU_ICSSG
        1. 6.3.20.1 MAIN Domain
      21. 6.3.21 DMTIMER
        1. 6.3.21.1 MAIN Domain
        2. 6.3.21.2 MCU Domain
      22. 6.3.22 Emulation and Debug
        1. 6.3.22.1 MAIN Domain
        2. 6.3.22.2 MCU Domain
      23. 6.3.23 System and Miscellaneous
        1. 6.3.23.1 Boot Mode Configuration
          1. 6.3.23.1.1 MAIN Domain
        2. 6.3.23.2 Clock
          1. 6.3.23.2.1 MCU Domain
        3. 6.3.23.3 System
          1. 6.3.23.3.1 MAIN Domain
          2. 6.3.23.3.2 MCU Domain
        4. 6.3.23.4 VMON
      24. 6.3.24 Power Supply
    4. 6.4 Pin Multiplexing
    5. 6.5 Connections for Unused Pins
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Power-On Hours (POH)
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Operating Performance Points
    6. 7.6  Power Consumption Summary
    7. 7.7  Electrical Characteristics
      1. 7.7.1  I2C Open-Drain, and Fail-Safe (I2C OD FS) Electrical Characteristics
      2. 7.7.2  Fail-Safe Reset (FS RESET) Electrical Characteristics
      3. 7.7.3  High-Frequency Oscillator (HFOSC) Electrical Characteristics
      4. 7.7.4  eMMCPHY Electrical Characteristics
      5. 7.7.5  SDIO Electrical Characteristics
      6. 7.7.6  LVCMOS Electrical Characteristics
      7. 7.7.7  ADC12B Electrical Characteristics
      8. 7.7.8  USB2PHY Electrical Characteristics
      9. 7.7.9  SERDES Electrical Characteristics
      10. 7.7.10 DDR Electrical Characteristics
    8. 7.8  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 7.8.1 Recommended Operating Conditions for OTP eFuse Programming
      2. 7.8.2 Hardware Requirements
      3. 7.8.3 Programming Sequence
      4. 7.8.4 Impact to Your Hardware Warranty
    9. 7.9  Thermal Resistance Characteristics
      1. 7.9.1 Thermal Resistance Characteristics
    10. 7.10 Timing and Switching Characteristics
      1. 7.10.1 Timing Parameters and Information
      2. 7.10.2 Power Supply Sequencing
        1. 7.10.2.1 Power Supply Slew Rate Requirement
        2. 7.10.2.2 Power-Up Sequencing
        3. 7.10.2.3 Power-Down Sequencing
      3. 7.10.3 System Timing
        1. 7.10.3.1 Reset Timing
        2. 7.10.3.2 Safety Signal Timing
        3. 7.10.3.3 Clock Timing
      4. 7.10.4 Clock Specifications
        1. 7.10.4.1 Input Clocks / Oscillators
          1. 7.10.4.1.1 MCU_OSC0 Internal Oscillator Clock Source
            1. 7.10.4.1.1.1 Load Capacitance
            2. 7.10.4.1.1.2 Shunt Capacitance
          2. 7.10.4.1.2 MCU_OSC0 LVCMOS Digital Clock Source
        2. 7.10.4.2 Output Clocks
        3. 7.10.4.3 PLLs
      5. 7.10.5 Peripherals
        1. 7.10.5.1  CPSW3G
          1. 7.10.5.1.1 CPSW3G MDIO Timing
          2. 7.10.5.1.2 CPSW3G RMII Timing
          3. 7.10.5.1.3 CPSW3G RGMII Timing
          4. 7.10.5.1.4 CPSW3G IOSETs
        2. 7.10.5.2  DDRSS
        3. 7.10.5.3  ECAP
        4. 7.10.5.4  EPWM
        5. 7.10.5.5  EQEP
        6. 7.10.5.6  FSI
        7. 7.10.5.7  GPIO
        8. 7.10.5.8  GPMC
          1. 7.10.5.8.1 GPMC and NOR Flash — Synchronous Mode
          2. 7.10.5.8.2 GPMC and NOR Flash — Asynchronous Mode
          3. 7.10.5.8.3 GPMC and NAND Flash — Asynchronous Mode
          4. 7.10.5.8.4 GPMC IOSETs
        9. 7.10.5.9  I2C
          1. 7.10.5.9.1 Timing Requirements for I2C Input Timings
        10. 7.10.5.10 MCAN
        11. 7.10.5.11 MCSPI
          1. 7.10.5.11.1 MCSPI — Master Mode
          2. 7.10.5.11.2 MCSPI — Slave Mode
        12. 7.10.5.12 MMCSD
          1. 7.10.5.12.1 MMC0 - eMMC Interface
            1. 7.10.5.12.1.1 Legacy SDR Mode
            2. 7.10.5.12.1.2 High Speed SDR Mode
            3. 7.10.5.12.1.3 High Speed DDR Mode
            4. 7.10.5.12.1.4 HS200 Mode
          2. 7.10.5.12.2 MMC1 - SD/SDIO Interface
            1. 7.10.5.12.2.1 Default Speed Mode
            2. 7.10.5.12.2.2 High Speed Mode
            3. 7.10.5.12.2.3 UHS–I SDR12 Mode
            4. 7.10.5.12.2.4 UHS–I SDR25 Mode
            5. 7.10.5.12.2.5 UHS–I SDR50 Mode
            6. 7.10.5.12.2.6 UHS–I DDR50 Mode
            7. 7.10.5.12.2.7 UHS–I SDR104 Mode
        13. 7.10.5.13 CPTS
        14. 7.10.5.14 OSPI
          1. 7.10.5.14.1 OSPI With Data Training
            1. 7.10.5.14.1.1 OSPI Switching Characteristics – Data Training
          2. 7.10.5.14.2 OSPI Without Data Training
            1. 7.10.5.14.2.1 OSPI SDR Timing
            2. 7.10.5.14.2.2 OSPI DDR Timing
        15. 7.10.5.15 PCIe
        16. 7.10.5.16 PRU_ICSSG
          1. 7.10.5.16.1 PRU_ICSSG Programmable Real-Time Unit (PRU)
            1. 7.10.5.16.1.1 PRU_ICSSG PRU Direct Output Mode Timing
            2. 7.10.5.16.1.2 PRU_ICSSG PRU Parallel Capture Mode Timing
            3. 7.10.5.16.1.3 PRU_ICSSG PRU Shift Mode Timing
            4. 7.10.5.16.1.4 PRU_ICSSG PRU Sigma Delta and Peripheral Interface
              1. 7.10.5.16.1.4.1 PRU_ICSSG PRU Sigma Delta and Peripheral Interface Timing
          2. 7.10.5.16.2 PRU_ICSSG Pulse Width Modulation (PWM)
            1. 7.10.5.16.2.1 PRU_ICSSG PWM Timing
          3. 7.10.5.16.3 PRU_ICSSG Industrial Ethernet Peripheral (IEP)
            1. 7.10.5.16.3.1 PRU_ICSSG IEP Timing
          4. 7.10.5.16.4 PRU_ICSSG Universal Asynchronous Receiver Transmitter (UART)
            1. 7.10.5.16.4.1 PRU_ICSSG UART Timing
          5. 7.10.5.16.5 PRU_ICSSG Enhanced Capture Peripheral (ECAP)
            1. 7.10.5.16.5.1 PRU_ICSSG ECAP Timing
          6. 7.10.5.16.6 PRU_ICSSG RGMII, MII_RT, and Switch
            1. 7.10.5.16.6.1 PRU_ICSSG MDIO Timing
            2. 7.10.5.16.6.2 PRU_ICSSG MII Timing
            3. 7.10.5.16.6.3 PRU_ICSSG RGMII Timing
        17. 7.10.5.17 Timers
        18. 7.10.5.18 UART
        19. 7.10.5.19 USB
      6. 7.10.6 Emulation and Debug
        1. 7.10.6.1 Trace
        2. 7.10.6.2 JTAG
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Processor Subsystems
      1. 8.2.1 Arm Cortex-A53 Subsystem
      2. 8.2.2 Arm Cortex-R5F Subsystem (R5FSS)
      3. 8.2.3 Arm Cortex-M4F (M4FSS)
    3. 8.3 Accelerators and Coprocessors
      1. 8.3.1 Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU_ICSSG)
    4. 8.4 Other Subsystems
      1. 8.4.1 PDMA Controller
      2. 8.4.2 Peripherals
        1. 8.4.2.1  ADC
        2. 8.4.2.2  DCC
        3. 8.4.2.3  Dual Date Rate (DDR) External Memory Interface (DDRSS)
        4. 8.4.2.4  ECAP
        5. 8.4.2.5  EPWM
        6. 8.4.2.6  ELM
        7. 8.4.2.7  ESM
        8. 8.4.2.8  GPIO
        9. 8.4.2.9  EQEP
        10. 8.4.2.10 GPMC
        11. 8.4.2.11 I2C
        12. 8.4.2.12 MCAN
        13. 8.4.2.13 MCRC Controller
        14. 8.4.2.14 MCSPI
        15. 8.4.2.15 MMCSD
        16. 8.4.2.16 OSPI
        17. 8.4.2.17 Peripheral Component Interconnect Express (PCIe)
        18. 8.4.2.18 Serializer/Deserializer (SerDes)
        19. 8.4.2.19 RTI
        20. 8.4.2.20 DMTIMER
        21. 8.4.2.21 UART
        22. 8.4.2.22 Universal Serial Bus Subsystem(USBSS)
  9. Applications, Implementation, and Layout
    1. 9.1 Power Supply Mapping
    2. 9.2 Device Connection and Layout Fundamentals
      1. 9.2.1 Power Supply Decoupling and Bulk Capacitors
        1. 9.2.1.1 Power Distribution Network Implementation Guidance
      2. 9.2.2 External Oscillator
      3. 9.2.3 JTAG and EMU
      4. 9.2.4 Reset
      5. 9.2.5 Unused Pins
      6. 9.2.6 Hardware Design Guide
    3. 9.3 Peripheral- and Interface-Specific Design Information
      1. 9.3.1 DDR Board Design and Layout Guidelines
      2. 9.3.2 OSPI and QSPI Board Design and Layout Guidelines
        1. 9.3.2.1 No Loopback and Internal Pad Loopback
        2. 9.3.2.2 External Board Loopback
        3. 9.3.2.3 DQS (only available in Octal Flash devices)
      3. 9.3.3 USB VBUS Design Guidelines
      4. 9.3.4 System Power Supply Monitor Design Guidelines
      5. 9.3.5 High Speed Differential Signal Routing Guidance
      6. 9.3.6 External Capacitors
      7. 9.3.7 Thermal Solution Guidance
  10. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
      1. 10.1.1 Standard Package Symbolization
      2. 10.1.2 Device Naming Convention
    2. 10.2 Tools and Software
    3. 10.3 Documentation Support
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ALV|441
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Features

Processor cores:

  • 1× Dual 64-bit Arm®Cortex®-A53 microprocessor subsystem at up to 1.0 GHz
    • Dual-core Cortex-A53 cluster with 256KB L2 shared cache with SECDED ECC
    • Each A53 Core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection
  • Up to 2× Dual-core Arm®Cortex®-R5F MCU subsystems at at up to 800 MHz, integrated for real-time processing
    • Dual-core Arm®Cortex®-R5F supports dual-core and single-core modes
    • 32KB ICache, 32KB DCache and 64KB TCM per each R5F core for a total of 256KB TCM with SECDED ECC on all memories
  • 1× Single-core Arm®Cortex®-M4F MCU at up to 400 MHz
    • 256KB SRAM with SECDED ECC

Industrial subsystem:

  • 2× gigabit Industrial Communication Subsystems (PRU_ICSSG)
    • Supports Profinet IRT, Profinet RT, EtherNet/IP, EtherCAT, Time-Sensitive Networking (TSN), and more
    • Backward compatibility with 10/100Mb PRU_ICSS
    • Each PRU_ICSSG contains:
      • 2× Ethernet ports
        • MII (10/100)
        • RGMII (10/100/1000)
      • 6 PRU RISC cores per PRU_ICSSG each core having:
        • Instruction RAM with ECC
        • Broadside RAM
        • Multiplier with optional accumulator (MAC)
        • CRC16/32 hardware accelerator
        • Byte swap for Big/Little Endian conversion
        • SUM32 hardware accelerator for UDP checksum
        • Task Manager for preemption support
      • Three Data RAMs with ECC
      • 8 banks of 30 × 32-bit register scratchpad memory
      • Interrupt controller and task manager
      • Two 64-bit Industrial Ethernet Peripherals (IEPs) for time stamping and other time synchronization functions
      • 18× Sigma-Delta filters
        • Short circuit logic
        • Over-current logic
      • 6× Multi-protocol position encoder interfaces
      • One Enhanced Capture Module (ECAP)
      • 16550-compatible UART with a dedicated 192-MHz clock to support 12-Mbps PROFIBUS

Memory subsystem:

  • Up to 2MB of On-chip RAM (OCSRAM) with SECDED ECC:
    • Can be divided into smaller banks in increments of 256KB for as many as 8 separate memory banks
    • Each memory bank can be allocated to a single core to facilitate software task partitioning
  • DDR Subsystem (DDRSS)
    • Supports LPDDR4, DDR4 memory types
    • 16-Bit data bus with inline ECC
    • Supports speeds up to 1600 MT/s
  • 1× General-Purpose Memory Controller (GPMC)
    • 16-Bit parallel bus with 133 MHz clock or
    • 32-Bit parallel bus with 100 MHz clock
    • Error Location Module (ELM) support

System on Chip (SoC) Services:

  • Device Management Security Controller (DMSC-L)
    • Centralized SoC system controller
    • Manages system services including initial boot, security, and clock/reset/power management
    • Communication with various processing units over message manager
    • Simplified interface for optimizing unused peripherals
  • Data Movement Subsystem (DMSS)

    • Block Copy DMA (BCDMA)
    • Packet DMA (PKTDMA)
    • Secure Proxy (SEC_PROXY)
    • Ring Accelerator (RINGACC)

Security:

  • Secure boot supported
    • Hardware-enforced Root-of-Trust (RoT)
    • Support to switch RoT via backup key
    • Support for takeover protection, IP protection, and anti-roll back protection
  • Cryptographic acceleration supported
    • Session-aware cryptographic engine with ability to auto-switch key-material based on incoming data stream
    • Supports cryptographic cores
      • AES – 128/192/256 Bits key sizes
      • 3DES – 56/112/168 Bits key sizes
      • MD5, SHA1
      • SHA2 – 224/256/384/512
      • DRBG with true random number generator
      • PKA (Public Key Accelerator) to Assist in RSA/ECC processing
    • DMA support
  • Debugging security
    • Secure software controlled debug access
    • Security aware debugging
  • Trusted Execution Environment (TEE) supported
    • Arm TrustZone® based TEE
    • Extensive firewall support for isolation
    • Secure watchdog/timer/IPC
  • Secure storage support
  • On-the-Fly encryption and authentication support for OSPI interface in XIP mode
  • Networking security support for data (Payload) encryption/authentication via packet based hardware cryptographic engine
  • Security co-processor (DMSC-L) for key and security management, with dedicated device level interconnect for security

High-speed interfaces:

  • 1× Integrated Ethernet switch (CPSW3G) supporting
    • Up to 2 Ethernet ports
      • RMII (10/100)
      • RGMII (10/100/1000)
    • IEEE 1588 (2008 Annex D, Annex E, Annex F) with 802.1AS PTP
    • Clause 45 MDIO PHY management
    • Energy efficient Ethernet (802.3az)
  • PCI-Express® Gen2 controller (PCIE)
    • Supports Gen2 operation
    • Supports Single Lane operation
  • 1× USB 3.1-Gen1 Dual-Role Device (DRD) Subsystem (USBSS)
    • One enhanced SuperSpeed Gen1 port
    • Port configurable as USB host, USB peripheral, or USB Dual-Role Device
    • Integrated USB VBUS detection

General connectivity:

  • 6× Inter-Integrated Circuit (I2C) ports
  • 9× configurable Universal Asynchronous Recieve/Transmit (UART) modules
  • 1× Flash Subsystem (FSS) that can be configured as Octal SPI (OSPI) flash interfaces or one Quad SPI (QSPI)
  • 1× 12-Bit Analog-to-Digital Converters (ADC)
    • Up to 4 MSPS
    • 8× multiplexed analog inputs
  • 7× Multichannel Serial Peripheral Interfaces (MCSPI) controllers
  • 6× Fast Serial Interface Receiver (FSI_RX) cores
  • 2× Fast Serial Interface Transmitter (FSI_TX) cores
  • 3× General-Purpose I/O (GPIO) modules

Control interfaces:

  • 9x Enhanced Pulse-Width Modulator (EPWM) modules
  • 3× Enhanced Capture (ECAP) modules
  • 3× Enhanced Quadrature Encoder Pulse (EQEP) modules
  • 2× Modular Controller Area Network (MCAN) modules with or without full CAN-FD support

Media and data storage:

  • 2× Multi-Media Card/Secure Digital (MMC/SD/SDIO) interfaces
    • One 4-bit for SD/SDIO;
    • One 8-bit for eMMC
    • Integrated analog switch for voltage switching between 3.3V to 1.8V for high-speed cards

Power management:

  • Simplified power sequence
  • Integrated SDIO LDO for handling automatic voltage transition for SD interface
  • Integrated voltage supervisor for safety monitoring of over-under voltage conditions
  • Integrated power supply glitch detector for detecting fast supply transients

Functional Safety:

  • Functional Safety-Compliant targeted
    • Developed for functional safety applications
    • Documentation will be available to aid IEC 61508 functional safety system design
    • Systematic capability up to SIL 3
    • Hardware integrity up to SIL 2 targeted for MCU domain
    • Quality-Managed Main Domain
    • Safety-related certification
      • IEC 61508 certification planned
    • ECC or parity on calculation-critical memories
    • ECC and parity on select internal bus interconnect
    • Built-In Self-Test (BIST) for CPU and on-chip RAM
    • Error Signaling Module (ESM) with error pin
    • Runtime safety diagnostics, voltage, temperature, and clock monitoring, windowed watchdog timers, CRC engine for memory integrity checks
    • Dedicated MCU domain memory, interfaces, and M4F core capable of being isolated from the larger SoC with Freedom From Interference (FFI) features
      • Separate interconnect
      • Firewalls and timeout gaskets
      • Dedicated PLL
      • Dedicated I/O supply
      • Separate reset

SoC architecture:

  • Supports primary boot from UART, I2C, OSPI/QSPI Flash, SPI Flash, parallel NOR Flash, parallel NAND Flash, SD, eMMC, USB 2.0, PCIe, and Ethernet interfaces
  • 16-nm FinFET technology
  • 17.2 mm × 17.2 mm, 0.8-mm pitch, 441-pin BGA package