SLAS986D November 2014 – February 2018 AMC7836
Each DAC can be set to a CLEAR state using either hardware or software. When a DAC goes to CLEAR state, it is loaded with a zero-code input and the output voltage is set according to the auto-range detector output range. The DAC buffer or active registers do not change when the DACs enter the CLEAR state which makes it possible to return to the same voltage output before the clear event was issued. Even though the contents of the active register do not change while a DAC is in CLEAR state, a data-register read operation from the active registers while in this state returns zero-code. This functionality enables the ability to determine the DAC output voltage regardless of the operating state (CLEAR or NORMAL).
The DAC buffer and active registers can be updated while the DACs are in CLEAR state allowing the DACs to output new values upon return to normal operation. When the DACs exit the CLEAR state, the DACs are immediately loaded with the data in the DAC active registers and the output is set back to the corresponding level to restore operation.
The DAC clear registers (address 0xB0 through 0xB1) enable independent control of each DAC CLEAR state through software. The DACs can also be forced to enter a CLEAR state through hardware using the ALARMIN pin. See the Programmable Out-of-Range Alarms section for a detailed description of this method.
The ALARMIN-controlled clear mechanism is just a special case of the device capability to force the DACs into the CLEAR state as a response to an alarm event. To enable this function, the alarm events must first be enabled as DAC-clear alarm sources in the DAC clear source registers (address 0x1A through 0x1B). The DAC outputs to be cleared by the selected alarm events must also be specified in the DAC clear enable registers (address 0x18 through 0x19).
An alarm event sets the corresponding alarm bit in the alarm status registers. In addition all the DACs set to clear in response to the alarm event in the DAC clear enable registers enter a CLEAR state. Once the alarm bit is cleared, as long as no other CLEAR-state controlling alarm events have been triggered, the DACs are reloaded with the contents of the DAC active registers and the outputs update accordingly.