SLAS986D November 2014 – February 2018 AMC7836
The preferred (not required) pin order for applying power is IOVDD, DVDD and AVDD, AVCC and lastly AVEE, AVSSB, AVSSC, and AVSSD.When power sequencing, ensure that all digital pins are not powered or in an active state while the IOVDD pin ramps. Proper sequencing of the digital pins can be accomplished by attaching 10-kΩ pullup resistors to the IOVDD pin, or pulldown resistors to the DGND pin. See the supply voltage ranges in the Recommended Operating Conditions table.
In applications where a negative voltage is applied to AVEE, AVSSB, AVSSC, and AVSSD first, the user may notice some small negative voltages at other supply pins, such as the AVDD, DVDD, and AVCC pins. The negative voltages at the supply pins may exceed the values listed in the Absolute Maximum Ratings table, but because these voltages are created from intrinsic circuitry, the voltage levels are safe for operation.
Although these negative voltages are observed on the pins, the user must still adhere to the guidelines specified in the Absolute Maximum Ratings table and verify that the inputs are driven within the range specified in the table. The user should also ensure that current is only applied when operating with voltages between the ranges listed in the Absolute Maximum Ratings table.
In applications where the DAC channels are driving a large capacitive load and the output changes significantly (a full scale transition, for instance), the output current of the affected channels may drive to the short circuit current value as described in the specification table (see Table 64) while the capacitive load is being charged. This temporary increase in output current may inadvertently cause the AVCC or AVSS to collapse, potentially resulting in a POR event. It is recommended that the power supply solution for AVCC and AVSS be capable of supplying short circuit current for all DAC channels with capacitive loads simultaneously to ensure proper device performance.