SPRSP09B December 2017 – January 2019 AMIC120
Refer to the PDF data sheet for device specific package drawings
TI only supports board designs using DDR3 memory that follow the guidelines in this document. The switching characteristics and timing diagram for the DDR3 memory interface are shown in Table 5-47 and Figure 5-48.
|Cycle time, DDR_CK and DDR_CKn||2.5||3.3(1)||ns|