SPRSP09B December 2017 – January 2019 AMIC120
Refer to the PDF data sheet for device specific package drawings
The DDR3 interface schematic varies, depending upon the width of the DDR3 devices used.
Figure 5-49 shows the schematic connections for 16-bit interface using one x16 DDR3 device. Figure 5-50 shows the schematic connections for 16-bit interface without using VTT termination for the ADDR_CTRL net class signals. Figure 5-51 shows the schematic connections for 16-bit interface using two x8 DDR3 devices.
When not using all or part of a DDR3 interface, the proper method of handling the unused pins is to tie off the DDR_DQS[x] pins to the VDDS_DDR supply via a 1-kΩ resistor and pulling the DDR_DQSn[x] pins to ground via a 1k-Ω resistor. This must be done for each byte not used. Although these signals have internal pullup and pulldown, external pullup and pulldown provide additional protection against external electrical noise causing activity on the signals. Also, include the 49.9-Ω pulldown for DDR_VTP. The VDDS_DDR and DDR_VREF power supply terminals need to be connected to their respective power supplies even if the DDR3 interface is not being used. All other DDR3 interface pins can be left unconnected. The supported modes for use of the DDR3 EMIF are 32 bits wide, 16 bits wide, or not used.
The device can only source one load connected to the DQS[x] and DQ[x] net class signals and up to four loads connected to the CK and ADDR_CTRL net class signals. For more information related to net classes, see Section 220.127.116.11.1.3.8.