SLUS892D December   2009  – December 2019 BQ24610 , BQ24617


  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Simplified Schematic
  4. Revision History
  5. Description (continued)
  6. Device Comparison Table
  7. Pin Configuration and Functions
    1.     Pin Functions
  8. Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Typical Characteristics
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Battery Voltage Regulation
      2. 9.3.2  Battery Current Regulation
      3. 9.3.3  Input Adapter Current Regulation
      4. 9.3.4  Precharge
      5. 9.3.5  Charge Termination, Recharge, and Safety Timer
      6. 9.3.6  Power Up
      7. 9.3.7  Enable and Disable Charging
      8. 9.3.8  System Power Selector
      9. 9.3.9  Automatic Internal Soft-Start Charger Current
      10. 9.3.10 Converter Operation
      11. 9.3.11 Synchronous and Nonsynchronous Operation
      12. 9.3.12 Cycle-by-Cycle Charge Undercurrent Protection
      13. 9.3.13 Input Overvoltage Protection (ACOV)
      14. 9.3.14 Input Undervoltage Lockout (UVLO)
      15. 9.3.15 Battery Overvoltage Protection
      16. 9.3.16 Cycle-by-Cycle Charge Overcurrent Protection
      17. 9.3.17 Thermal Shutdown Protection
      18. 9.3.18 Temperature Qualification
      19. 9.3.19 Timer Fault Recovery
      20. 9.3.20 PG Output
      21. 9.3.21 CE (Charge Enable)
      22. 9.3.22 Charge Status Outputs
      23. 9.3.23 Battery Detection
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 System with Power Path
        1. Design Requirements
        2. Detailed Design Procedure
          1. Inductor Selection
          2. Input Capacitor
          3. Output Capacitor
          4. Power MOSFETs Selection
          5. Input Filter Design
          6. Inductor, Capacitor, and Sense Resistor Selection Guidelines
        3. Application Curves
      2. 10.2.2 Simplified System without Power Path or DPM
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curves
      3. 10.2.3 Lead-Acid Charging System
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Related Links
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Support Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Layout Guidelines

The switching node rise and fall times should be minimized for minimum switching loss. Proper layout of the components to minimize high-frequency current-path loop (see Figure 26) is important to prevent electrical and magnetic field radiation and high-frequency resonant problems. Here is a PCB layout priority list for proper layout. Layout of the PCB according to this specific order is essential.

  1. Place the input capacitor as close as possible to switching MOSFET supply and ground connections and use the shortest possible copper trace connection. These parts should be placed on the same layer of the PCB instead of on different layers and using vias to make this connection.
  2. The IC should be placed close to the switching MOSFET gate terminals to keep the gate-drive signal traces short for a clean MOSFET drive. The IC can be placed on the other side of the PCB from the switching MOSFETs.
  3. Place the inductor input terminal as close as possible to the switching MOSFET output terminal. Minimize the copper area of this trace to lower electrical and magnetic field radiation, but make the trace wide enough to carry the charging current. Do not use multiple layers in parallel for this connection. Minimize parasitic capacitance from this area to any other trace or plane.
  4. The charging-current sensing resistor should be placed right next to the inductor output. Route the sense leads connected across the sensing resistor back to the IC in same layer, close to each other (minimize loop area) and do not route the sense leads through a high-current path (see Figure 27 for Kelvin connection for best current accuracy). Place the decoupling capacitor on these traces next to the IC.
  5. Place the output capacitor next to the sensing resistor output and ground.
  6. Output capacitor ground connections must be tied to the same copper that connects to the input capacitor ground before connecting to system ground.
  7. Route the analog ground separately from the power ground and use a single ground connection to tie the charger power ground to the charger analog ground. Just beneath the IC, use the copper-pour for analog ground, but avoid power pins to reduce inductive and capacitive noise coupling. Connect analog ground to GND. Connect analog ground and power ground together using the thermal pad as the single ground connection point. Or use a 0-Ω resistor to tie analog ground to power ground (thermal pad should tie to analog ground in this case). A star connection under the thermal pad is highly recommended.
  8. It is critical to solder the exposed thermal pad on the back side of the IC package to the PCB ground. Ensure that there are sufficient thermal vias directly under the IC, connecting to the ground plane on the other layers.
  9. Place decoupling capacitors next to the IC pins and make trace connection as short as possible.
  10. Size and number of all vias must be enough for a given current path.

See the bq2461x/bq2463x (HPA422A) Multi-Cell Synchronous Switch-Mode Charger EVM design for the recommended component placement with trace and via locations.

For the QFN information, see Quad Flatpack No-Lead Logic Packages Application Report and QFN and SON PCB Attachment Application Report.