SLUSDU3 May   2021 BQ25720

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Power-Up Sequence
      2. 9.3.2  Vmin Active Protection (VAP) with Battery only
      3. 9.3.3  Two-Level Battery Discharge Current Limit
      4. 9.3.4  Fast Role Swap Feature
      5. 9.3.5  CHRG_OK Indicator
      6. 9.3.6  Input and Charge Current Sensing
      7. 9.3.7  Input Voltage and Current Limit Setup
      8. 9.3.8  Battery Cell Configuration
      9. 9.3.9  Device HIZ State
      10. 9.3.10 USB On-The-Go (OTG)
      11. 9.3.11 Converter Operation
      12. 9.3.12 Inductance Detection Through IADPT Pin
      13. 9.3.13 Converter Compensation
      14. 9.3.14 Continuous Conduction Mode (CCM)
      15. 9.3.15 Pulse Frequency Modulation (PFM)
      16. 9.3.16 Switching Frequency and Dithering Feature
      17. 9.3.17 Current and Power Monitor
        1. 9.3.17.1 High-Accuracy Current Sense Amplifier (IADPT and IBAT)
        2. 9.3.17.2 High-Accuracy Power Sense Amplifier (PSYS)
      18. 9.3.18 Input Source Dynamic Power Management
      19. 9.3.19 Input Current Optimizer (ICO)
      20. 9.3.20 Two-Level Adapter Current Limit (Peak Power Mode)
      21. 9.3.21 Processor Hot Indication
        1. 9.3.21.1 PROCHOT During Low Power Mode
        2. 9.3.21.2 PROCHOT Status
      22. 9.3.22 Device Protection
        1. 9.3.22.1 Watchdog Timer
        2. 9.3.22.2 Input Overvoltage Protection (ACOV)
        3. 9.3.22.3 Input Overcurrent Protection (ACOC)
        4. 9.3.22.4 System Overvoltage Protection (SYSOVP)
        5. 9.3.22.5 Battery Overvoltage Protection (BATOVP)
        6. 9.3.22.6 Battery Discharge Overcurrent Protection (BATOC)
        7. 9.3.22.7 Battery Short Protection (BATSP)
        8. 9.3.22.8 System Undervoltage Lockout (VSYS_UVP) and Hiccup Mode
        9. 9.3.22.9 Thermal Shutdown (TSHUT)
    4. 9.4 Device Functional Modes
      1. 9.4.1 Forward Mode
        1. 9.4.1.1 System Voltage Regulation with Narrow VDC Architecture
        2. 9.4.1.2 Battery Charging
      2. 9.4.2 USB On-The-Go
      3. 9.4.3 Pass Through Mode (PTM)-Patented Technology
    5. 9.5 Programming
      1. 9.5.1 SMBus Interface
        1. 9.5.1.1 SMBus Write-Word and Read-Word Protocols
        2. 9.5.1.2 Timing Diagrams
    6. 9.6 Register Map
      1. 9.6.1  ChargeOption0 Register (SMBus address = 12h) [reset = E70Eh]
      2. 9.6.2  ChargeCurrent Register (SMBus address = 14h) [reset = 0000h]
        1. 9.6.2.1 Battery Pre-Charge Current Clamp
      3. 9.6.3  ChargeVoltage Register (SMBus address = 15h) [reset value based on CELL_BATPRESZ pin setting]
      4. 9.6.4  ChargerStatus Register (SMBus address = 20h) [reset = 0000h]
      5. 9.6.5  ProchotStatus Register (SMBus address = 21h) [reset = B800h]
      6. 9.6.6  IIN_DPM Register With 10-mΩ Sense Resistor (SMBus address = 22h) [reset = 4100h]
      7. 9.6.7  ADCVBUS/PSYS Register (SMBus address = 23h)
      8. 9.6.8  ADCIBAT Register (SMBus address = 24h)
      9. 9.6.9  ADCIINCMPIN Register (SMBus address = 25h)
      10. 9.6.10 ADCVSYSVBAT Register (SMBus address = 26h)
      11. 9.6.11 ChargeOption1 Register (SMBus address = 30h) [reset = 3300h]
      12. 9.6.12 ChargeOption2 Register (SMBus address = 31h) [reset = 00B7]
      13. 9.6.13 ChargeOption3 Register (SMBus address = 32h) [reset = 0434h]
      14. 9.6.14 ProchotOption0 Register (SMBus address = 33h) [reset = 4A81h(2S~) 4A09(1S)]
      15. 9.6.15 ProchotOption1 Register (SMBus address = 34h) [reset = 41A0h]
      16. 9.6.16 ADCOption Register (SMBus address = 35h) [reset = 2000h]
      17. 9.6.17 ChargeOption4 Register (SMBus address = 36h) [reset = 0048h]
      18. 9.6.18 Vmin Active Protection Register (SMBus address = 37h) [reset = 006Ch(2s~4s)/0004h(1s)]
      19. 9.6.19 OTGVoltage Register (SMBus address = 3Bh) [reset = 09C4h]
      20. 9.6.20 OTGCurrent Register (SMBus address = 3Ch) [reset = 3C00h]
      21. 9.6.21 InputVoltage (VINDPM) Register (SMBus address = 3Dh) [reset = VBUS-1.28V]
      22. 9.6.22 VSYS_MIN Register (SMBus address = 3Eh) [reset value based on CELL_BATPRESZ pin setting]
      23. 9.6.23 IIN_HOST Register (SMBus address = 3Fh) [reset = 4100h]
      24. 9.6.24 ID Registers
        1. 9.6.24.1 ManufactureID Register (SMBus address = FEh) [reset = 0040h]
        2. 9.6.24.2 Device ID (DeviceAddress) Register (SMBus address = FFh) [reset = 00E1h]
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 ACP-ACN Input Filter
        2. 10.2.2.2 Inductor Selection
        3. 10.2.2.3 Input Capacitor
        4. 10.2.2.4 Output Capacitor
        5. 10.2.2.5 Power MOSFETs Selection
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
      1. 12.2.1 Layout Example Reference Top View
      2. 12.2.2 Inner Layer Layout and Routing Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Support Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.6.4 ChargerStatus Register (SMBus address = 20h) [reset = 0000h]

Figure 9-11 ChargerStatus Register (SMBus address = 20h) [reset = 0000h]
15141312111098
STAT_ACICO_DONEIN_VAPIN_VINDPMIN_IIN_DPMIN_FCHRGIN_PCHRGIN_OTG
RRRRRRRR
76543210
Fault ACOVFault BATOCFault ACOCFAULT SYSOVP
Fault VSYS
_UVP		Fault Force_Converter_OffFault_OTG
_OVP		Fault_OTG
_UVP
RRRR/WR/WRRR
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9-16 ChargerStatus Register (SMBus address = 20h) Field Descriptions
SMBus
BIT		FIELDTYPERESETDESCRIPTION
15STAT_ACR0b

Input source status. STAT_AC is valid as long as VBUS go within 3.5V ~26V range. It is different from CHRG_OK bit, When CHRG_OK is valid, STAT_AC must be valid, but if STAT_AC is valid, it is not necessary CHRG_OK is valid. There are Force converter off, ACOC, TSHUT , SYSOVP, VSYS_UVP, BATOVP can pull low CHRG_OK.

0b: Input not present

1b: Input is present

14ICO_DONER0b

After the ICO routine is successfully executed, the bit goes 1.

0b: ICO is not complete

1b: ICO is complete

13IN_VAPR0b

0b: Charger is not operated in VAP mode

1b: Charger is operated in VAP mode

Digital status bit indicates VAP has enabled(1) or disabled(0). The enable of VAP mode only follows the host command, which is not blocked by any status of /PROCHOT. The exit of VAP mode also follows the host command, except that any faults will exit VAP mode automatically. STAT_EXIT_VAP (REG0x21[8]) becomes 1 which will pull low /PROCHOT until host clear.

The host can enable VAP by setting OTG/VAP/FRS pin high and 0x32[5]=0, disable VAP by setting either OTG/VAP/FRS pin low or 0x32[5]=1. Any faults in VAP When IN_VAP bit goes 0->1, charger should disable VINDPM, IIN_DPM, ICRIT, ILIM pin, disable PP_ACOK if it is enabled, enable PP_VSYS if it is disabled. When IN_VAP bit goes 1->0, charger should enable VINDPM, IIN_DPM, ICRIT, ILIM pin function.

12IN_VINDPMR0b

0b: Charger is not in VINDPM during forward mode, or voltage regulation during OTG mode

1b: Charger is in VINDPM during forward mode, or voltage regulation during OTG mode

11IN_IIN_DPMR0b

0b: Charger is not in IIN_DPM during forward mode.

1b: Charger is not in IIN_DPM during forward mode.

10IN_FCHRGR0b

0b: Charger is not in fast charge

1b: Charger is in fast charger

9IN_PCHRGR0b

0b: Charger is not in pre-charge

1b: Charger is in pre-charge

8IN_OTGR0b

0b: Charger is not in OTG

1b: Charge is in OTG

Table 9-17 ChargerStatus Register (SMBus address = 20h) Field Descriptions
SMBus
BIT		FIELDTYPERESETDESCRIPTION
7Fault ACOVR0b

The status are latched if triggered until a read from host.

0b: No fault

1b: ACOV

6Fault BATOCR0b

The status is latched if triggered until a read from host. Fault indicator for BATOC only during normal operation. However in PTM mode when EN_BATOC=1b, this status bit is fault indicator for both BATOVP and BATOC; when EN_BATOC=0b, this status bit is not effective.

0b: No fault

1b: BATOC is triggered

5Fault ACOCR0b

The status is latched if triggered until a read from host.

0b: No fault

1b: ACOC

4Fault SYSOVPR/W0b

SYSOVP Status and Clear. SYSOVP fault is latched until a clear from host by writing this bit to 0.

When the SYSOVP occurs, this bit is HIGH. During the SYSOVP, the converter is disabled.

After the SYSOVP is removed, the user must write a 0 to this bit or unplug the adapter to clear the SYSOVP condition to enable the converter again.

0b: Not in SYSOVP <default at POR>

1b: In SYSOVP. When SYSOVP is removed, write 0 to clear the SYSOVP latch.

3Fault VSYS_UVPR/W0b

VSYS_UVP fault status and clear. VSYS_UVP fault is latched until a clear from host by writing this bit to 0.

0b: No fault <default at POR>

1b: When system voltage is lower than VSYS_UVP, then 7 times restart tries are failed.

2Fault Force_Converter_OffR0b

The status is latched if triggered until a read from host.

0b: No fault

1b: Force converter off triggered (when FORCE_CONV_OFF (REG0x30[3]=1b)

1Fault_OTG_OVPR0b

The status is latched if triggered until a read from host.

0b: No fault

1b: OTG OVP fault is triggered

0Fault_OTG_UVPR0b

The status is latched if triggered until a read from host.

0b: No fault

1b: OTG UVP fault is triggered