SLUSE66A June   2020  – January 2021 BQ25731

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics(BQ25731)
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Power-Up Sequence
      2. 9.3.2  Two-Level Battery Discharge Current Limit
      3. 9.3.3  Fast Role Swap Feature
      4. 9.3.4  CHRG_OK Indicator
      5. 9.3.5  Input and Charge Current Sensing
      6. 9.3.6  Input Voltage and Current Limit Setup
      7. 9.3.7  Battery Cell Configuration
      8. 9.3.8  Device HIZ State
      9. 9.3.9  USB On-The-Go (OTG)
      10. 9.3.10 Converter Operation
      11. 9.3.11 Inductance Detection Through IADPT Pin
      12. 9.3.12 Converter Compensation
      13. 9.3.13 Continuous Conduction Mode (CCM)
      14. 9.3.14 Pulse Frequency Modulation (PFM)
      15. 9.3.15 Switching Frequency and Dithering Feature
      16. 9.3.16 Current and Power Monitor
        1. 9.3.16.1 High-Accuracy Current Sense Amplifier (IADPT and IBAT)
        2. 9.3.16.2 High-Accuracy Power Sense Amplifier (PSYS)
      17. 9.3.17 Input Source Dynamic Power Management
      18. 9.3.18 Input Current Optimizer (ICO)
      19. 9.3.19 Two-Level Adapter Current Limit (Peak Power Mode)
      20. 9.3.20 Processor Hot Indication
        1. 9.3.20.1 PROCHOT During Low Power Mode
        2. 9.3.20.2 PROCHOT Status
      21. 9.3.21 Device Protection
        1. 9.3.21.1 Watchdog Timer
        2. 9.3.21.2 Input Overvoltage Protection (ACOV)
        3. 9.3.21.3 Input Overcurrent Protection (ACOC)
        4. 9.3.21.4 System Overvoltage Protection (SYSOVP)
        5. 9.3.21.5 Battery Overvoltage Protection (BATOVP)
        6. 9.3.21.6 Battery Discharge Overcurrent Protection (BATOC)
        7. 9.3.21.7 Battery Short Protection (BATSP)
        8. 9.3.21.8 System Undervoltage Lockout (VSYS_UVP)
        9. 9.3.21.9 Thermal Shutdown (TSHUT)
    4. 9.4 Device Functional Modes
      1. 9.4.1 Forward Mode
      2. 9.4.2 USB On-The-Go
      3. 9.4.3 Pass Through Mode (PTM)-Patented Technology
    5. 9.5 Programming
      1. 9.5.1 I2C Serial Interface
        1. 9.5.1.1 Timing Diagrams
        2. 9.5.1.2 Data Validity
        3. 9.5.1.3 START and STOP Conditions
        4. 9.5.1.4 Byte Format
        5. 9.5.1.5 Acknowledge (ACK) and Not Acknowledge (NACK)
        6. 9.5.1.6 Target Address and Data Direction Bit
        7. 9.5.1.7 Single Read and Write
        8. 9.5.1.8 Multi-Read and Multi-Write
        9. 9.5.1.9 Write 2-Byte I2C Commands
    6. 9.6 Register Map
      1. 9.6.1  ChargeOption0 Register (I2C address = 01/00h) [reset = E70Eh]
      2. 9.6.2  ChargeCurrent Register (I2C address = 03/02h) [reset = 0080h]
        1. 9.6.2.1 Battery Low Voltage Current Clamp
      3. 9.6.3  ChargeVoltage Register (I2C address = 05/04h) [reset value based on CELL_BATPRESZ pin setting]
      4. 9.6.4  ChargerStatus Register (I2C address = 21/20h) [reset = 0000h]
      5. 9.6.5  ProchotStatus Register (I2C address = 23/22h) [reset = B800h]
      6. 9.6.6  IIN_DPM Register (I2C address = 25/24h) [reset = 4100h]
      7. 9.6.7  ADCVBUS/PSYS Register (I2C address = 27/26h)
      8. 9.6.8  ADCIBAT Register (I2C address = 29/28h)
      9. 9.6.9  ADCIIN/CMPIN Register (I2C address = 2B/2Ah)
      10. 9.6.10 ADCVSYS/VBAT Register (I2C address = 2D/2Ch)
      11. 9.6.11 ChargeOption1 Register (I2C address = 31/30h) [reset = 3F00h]
      12. 9.6.12 ChargeOption2 Register (I2C address = 33/32h) [reset = 00B7]
      13. 9.6.13 ChargeOption3 Register (I2C address = 35/34h) [reset = 0434h]
      14. 9.6.14 ProchotOption0 Register (I2C address = 37/36h) [reset = 4A81h(2S~5s) 4A09(1S)]
      15. 9.6.15 ProchotOption1 Register (I2C address = 39/38h) [reset = 41A0h]
      16. 9.6.16 ADCOption Register (I2C address = 3B/3Ah) [reset = 2000h]
      17. 9.6.17 ChargeOption4 Register (I2C address = 3D/3Ch) [reset = 0048h]
      18. 9.6.18 Vmin Active Protection Register (I2C address = 3F/3Eh) [reset = 006Ch(2s~5s)/0004h(1S)]
      19. 9.6.19 OTGVoltage Register (I2C address = 07/06h) [reset = 09C4h]
      20. 9.6.20 OTGCurrent Register (I2C address = 09/08h) [reset = 3C00h]
      21. 9.6.21 InputVoltage(VINDPM) Register (I2C address = 0B/0Ah) [reset =VBUS-1.28V]
      22. 9.6.22 IIN_HOST Register (I2C address = 0F/0Eh) [reset = 2000h]
      23. 9.6.23 ID Registers
        1. 9.6.23.1 ManufactureID Register (I2C address = 2Eh) [reset = 40h]
        2. 9.6.23.2 Device ID (DeviceAddress) Register (I2C address = 2Fh) [reset = D6h]
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Input Snubber and Filter for Voltage Spike Damping
        2. 10.2.2.2 ACP-ACN Input Filter
        3. 10.2.2.3 Inductor Selection
        4. 10.2.2.4 Input Capacitor
        5. 10.2.2.5 Output Capacitor
        6. 10.2.2.6 Power MOSFETs Selection
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
      1. 12.2.1 Layout Example Reference Top View
      2. 12.2.2 Inner Layer Layout and Routing Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Support Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.6.11 ChargeOption1 Register (I2C address = 31/30h) [reset = 3F00h]

Figure 9-26 ChargeOption1 Register (I2C address = 31/30h) [reset = 3300h]
7 6 5 4 3 2 1 0
EN_IBATEN_PROCHOT_LPWRPSYS_CONFIGRSNS_RACRSNS_RSRPSYS_RATIOEN_FAST_5MOHM
R/WR/WR/WR/WR/WR/WR/W
76543210
CMP_REFCMP_POLCMP_DEGFORCE_CONV_OFFEN_PTMEN_SHIP_DCHGAUTO_WAKEUP_EN
R/WR/WR/WR/WR/WR/WR/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9-28 ChargeOption1 Register (I2C address = 31h) Field Descriptions
BITFIELDTYPERESETDESCRIPTION
7EN_IBATR/W0b

IBAT Enable

Enable the IBAT output buffer. In low power mode (EN_LWPWR=1b), IBAT buffer is always disabled regardless of this bit value.

0b Turn off IBAT buffer to minimize Iq <default at POR>

1b: Turn on IBAT buffer

6EN_PROCHOT_LPWRR/W0b

Enable PROCHOT during battery only low power mode

With battery only, enable VSYS in PROCHOT with low power consumption. Do not enable this function with adapter present. Refer to Section 9.3.20.1 for more details.

0b: Disable Independent Comparator low power PROCHOT <default at POR>

1b: Enable Independent Comparator low power PROCHOT

5-4PSYS_CONFIGR/W11b

PSYS Enable and Definition Register

Enable PSYS sensing circuit and output buffer (whole PSYS circuit). In low power mode (EN_LWPWR=1b), PSYS sensing and buffer are always disabled regardless of this bit value.

00b: PSYS=PBUS+PBAT

01b: PSYS=PBUS

10b: Reserved

11b: Turn off PSYS buffer to minimize Iq<default at POR>

3RSNS_RACR/W1b

Input sense resistor RAC

0b: 10 mΩ

1b: 5 mΩ <default at POR>

2RSNS_RSRR/W1b

Charge sense resistor RSR

0b: 10 mΩ

1b: 5 mΩ <default at POR>

1PSYS_RATIOR/W1b

PSYS Gain

Ratio of PSYS output current vs total system power

0b: 0.25 µA/W

1b: 1 µA/W <default at POR>

0 EN_FAST_5MOHM R/W 1b

Enable fast compensation to increase bandwidth under 5 mΩ RAC (RSNS_RAC=1b) for input current up to 6.4-A application (the fast compensation will only work when IADPT pin is configured less than 160 kΩ)

0b: Turn off bandwidth promotion under RSNS_RAC=1b

(Note when this bit configured as 0b, IIN_HOST DAC can be extended up to 10 A, writing IIN_HOST value higher than 10 A will be neglected, the ICHG regulation loop will be slower to guarantee stability under 6.4-A to 10-A input current range)

1b: Turn on bandwidth promotion under RSNS_RAC=1b <default at POR>

(Note when this bit configured as 1b, IIN_HOST DAC is clamped at 6.4 A, writing IIN_HOST value higher than 6.4 A will be neglected, the ICHG regulation loop will be faster within 6.4-A input current range)
Table 9-29 ChargeOption1 Register (I2C address = 30h) Field Descriptions
BITFIELDTYPERESETDESCRIPTION
7CMP_REFR/W0b

Independent Comparator internal Reference

0b: 2.3 V <default at POR>

1b: 1.2 V

6CMP_POLR/W0b

Independent Comparator output Polarity

0b: When CMPIN is above internal threshold, CMPOUT is LOW (internal hysteresis) <default at POR>

1b: When CMPIN is below internal threshold, CMPOUT is LOW (external hysteresis)

5-4CMP_DEGR/W00b

Independent comparator deglitch time, only applied to the falling edge of CMPOUT (HIGH → LOW).

00b: Independent comparator is enabled with output deglitch time 5 µs <default at POR>

01b: Independent comparator is enabled with output deglitch time of 2 ms

10b: Independent comparator is enabled with output deglitch time of 20 ms

11b: Independent comparator is enabled with output deglitch time of 5 sec

3FORCE_CONV_OFFR/W0b

Force Converter Off function

When independent comparator triggers, (CMPOUT pin pulled down) converter latches off, at the same time, CHRG_OK signal goes LOW to notify the system. Charge current is also set to zero internally, but charge current register setting keeps the same. To get out of converter latches off, firstly the CMPOUT should be released to high and secondly FORCE_CONV_OFF bit should be cleared (=0b).

0b: Disable this function <default at POR>

1b: Enable this function

2EN_PTMR/W0b

PTM enable register bit, it will automatically reset to zero

0b: disable PTM. <default at POR>

1b: enable PTM.

1EN_SHIP_DCHGR/W0b

Discharge SRN for Shipping Mode. Used to discharge VBAT pin capacitor voltage which is necessary for battery gauge device shipping mode.

When this bit is 1, discharge SRN pin down in 140 ms 20 mA. When 140 ms is over, this bit is reset to 0b automatically. If this bit is written to 0b by host before 140 ms expires, VSYS should stop discharging immediately. Note if after 140-ms SRN voltage is still not low enough for battery gauge device entering ship mode, the host may need to start a new 140-ms discharge cycle.

0b: Disable shipping mode <default at POR>

1b: Enable shipping mode

0AUTO_WAKEUP_ENR/W0b

Auto Wakeup Enable

When this bit is HIGH, if the battery is below VSYS_MIN , the device should automatically enable 128-mA charging current for 30 mins. When the battery is charged up above minimum system voltage, charge will terminate and the bit is reset to LOW. The charger will also exit auto wake up if host write a new charge current value to charge current register Reg0x14().

0b: Disable <default at POR>

1b: Enable