SLVSDU0B September 2017 – September 2019 BQ25910
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
REG05 is shown in Figure 36 and described in Table 10.
Return to Summary Table.
When the WATCHDOG[1:0] bits change (writing the same value does not change these bits), the internal counter is reset. The same applies for the CHG_TIMER bits (changing the value in the register will reset the CHG_TIMER).
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EN_TERM | WD_RST | WATCHDOG[1:0] | EN_TIMER | CHG_TIMER[1:0] | TMR2X_EN | ||
R/W-1h | R/W-0h | R/W-1h | R/W-1h | R/W-2h | R/W-1h |
Bit | Field | Type | Reset by REG_RST | Reset by WATCHDOG | Description |
---|---|---|---|---|---|
7 | EN_TERM | R/W | Yes | Yes |
Termination control 0h = Disable termination 1h = Enable termination |
6 | WD_RST | R/W | Yes | Yes |
I2C watchdog-timer reset 0h = Normal 1h = Reset (bit returns to 0 after time reset) |
5-4 | WATCHDOG[1:0] | R/W | Yes | Yes |
I2C watchdog-timer settings 0h = Disable watchdog timer 1h = 40 s 2h = 80 s 3h = 160 s |
3 | EN_TIMER | R/W | Yes | Yes |
Charging safety-timer enable 0h = Disable 1h = Enable |
2-1 | CHG_TIMER[1:0] | R/W | Yes | Yes |
Fast-charge safety timer setting 0h = 5 hours 1h = 8 hours 2h = 12 hours 3h = 20 hours |
0 | TMR2X_EN | R/W | Yes | Yes |
Safety timer behavior during DPM or TREG 0h = Safety timer always counts normally 1h = Safety timer count slowed by 2x during input DPM or TREG |