SLUSC16B November   2015  – March 2019

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Charge Pump Control
      2. 7.3.2 Pin Enable Controls
        1. 7.3.2.1 External Control of CHG and DSG Output Drivers
        2. 7.3.2.2 External Control of PCHG Output Driver
        3. 7.3.2.3 Pack Monitor Enable
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Recommended System Implementation
        1. 8.1.1.1 bq76200 Slave Device
        2. 8.1.1.2 Flexible Control via AFE or via MCU
        3. 8.1.1.3 Scalable VDDCP Capacitor to Support Multiple FETs in Parallel
        4. 8.1.1.4 Precharge and Predischarge Support
        5. 8.1.1.5 Optional External Gate Resistor
        6. 8.1.1.6 Separate Charge and Discharge paths
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.1 Charge Pump Control

The bq76200 device has an integrated charge pump. A minimum of 470-nF capacitor is required on the V(VDDCP) pin to the BAT pin to ensure proper function of the charge pump. If the V(VDDCP) capacitor is disconnected, a residual voltage could reside at the CHG and/or DSG output if CHG_EN and/or DSG_EN are enabled. Such a fault condition can put the external FETs in high Rdson state and result in FET damage.

The V(VDDCP) capacitor can be scaled up to support more FETs in parallel (such as high-total FET-gate capacitance) than the value specified in the electrical characteristics table. A higher VDDCP capacitance results in longer tCPON time. See the Application Information section for more information. Note that probing the VDDCP pin may increase the loading on the charge pump and result in lower measurement value than the V(VDDCP) specification. Using higher impedance probe can reduce such effect on the measurement.

The charge pump is controlled by CP_EN and also OR'ed with the CHG_EN and DSG_EN inputs. This means by enabling CHG_EN or DSG_EN alone, the charge pump will automatically turn on even if the CP_EN pin is disabled. The PCHG_EN controls the PCHG pin, which is a P-channel FET driver and does not require the function of the charge pump. The charge pump is turned off by default. When CP_EN is high, the charge pump turns on regardless of the status of the CHG_EN and DSG_EN inputs.

When CP_EN is enabled, the charge pump voltage starts to ramp up. Once the voltage is above an internal UVLO level, about 9-V typical above VBAT, the charge pump is considered on. The charge pump voltage should continuously ramp to the V(VDDCP) level. If the CHG_EN and/or DSG_EN is enabled, the CHG and/or DSG voltage will starts to turn on after the charge pump voltage is above the UVLO level, and ramp up along the charge pump voltage to the V(VDDCP) level. Otherwise, the CHG and DSG do not turn on if the charge pump voltage fails to ramp up above UVLO. For example, if the C(VDDCP) is not scaled properly to support the number of FETs in parallel, the heavy loading would prevent the charge pump to ramp up above UVLO. CHG and DSG would not be turned on in this case.

When CHG_EN and/or DSG_EN is enabled after the charge pump is fully turned on, the CHG_EN-enable to CHG-on delay (or DSG_EN-enable to DSG-on delay) is simply the sum of (tprop + FET rise time). A system configuration example for this scenario will be connecting the CP_EN to the host MCU, enable CP_EN at system start-up and keep the CP_EN enabled during normal operation. This is the recommended configuration, because the charge pump ramp-up time, tCPON, becomes part of the system start-up time and does not add onto the FET switch delay during normal operation.

If CP_EN is not used (it is highly recommended to connect the CP_EN to ground), the charge pump on- and off-state is controlled by CHG_EN or DSG_EN. The CHG or DSG output will only be on after the charge-pump voltage is ramped up above UVLO. This means the CHG_EN-enable to CHG-on delay (or DSG_EN-enable to DSG-on delay) will be (tCPON + tprop + FET rise time).

The charge pump is turned off when CP_EN AND CHG_EN AND DSG_EN signals are all low. The charge pump is not actively driven low and the voltage on the V(VDDCP) capacitor bleeds off passively. If any of the CP_EN, CHG_EN, or DSG_EN signals is switched high again while the V(VDDCP) capacitor is still bleeding off its charge, the charge pump start up time, tCPON, will be shorter.