SLUSC16B November   2015  – March 2019

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Charge Pump Control
      2. 7.3.2 Pin Enable Controls
        1. 7.3.2.1 External Control of CHG and DSG Output Drivers
        2. 7.3.2.2 External Control of PCHG Output Driver
        3. 7.3.2.3 Pack Monitor Enable
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Recommended System Implementation
        1. 8.1.1.1 bq76200 Slave Device
        2. 8.1.1.2 Flexible Control via AFE or via MCU
        3. 8.1.1.3 Scalable VDDCP Capacitor to Support Multiple FETs in Parallel
        4. 8.1.1.4 Precharge and Predischarge Support
        5. 8.1.1.5 Optional External Gate Resistor
        6. 8.1.1.6 Separate Charge and Discharge paths
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

Typical values stated at TA = 25°C and V(BAT) = 48 V. MIN/MAX values stated with TA = –40°C to 85°C and V(BAT) = 8 to 75 V unless otherwise noted.
PARAMETER DESCRIPTION TEST CONDITION MIN TYP MAX UNIT
SUPPLY AND LEAKAGE CURRENT
I(BAT) NORMAL mode current(1) C(VDDCP) = 470 nF, V(BAT) = 8V
CL = 10 nF		 40 60 µA
C(VDDCP) = 470 nF, V(BAT) ≥ 48V
CL = 10 nF		 40 52 uA
Ishut Sum of current into BAT and PACK pin Shutdown Mode, PACK = 0 V, BAT = 8 V 6 9.5 µA
CHARGE PUMP
V(VDDCP) Charge pump voltage No Load, CP_EN = hi, V(VDDCP) – V(BAT) 9 14 V
tCPON Charge pump start up time from zero volt C(VDDCP) = 470 nF, 10% to 90% of V(VDDCP) 100 ms
INPUT ENABLE CONTROL SIGNALS
VIL Digital low input level for CHG_EN, DSG_EN, PCHG_EN, CP_EN, PMON_EN 0.6 V
VIH Digital high input level for CHG_EN, DSG_EN, PCHG_EN, CP_EN, PMON_EN 1.2 V
RPD Internal Pull down VIN = 5 V 0.6 1 4 MΩ
CHARGE FET DRIVER
V(CHGFETON) CHG gate drive voltage (on) CL = 10 nF, CHG_EN = Hi,  V(BAT) = V(PACK), V(CHG) – V(BAT) 9 12 14 V
R(CHGFETON) CHG FET driver on resistance V(VDDCP) – V(BAT) = 12 V, CHG_EN = Hi, V(BAT) = V(PACK) 1.1 kΩ
R(CHGFETOFF) CHG FET driver off resistance V(VDDCP) – V(BAT) = 12 V, CHG_EN = Lo, V(BAT) = V(PACK) 0.3 kΩ
DISCHARGE FET DRIVER
V(DSGFETON) DSG gate drive voltage (on) CL = 10 nF, DSG_EN = Hi, V(BAT) = V(PACK), V(DSG) – V(PACK) 9 12 14 V
R(DSGFETON) DSG FET driver on resistance V(VDDCP) – V(BAT) = 12 V, DSG_EN = Hi, V(BAT) = V(PACK) 3.5 kΩ
R(DSGFETOFF) DSG FET driver off resistance V(VDDCP) – V(BAT) = 12 V, DSG_EN = Lo, V(BAT) = V(PACK) 1 kΩ
PRECHARGE FET DRIVER
V(PCHGFETON) PCHG gate drive voltage (on) V(PACK) > 17 V, V(BAT) < V(PACK), V(PACK) – V(PCHG) 5 12 14 V
PACK MONITOR (PACK_DIV)
R(PMONFET) On resistance of internal FET (R between PACK and PACKDIV) PMON_EN = hi 1.5 2.5 3.5 kΩ
(1) NORMAL mode is defined as CHG_EN = Hi, DSG_EN = Hi, CP_EN = Hi, PCHG_EN = Lo, PMON_EN = Lo. Current value is averaged out over time.