SWRS243B February   2020  – May 2021 CC3235MODAS , CC3235MODASF , CC3235MODS , CC3235MODSF

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Functional Block Diagrams
  5. Revision History
  6. Device Comparison
    1. 6.1 Related Products
  7. Terminal Configuration and Functions
    1. 7.1 CC3235MODx and CC3235MODAx Pin Diagram
    2. 7.2 Pin Attributes and Pin Multiplexing
      1. 7.2.1 Module Pin Descriptions
    3. 7.3 Signal Descriptions
    4. 7.4 Drive Strength and Reset States for Analog-Digital Multiplexed Pins
    5. 7.5 Pad State After Application of Power to Chip, but Before Reset Release
    6. 7.6 Connections for Unused Pins
  8. Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Current Consumption (CC3235MODS and CC3235MODAS)
      1.     
      2.     
    5. 8.5  Current Consumption (CC3235MODSF and CC3235MODASF)
      1.     
      2.     
    6. 8.6  TX Power Control for 2.4 GHz Band
    7. 8.7  TX Power Control for 5 GHz
    8. 8.8  Brownout and Blackout Conditions
    9. 8.9  Electrical Characteristics for GPIO Pins
      1. 8.9.1 Electrical Characteristics for Pin Internal Pullup and Pulldown (25°C)
    10. 8.10 CC3235MODAx Antenna Characteristics
    11. 8.11 WLAN Receiver Characteristics
      1.     
      2.     
    12. 8.12 WLAN Transmitter Characteristics
      1.     
      2.     
    13. 8.13 BLE and WLAN Coexistence Requirements
    14. 8.14 Reset Requirement
    15. 8.15 Thermal Resistance Characteristics for MOB and MON Packages
    16. 8.16 Timing and Switching Characteristics
      1. 8.16.1 Power-Up Sequencing
      2. 8.16.2 Power-Down Sequencing
      3. 8.16.3 Device Reset
      4. 8.16.4 Wake Up From Hibernate Timing
      5. 8.16.5 Peripherals Timing
        1. 8.16.5.1  SPI
          1. 8.16.5.1.1 SPI Master
          2. 8.16.5.1.2 SPI Slave
        2. 8.16.5.2  I2S
          1. 8.16.5.2.1 I2S Transmit Mode
          2. 8.16.5.2.2 I2S Receive Mode
        3. 8.16.5.3  GPIOs
          1. 8.16.5.3.1 GPIO Input Transition Time Parameters
        4. 8.16.5.4  I2C
        5. 8.16.5.5  IEEE 1149.1 JTAG
        6. 8.16.5.6  ADC
        7. 8.16.5.7  Camera Parallel Port
        8. 8.16.5.8  UART
        9. 8.16.5.9  External Flash Interface
        10. 8.16.5.10 SD Host
        11. 8.16.5.11 Timers
  9. Detailed Description
    1. 9.1  Overview
    2. 9.2  Functional Block Diagram
    3. 9.3  Arm Cortex-M4 Processor Core Subsystem
    4. 9.4  Wi-Fi Network Processor Subsystem
      1. 9.4.1 WLAN
      2. 9.4.2 Network Stack
    5. 9.5  Security
    6. 9.6  FIPS 140-2 Level 1 Certification
    7. 9.7  Power-Management Subsystem
      1. 9.7.1 VBAT Wide-Voltage Connection
    8. 9.8  Low-Power Operating Mode
    9. 9.9  Memory
      1. 9.9.1 Internal Memory
        1. 9.9.1.1 SRAM
        2. 9.9.1.2 ROM
        3. 9.9.1.3 Flash Memory
        4. 9.9.1.4 Memory Map
    10. 9.10 Restoring Factory Default Configuration
    11. 9.11 Boot Modes
      1. 9.11.1 Boot Mode List
    12. 9.12 Hostless Mode
    13. 9.13 Device Certification and Qualification
      1. 9.13.1 FCC Certification and Statement
      2. 9.13.2 IC/ISED Certification and Statement
      3. 9.13.3 ETSI/CE Certification
      4. 9.13.4 MIC Certification
    14. 9.14 Module Markings
    15. 9.15 End Product Labeling
    16. 9.16 Manual Information to the End User
  10. 10Applications, Implementation, and Layout
    1. 10.1 Typical Application
      1. 10.1.1 BLE/2.4 GHz Radio Coexistence
      2. 10.1.2 Antenna Selection (CC3235MODx only)
      3. 10.1.3 Typical Application Schematic (CC3235MODx)
      4. 10.1.4 Typical Application Schematic (CC3235MODAx)
    2. 10.2 Device Connection and Layout Fundamentals
      1. 10.2.1 Power Supply Decoupling and Bulk Capacitors
      2. 10.2.2 Reset
      3. 10.2.3 Unused Pins
    3. 10.3 PCB Layout Guidelines
      1. 10.3.1 General Layout Recommendations
      2. 10.3.2 CC3235MODx RF Layout Recommendations
        1. 10.3.2.1 Antenna Placement and Routing
        2. 10.3.2.2 Transmission Line Considerations
      3. 10.3.3 CC3235MODAx RF Layout Recommendations
  11. 11Environmental Requirements and SMT Specifications
    1. 11.1 PCB Bending
    2. 11.2 Handling Environment
      1. 11.2.1 Terminals
      2. 11.2.2 Falling
    3. 11.3 Storage Condition
      1. 11.3.1 Moisture Barrier Bag Before Opened
      2. 11.3.2 Moisture Barrier Bag Open
    4. 11.4 PCB Assembly Guide
      1. 11.4.1 PCB Land Pattern & Thermal Vias
      2. 11.4.2 SMT Assembly Recommendations
      3. 11.4.3 PCB Surface Finish Requirements
      4. 11.4.4 Solder Stencil
      5. 11.4.5 Package Placement
      6. 11.4.6 Solder Joint Inspection
      7. 11.4.7 Rework and Replacement
      8. 11.4.8 Solder Joint Voiding
    5. 11.5 Baking Conditions
    6. 11.6 Soldering and Reflow Condition
  12. 12Device and Documentation Support
    1. 12.1 Development Tools and Software
    2. 12.2 Firmware Updates
    3. 12.3 Device Nomenclature
    4. 12.4 Documentation Support
    5. 12.5 Related Links
    6. 12.6 Support Resources
    7. 12.7 Trademarks
    8. 12.8 Electrostatic Discharge Caution
    9. 12.9 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Mechanical, Land, and Solder Paste Drawings
    2. 13.2 Package Option Addendum
      1. 13.2.1 Packaging Information
      2. 13.2.2 Tape and Reel Information
      3. 13.2.3 CC3235MODx Tape Specifications
      4. 13.2.4 CC3235MODAx Tape Specifications

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • MON|63
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Signal Descriptions

Table 7-2 Signal Descriptions
FUNCTIONSIGNAL NAMEPIN
NO.
PIN
TYPE
SIGNAL DIRECTIONDESCRIPTION
ADCADC_CH047I/OIADC channel 0 input (maximum of 1.5 V)
ADC_CH148I/OIADC channel 1 input (maximum of 1.5 V)
ADC_CH249I/OIADC channel 2 input (maximum of 1.5 V)
ADC_CH350IIADC channel 3 input (maximum of 1.5 V)
BLE/2.4 GHz radio coexistence(2)GPIO103I/OI/OCoexistence inputs and outputs
GPIO145I/OI/O
GPIO156I/OI/O
GPIO167I/OI/O
GPIO178I/OI/O
GPIO129I/OI/O
GPIO2211I/OI/O
GPIO2819(1)I/OI/O
GPIO044I/OI/O
GPIO3042(1)I/OI/O
GPIO550I/OI/O
GPIO651I/OI/O
GPIO853I/OI/O
GPIO954I/OI/O
Hostless modeHM_IO3I/OI/OHostless mode inputs and outputs
4I/OO
5I/OI/O
6I/OI/O
7I/OI/O
8I/OI/O
9I/OI/O
10I/OO
11I/OI/O
19(1)I/OI/O
23OO
42(1)I/OI/O
44I/OI/O
48OO
49OO
50I/OI/O
51I/OI/O
53I/OI/O
54I/OI/O
JTAG / SWDTDI12I/OIJTAG TDI. Reset default pinout.
TDO18I/OOJTAG TDO. Reset default pinout.
TCK21I/OIJTAG/SWD TCK. Reset default pinout.
TMS22I/OI/OJTAG/SWD TMS. Reset default pinout.
I2CI2C_SCL3I/OI/O (open drain)I2C clock data
5
9
12
I2C_SDA4I/OI/O (open drain)I2C data
6
10
18
TimersGT_PWM063I/OOPulse-width modulated O/P
GT_CCP0146I/OITimer capture port
GT_PWM074I/OOPulse-width modulated O/P
GT_CCP0247I/OITimer capture ports
GT_CCP039I/OI
GT_CCP0410I/OI
11I/OI
GT_CCP055I/OI
GT_CCP066I/OI
18I/OI
51I/OI
53I/OI
GT_CCP077I/OI
PWM018I/OOPulse-width modulated outputs
GT_PWM0321I/OO
GT_PWM0223OO
GT_CCP0044I/OITimer capture ports
54I/OI
GT_CCP0542I/OI
GT_CCP0146I/OI
GT_CCP0247I/OI
GT_CCP0550IITimer capture port Input
GT_PWM0554I/OOPulse-width modulated output
GPIOGPIO103I/OI/OGeneral-purpose inputs or outputs
GPIO114I/OI/O
GPIO145I/OI/O
GPIO156I/OI/O
GPIO167I/OI/O
GPIO178I/OI/O
GPIO129I/OI/O
GPIO1310I/OI/O
GPIO2211I/OI/O
GPIO2312I/OI/O
GPIO2418I/OI/O
GPIO2819I/OI/O
GPIO2922I/OI/O
GPIO2523OO
GPIO044I/OI/O
GPIO3042I/OI/O
GPIO146I/OI/O
GPIO247I/OI/O
GPIO348I/OI/O
GPIO449I/OI/O
GPIO550I/OI/O
GPIO651I/OI/O
GPIO752I/OI/O
GPIO853I/OI/O
GPIO954I/OI/O
McASP
I2S or PCM
MCAFSX4I/OOI2S audio port frame sync
11
18
23
42
53
McACLK9I/OOI2S audio port clock outputs
42I/OO
McAXR144I/OI/OI2S audio port data 1 (RX/TX)
50II/OI2S audio port data 1 (RX and TX)
McAXR044I/OI/OI2S audio port data 0 (RX and TX)
54I/OI/OI2S audio port data (RX and TX)
McACLKX52I/OOI2S audio port clock
Multimedia card
(MMC or SD)
SDCARD_CLK3I/OOSD card clock data
7
SDCARD_CMD4I/OI/O (open drain)SD card command line
8I/OI/O
SDCARD_DATA06I/OI/OSD card data
54
SDCARD_IRQ53I/OIInterrupt from SD card(3)
Parallel interface
(8-bit π)
pXCLK (XVCLK)4I/OOFree clock to parallel camera
pVS (VSYNC)9I/OIParallel camera vertical sync
pHS (HSYNC)10I/OIParallel camera horizontal sync
pDATA8 (CAM_D4)5I/OIParallel camera data bit 4
pDATA9 (CAM_D5)6I/OIParallel camera data bit 5
pDATA10 (CAM_D6)7I/OIParallel camera data bit 6
pDATA11 (CAM_D7)8I/OIParallel camera data bit 7
pCLK (PIXCLK)46I/OIPixel clock from parallel camera sensor
pDATA7 (CAM_D3)48I/OIParallel camera data bit 3
pDATA6 (CAM_D2)49I/OIParallel camera data bit 2
pDATA5 (CAM_D1)50IIParallel camera data bit 1
pDATA4 (CAM_D0)51I/OIParallel camera data bit 0
PowerVBAT137Power supply for the module
VBAT240Power supply for the module
RF(4)RF_ABG31I/OIWLAN analog RF 802.11 a/b/g/n bands
SPIGSPI_CLK5I/OI/OGeneral SPI clock
GSPI_MISO6I/OI/OGeneral SPI MISO
42I/OI/O
GSPI_CS8I/OI/OGeneral SPI device select
44I/OI/O
GSPI_MOSI7I/OI/OGeneral SPI MOSI
FLASH SPIFLASH_SPI_CLK15OOClock to SPI serial flash (fixed default)
FLASH_SPI_DOUT17OOData to SPI serial flash (fixed default)
FLASH_SPI_DIN13IIData from SPI serial flash (fixed default)
FLASH_SPI_CS14OODevice select to SPI serial flash (fixed default)
UARTUART1_TX3I/OOUART TX data
7I/OO
12I/OO
46I/OO
48I/OOUART1 TX data
UART1_RX4I/OIUART RX data
8I/OI
18I/OI
47I/OIUART1 RX data
49I/OI
UART1_RTS44I/OOUART1 request-to-send (active low)
52I/OO
UART1_CTS51I/OIUART1 clear-to-send (active low)
UART0_TX9I/OOUART0 TX data
42I/OO
46I/OO
52I/OO
UART0_RX10I/OIUART0 RX data
47I/OIUART0 RX data
UART0_CTS44I/OIUART0 clear-to-send input (active low)
51
UART0_RTS44I/OOUART0 request-to-send (active low)
51I/OO
52I/OO
Sense-On-PowerSOP223(5)OISense-on-power 2
SOP124IIConfiguration sense-on-power 1
SOP034IIConfiguration sense-on-power 0
LPDS retention unavailable.
The CC3235MODx or CC3235MODAx modules are compatible with TI BLE modules using an external RF switch.
Future support.
This pins is not accessible on the CC3235MODAx devices as it is directly tied to the integrated antenna.
This pin has dual functions: as a SOP[2] (device operation mode), and as an external TCXO enable. As a TXCO enable, the pin is an output on power up and driven logic high. During hibernate low-power mode, the pin is in a Hi-Z state but is pulled down for SOP mode to disable TCXO. Because of the SOP functionality, the pin must be used as an output only.