SWRS243B Data sheet

SWRS243B February 2020 – May 2021 CC3235MODAS , CC3235MODASF , CC3235MODS , CC3235MODSF

PRODUCTION DATA

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)

MON|63

Thermal pad, mechanical data (Package|Pins)

Orderable Information

swrs243b_oa

7.3 Signal Descriptions

Table 7-2 Signal Descriptions

FUNCTION	SIGNAL NAME	PIN NO.	PIN TYPE	SIGNAL DIRECTION	DESCRIPTION
ADC	ADC_CH0	47	I/O	I	ADC channel 0 input (maximum of 1.5 V)
	ADC_CH1	48	I/O	I	ADC channel 1 input (maximum of 1.5 V)
	ADC_CH2	49	I/O	I	ADC channel 2 input (maximum of 1.5 V)
	ADC_CH3	50	I	I	ADC channel 3 input (maximum of 1.5 V)
BLE/2.4 GHz radio coexistence^⁽²⁾	GPIO10	3	I/O	I/O	Coexistence inputs and outputs
	GPIO14	5	I/O	I/O
	GPIO15	6	I/O	I/O
	GPIO16	7	I/O	I/O
	GPIO17	8	I/O	I/O
	GPIO12	9	I/O	I/O
	GPIO22	11	I/O	I/O
	GPIO28	19^⁽¹⁾	I/O	I/O
	GPIO0	44	I/O	I/O
	GPIO30	42^⁽¹⁾	I/O	I/O
	GPIO5	50	I/O	I/O
	GPIO6	51	I/O	I/O
	GPIO8	53	I/O	I/O
	GPIO9	54	I/O	I/O
Hostless mode	HM_IO	3	I/O	I/O	Hostless mode inputs and outputs
		4	I/O	O
		5	I/O	I/O
		6	I/O	I/O
		7	I/O	I/O
		8	I/O	I/O
		9	I/O	I/O
		10	I/O	O
		11	I/O	I/O
		19^⁽¹⁾	I/O	I/O
		23	O	O
		42^⁽¹⁾	I/O	I/O
		44	I/O	I/O
		48	O	O
		49	O	O
		50	I/O	I/O
		51	I/O	I/O
		53	I/O	I/O
		54	I/O	I/O
JTAG / SWD	TDI	12	I/O	I	JTAG TDI. Reset default pinout.
	TDO	18	I/O	O	JTAG TDO. Reset default pinout.
	TCK	21	I/O	I	JTAG/SWD TCK. Reset default pinout.
	TMS	22	I/O	I/O	JTAG/SWD TMS. Reset default pinout.
I²C	I2C_SCL	3	I/O	I/O (open drain)	I²C clock data
		5
		9
		12
	I2C_SDA	4	I/O	I/O (open drain)	I²C data
		6
		10
		18
Timers	GT_PWM06	3	I/O	O	Pulse-width modulated O/P
	GT_CCP01	46	I/O	I	Timer capture port
	GT_PWM07	4	I/O	O	Pulse-width modulated O/P
	GT_CCP02	47	I/O	I	Timer capture ports
	GT_CCP03	9	I/O	I
	GT_CCP04	10	I/O	I
	GT_CCP04	11	I/O	I
	GT_CCP05	5	I/O	I
	GT_CCP06	6	I/O	I
		18	I/O	I
		51	I/O	I
		53	I/O	I
	GT_CCP07	7	I/O	I
	PWM0	18	I/O	O	Pulse-width modulated outputs
	GT_PWM03	21	I/O	O
	GT_PWM02	23	O	O
	GT_CCP00	44	I/O	I	Timer capture ports
	GT_CCP00	54	I/O	I
	GT_CCP05	42	I/O	I
	GT_CCP01	46	I/O	I
	GT_CCP02	47	I/O	I
	GT_CCP05	50	I	I	Timer capture port Input
	GT_PWM05	54	I/O	O	Pulse-width modulated output
GPIO	GPIO10	3	I/O	I/O	General-purpose inputs or outputs
	GPIO11	4	I/O	I/O
	GPIO14	5	I/O	I/O
	GPIO15	6	I/O	I/O
	GPIO16	7	I/O	I/O
	GPIO17	8	I/O	I/O
	GPIO12	9	I/O	I/O
	GPIO13	10	I/O	I/O
	GPIO22	11	I/O	I/O
	GPIO23	12	I/O	I/O
	GPIO24	18	I/O	I/O
	GPIO28	19	I/O	I/O
	GPIO29	22	I/O	I/O
	GPIO25	23	O	O
	GPIO0	44	I/O	I/O
	GPIO30	42	I/O	I/O
	GPIO1	46	I/O	I/O
	GPIO2	47	I/O	I/O
	GPIO3	48	I/O	I/O
	GPIO4	49	I/O	I/O
	GPIO5	50	I/O	I/O
	GPIO6	51	I/O	I/O
	GPIO7	52	I/O	I/O
	GPIO8	53	I/O	I/O
	GPIO9	54	I/O	I/O
McASP I²S or PCM	MCAFSX	4	I/O	O	I²S audio port frame sync
		11
		18
		23
		42
		53
	McACLK	9	I/O	O	I²S audio port clock outputs
	McACLK	42	I/O	O	I²S audio port clock outputs
	McAXR1	44	I/O	I/O	I²S audio port data 1 (RX/TX)
	McAXR1	50	I	I/O	I²S audio port data 1 (RX and TX)
	McAXR0	44	I/O	I/O	I²S audio port data 0 (RX and TX)
	McAXR0	54	I/O	I/O	I²S audio port data (RX and TX)
	McACLKX	52	I/O	O	I²S audio port clock
Multimedia card (MMC or SD)	SDCARD_CLK	3	I/O	O	SD card clock data
	SDCARD_CLK	7	I/O	O	SD card clock data
	SDCARD_CMD	4	I/O	I/O (open drain)	SD card command line
	SDCARD_CMD	8	I/O	I/O	SD card command line
	SDCARD_DATA0	6	I/O	I/O	SD card data
	SDCARD_DATA0	54	I/O	I/O	SD card data
	SDCARD_IRQ	53	I/O	I	Interrupt from SD card^⁽³⁾
Parallel interface (8-bit π)	pXCLK (XVCLK)	4	I/O	O	Free clock to parallel camera
	pVS (VSYNC)	9	I/O	I	Parallel camera vertical sync
	pHS (HSYNC)	10	I/O	I	Parallel camera horizontal sync
	pDATA8 (CAM_D4)	5	I/O	I	Parallel camera data bit 4
	pDATA9 (CAM_D5)	6	I/O	I	Parallel camera data bit 5
	pDATA10 (CAM_D6)	7	I/O	I	Parallel camera data bit 6
	pDATA11 (CAM_D7)	8	I/O	I	Parallel camera data bit 7
	pCLK (PIXCLK)	46	I/O	I	Pixel clock from parallel camera sensor
	pDATA7 (CAM_D3)	48	I/O	I	Parallel camera data bit 3
	pDATA6 (CAM_D2)	49	I/O	I	Parallel camera data bit 2
	pDATA5 (CAM_D1)	50	I	I	Parallel camera data bit 1
	pDATA4 (CAM_D0)	51	I/O	I	Parallel camera data bit 0
Power	VBAT1	37	—	—	Power supply for the module
Power	VBAT2	40	—	—	Power supply for the module
RF^⁽⁴⁾	RF_ABG	31	I/O	I	WLAN analog RF 802.11 a/b/g/n bands
SPI	GSPI_CLK	5	I/O	I/O	General SPI clock
	GSPI_MISO	6	I/O	I/O	General SPI MISO
	GSPI_MISO	42	I/O	I/O	General SPI MISO
	GSPI_CS	8	I/O	I/O	General SPI device select
	GSPI_CS	44	I/O	I/O	General SPI device select
	GSPI_MOSI	7	I/O	I/O	General SPI MOSI
FLASH SPI	FLASH_SPI_CLK	15	O	O	Clock to SPI serial flash (fixed default)
	FLASH_SPI_DOUT	17	O	O	Data to SPI serial flash (fixed default)
	FLASH_SPI_DIN	13	I	I	Data from SPI serial flash (fixed default)
	FLASH_SPI_CS	14	O	O	Device select to SPI serial flash (fixed default)
UART	UART1_TX	3	I/O	O	UART TX data
		7	I/O	O
		12	I/O	O
		46	I/O	O
		48	I/O	O	UART1 TX data
	UART1_RX	4	I/O	I	UART RX data
		8	I/O	I
		18	I/O	I
		47	I/O	I	UART1 RX data
		49	I/O	I	UART1 RX data
	UART1_RTS	44	I/O	O	UART1 request-to-send (active low)
	UART1_RTS	52	I/O	O	UART1 request-to-send (active low)
	UART1_CTS	51	I/O	I	UART1 clear-to-send (active low)
	UART0_TX	9	I/O	O	UART0 TX data
		42	I/O	O
		46	I/O	O
		52	I/O	O
	UART0_RX	10	I/O	I	UART0 RX data
	UART0_RX	47	I/O	I	UART0 RX data
	UART0_CTS	44	I/O	I	UART0 clear-to-send input (active low)
	UART0_CTS	51	I/O	I	UART0 clear-to-send input (active low)
	UART0_RTS	44	I/O	O	UART0 request-to-send (active low)
		51	I/O	O
		52	I/O	O
Sense-On-Power	SOP2	23^⁽⁵⁾	O	I	Sense-on-power 2
	SOP1	24	I	I	Configuration sense-on-power 1
	SOP0	34	I	I	Configuration sense-on-power 0

(1) LPDS retention unavailable.

(2) The CC3235MODx or CC3235MODAx modules are compatible with TI BLE modules using an external RF switch.

(3) Future support.

(4) This pins is not accessible on the CC3235MODAx devices as it is directly tied to the integrated antenna.

(5) This pin has dual functions: as a SOP[2] (device operation mode), and as an external TCXO enable. As a TXCO enable, the pin is an output on power up and driven logic high. During hibernate low-power mode, the pin is in a Hi-Z state but is pulled down for SOP mode to disable TCXO. Because of the SOP functionality, the pin must be used as an output only.