SWRS333 Data sheet

SWRS333A July 2025 – August 2025 CC3300MOD , CC3301MOD

PRODUCTION DATA

Package Options

Mechanical Data (Package|Pins)

MOZ|65

Thermal pad, mechanical data (Package|Pins)

Orderable Information

swrs333a_oa

5.2 Pin Descriptions

Table 5-1 Pin Descriptions

PIN	SIGNAL NAME	TYPE	DIR (I/O)	VOLTAGE LEVEL	SHUTDOWN STATE	STATE AFTER POWER-UP	DESCRIPTION
1	GND	GND					GND
2	GND	GND					GND
3	SDIO CLK	Digital	I	1.8V	HiZ	HiZ	SDIO clock or SPI clock
4	SDIO CMD	Digital	I/O	1.8V	HiZ	HiZ	SDIO command or SPI PICO
5	SDIO_D3	Digital	I/O	1.8V	HiZ	PU	SDIO data D3 or SPI CS
6	SDIO_D2	Digital	I/O	1.8V	HiZ	HiZ	SDIO data D2
7	SDIO_D1	Digital	I/O	1.8V	HiZ	HiZ	SDIO data D1
8	SDIO_D0	Digital	I/O	1.8V	HiZ	HiZ	SDIO data D0 or SPI POCI
9	Logger³	Digital	O	1.8V	PU	PU	Tracer (UART TX debug logger)
10	Host_IRQ_WL³	Digital	O	1.8V	PD	0	Interrupt request to host for WLAN
11	Host_IRQ_BLE	Digital	O	1.8V	PD	PD	Reserved for future use
12	SWDIO	Digital	I/O	1.8V	PU	PU	Serial wire debug I/O
13	SWCLK	Digital	I	1.8V	PD	PD	Serial wire debug clock
14	GND	GND					GND
15	GND	GND					GND
16	GND	GND					GND
17	nReset	Digital	I	1.8V	PD	PD	Reset line for enabling or disabling device (active low)
18	SLOW_CLK_IN	Digital	I	1.8V	PD	PD	32.768kHZ RTC clock input
19	VPP_IN	POW					1.8V OTP programming input supply
20	GND	GND					GND
21	GND	GND					GND
22	GND	GND					GND
23	RF_OUT	RF	I/O				Bluetooth Low Energy and WLAN 2.4GHz RF port
24	GND	GND					GND
25	GND	GND					GND
26	GND	GND					GND
27	GND	GND					GND
28	GND	GND					GND
29	GND	GND					GND
30	GND	GND					GND
31	GND	GND					GND
32	GND	GND					GND
33	GND	GND					GND
34	GND	GND					GND
35	GND	GND					GND
36	GND	GND					GND
37	3V3_IN	POW					VDD PA Voltage
38	3V3_IN	POW					VDD PA Voltage
39	GND	GND					GND
40	GND	GND					GND
41	GND	GND					GND
42	GND	GND					GND
43	GND	GND					GND
44	GND	GND					GND
45	COEX_PRIORITY²	Digital	I	1.8V	PU	PU	External coexistence interface: priority
46	COEX_REQ²	Digital	I	1.8V	PU	PU	External coexistence interface: request
47	COEX_GRANT²	Digital	O	1.8V	PD	PD	External coexistence interface: grant
48	UART RTS	Digital	O	1.8V	PU	PU	Device RTS signal: flow control for BLE HCI
49	UART CTS	Digital	I	1.8V	PU	PU	Device CTS signal: flow control for BLE HCI
50	UART RX	Digital	I	1.8V	PU	PU	UART RX for BLE HCI
51	UART TX	Digital	O	1.8V	PU	PU	UART TX for BLE HCI
52	ANT_SEL²	Digital	O	1.8V	PD	PD	Antenna select control line
53	1V8_IN	POW					Main supply voltage for analog and digital—VDD_MAIN_IN, VDDA_IN1, VDDA_IN2, VIO
54	1V8_IN	POW					Main supply voltage for analog and digital—VDD_MAIN_IN, VDDA_IN1, VDDA_IN2, VIO
55	GND	GND					GND
56	GND	GND					GND
57	GND	GND					GND
58	GND	GND					GND
59	GND	GND					GND
60	GND	GND					GND
61	GND	GND					GND
62	GND	GND					GND
63	GND	GND					GND
64	GND	GND					GND
65	GND	GND					GND

All digital I/Os (with the exception of SDIO signals) are Hi-Z when the device is in shutdown mode with internal PU/PD according to the "shutdown state" column.
See software release notes for support level.
Logger and Host_IRQ_WL pins are sensed by the device during boot, see CC33xx Hardware Integration.