SWRS333A July 2025 – August 2025 CC3300MOD , CC3301MOD
PRODUCTION DATA
Figure 6-3 SDIO HS Input Timing
Figure 6-4 SDIO HS Output Timing| Parameter | Description | MIN | MAX | Unit |
|---|---|---|---|---|
| fclock | Clock frequency, CLK | 52 | MHz | |
| tHigh | High Period | 7 | ns | |
| tLow | Low Period | 7 | ||
| tTLH | Rise time, CLK | 3 | ||
| tTHL | Fall time, CLK | 3 | ||
| tISU | Setup time, input valid before CLK ↑ | 6 | ||
| tIH | Hold time, input valid after CLK ↑ | 2 | ||
| tODLY | Delay time, CLK ↑ to output valid | 2 | 14 | |
| CL | Capacitive load on outputs | 15 | 40 | pF |