SNAS786D August   2019  – November 2026 CDCE6214-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  EEPROM Characteristics
    6. 5.6  Reference Input, Single-Ended Characteristics
    7. 5.7  Reference Input, Differential Characteristics
    8. 5.8  Reference Input, Crystal Mode Characteristics
    9. 5.9  General-Purpose Input Characteristics
    10. 5.10 Triple Level Input Characteristics
    11. 5.11 Logic Output Characteristics
    12. 5.12 Phase Locked Loop Characteristics
    13. 5.13 Closed-Loop Output Jitter Characteristics
    14. 5.14 Input and Output Isolation
    15. 5.15 Buffer Mode Characteristics
    16. 5.16 PCIe Spread Spectrum Generator
    17. 5.17 LVCMOS Output Characteristics
    18. 5.18 LP-HCSL Output Characteristics
    19. 5.19 LVDS Output Characteristics
    20. 5.20 Output Synchronization Characteristics
    21. 5.21 Power-On Reset Characteristics
    22. 5.22 I2C-Compatible Serial Interface Characteristics
    23. 5.23 Timing Requirements, I2C-Compatible Serial Interface
    24. 5.24 Power Supply Characteristics
    25. 5.25 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Reference Inputs
    2. 6.2 Outputs
    3. 6.3 Serial Interface
    4. 6.4 PSNR Test
    5. 6.5 Clock Interfacing and Termination
      1. 6.5.1 Reference Input
      2. 6.5.2 Outputs
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Reference Block
        1. 7.3.1.1 Zero Delay Mode, Internal and External Path
      2. 7.3.2 Phase-Locked Loop (PLL)
        1. 7.3.2.1 PLL Configuration and Divider Settings
        2. 7.3.2.2 Spread Spectrum Clocking
        3. 7.3.2.3 Digitally-Controlled Oscillator and Frequency Increment or Decrement - Serial Interface Mode and GPIO Mode
      3. 7.3.3 Clock Distribution
        1. 7.3.3.1 Glitchless Operation
        2. 7.3.3.2 Divider Synchronization
        3. 7.3.3.3 Global and Individual Output Enable
      4. 7.3.4 Power Supplies and Power Management
      5. 7.3.5 Control Pins
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation Modes
        1. 7.4.1.1 Fall-Back Mode
        2. 7.4.1.2 Pin Mode
        3. 7.4.1.3 Serial Interface Mode
    5. 7.5 Programming
      1. 7.5.1 I2C Serial Interface
      2. 7.5.2 EEPROM
        1. 7.5.2.1 EEPROM - Cyclic Redundancy Check
        2. 7.5.2.2 Recommended Programming Procedure
        3. 7.5.2.3 EEPROM Access
          1. 7.5.2.3.1 Register Commit Flow
          2. 7.5.2.3.2 Direct Access Flow
        4. 7.5.2.4 Register Bits to EEPROM Mapping
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Recommended Register Settings for PCIe Applications
    4. 8.4 Power Supply Recommendations
      1. 8.4.1 Power-Up Sequence
      2. 8.4.2 Decoupling
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Examples
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
      2. 9.1.2 Device Nomenclature
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Package Option Addendum
    2. 11.2 Tape and Reel Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RGE|24
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.17 LVCMOS Output Characteristics

VDD_VCO, VDDO_12, VDDO_34, VDD_REF = 1.8V ± 5%, 2.5V ± 5%, 3.3V ± 5% and TA = -40°C to 105°C
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
fO_LVCMOSOutput frequency2pF to GND, normal mode0.024200MHz
VOH_LVCMOSOutput high voltageIOH = 1mA, VDDO_x is corresponding supply voltage.0.8 × VDDO_xV
VOL_LVCMOSOutput low voltageIOL = 1mA, VDDO_x is corresponding supply voltage.0.2 × VDDO_xV
IOHOutput high currentVout = 0.8 × VDDO_x, VDDO_x = 1.8V-6mA
IOHOutput high currentVout = 0.8 × VDDO_x, VDDO_x = 2.5V-8.5mA
IOHOutput high currentVout = 0.8 × VDDO_x, VDDO_x = 3.3V-11.2mA
IOLOutput low currentVout = 0.2 × VDDO_x, VDDO_x = 1.8V6mA
IOLOutput low currentVout = 0.2 × VDDO_x, VDDO_x = 2.5V8.5mA
IOLOutput low currentVout = 0.2 × VDDO_x, VDDO_x = 3.3V11.2mA
TRISE-FALLOutput rise/fall time20/80%, CL= 5pF, normal mode300500700ps
TRISE-FALLOutput rise/fall time20/80%, CL= 5pF, slow mode, measured on OUT01000ps
TSKEWOutput-to-output skew(1)LVCMOS-to-LVCMOS outputs, same divide value100ps
TSKEWOutput-to-output skew(1)LVCMOS-to-Differential outputs, same divide value400ps
ODCOutput duty cycleNot in PLL bypass mode4555%
RON_LVCMOSOutput impedanceNormal mode456075Ω
RON_LVCMOSOutput impedanceSlow mode506585Ω
(1) OUT1/OUT4 and OUT2/OUT3 are matched pair-wise. OUT1/OUT4 has LVCMOS buffer while OUT2/OUT3 do not have LVCMOS buffer. OUT1/OUT4 is matched within TOUT-SKEW. OUT2/OUT3 is matched within TOUT-SKEW.