SLPS422B March   2013  – August 2016 CSD97376Q4M

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Application Diagram
      2.      Typical Power Stage Efficiency and Power Loss
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Functional Block Diagram
    2. 7.2 Powering CSD97376Q4M and Gate Drivers
    3. 7.3 Undervoltage Lockout Protection (UVLO)
    4. 7.4 PWM Pin
    5. 7.5 SKIP# Pin
      1. 7.5.1 Zero Crossing (ZX) Operation
    6. 7.6 Integrated Boost-Switch
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Power Loss Curves
    3. 8.3 Safe Operating Curves (SOA)
    4. 8.4 Normalized Curves
    5. 8.5 Calculating Power Loss and SOA
      1. 8.5.1 Design Example
      2. 8.5.2 Calculating Power Loss
      3. 8.5.3 Calculating SOA Adjustments
  9. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 Recommended PCB Design Overview
      2. 9.1.2 Electrical Performance
      3. 9.1.3 Thermal Performance
    2. 9.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Community Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  11. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Package Dimensions
    2. 11.2 Recommended PCB Land Pattern
    3. 11.3 Recommended Stencil Opening

Package Options

Mechanical Data (Package|Pins)
  • DPC|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

TA = 25°C, VDD = POR to 5.5 V (unless otherwise noted)
PARAMETER CONDITIONS MIN TYP MAX UNIT
PLOSS
Power loss(1) VIN = 12 V, VDD = 5 V, VOUT = 1.8 V, IOUT = 12 A,
ƒSW = 500 kHz, LOUT = 0.29 µH , TJ = 25°C		 2.2 W
Power loss(2) VIN = 19 V, VDD = 5 V, VOUT = 1.8 V, IOUT = 12 A,
ƒSW = 500 kHz, LOUT = 0.29 µH , TJ = 25°C		 2.4 W
Power loss(2) VIN = 19 V, VDD = 5 V, VOUT = 1.8 V, IOUT = 12 A,
ƒSW = 500 kHz, LOUT = 0.29 µH , TJ = 125°C		 3 W
VIN
IQ VIN quiescent current PWM = floating, VDD = 5 V, VIN = 24 V 1 µA
VDD
IDD Standby supply current PWM = float, SKIP# = VDD or 0 V 130 µA
SKIP# = float 8
IDD Operating supply current PWM = 50% duty cycle, ƒSW = 500 kHz 5.3 mA
POWER-ON RESET AND UNDERVOLTAGE LOCKOUT
VDD rising Power-on reset 4.15 V
VDD falling UVLO 3.7 V
Hysteresis 0.2 mV
PWM AND SKIP# I/O SPECIFICATIONS
RI Input impedance Pullup to VDD 1700 kΩ
Pulldown (to GND) 800
VIH Logic level high 2.65 V
VIL Logic level low 0.6 V
VIH Hysteresis 0.2 V
VTS Tri-state voltage 1.3 2 V
tTHOLD(off1) Tri-state activation time (falling) PWM 60 ns
tTHOLD(off2) Tri-state activation time (rising) PWM 60 ns
tTSKF Tri-state activation time (falling) SKIP# 1 µs
tTSKR Tri-state activation time (rising) SKIP# 1 µs
t3RD(PWM)(2) Tri-state exit time PWM 100 ns
t3RD(SKIP#)(2) Tri-state exit time SKIP# 50 µs
BOOTSTRAP SWITCH
VFBST Forward voltage IF = 10 mA 120 240 mV
IRLEAK(2) Reverse leakage VBST – VDD = 25 V 2 µA
(1) Measurement made with six 10 µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across VIN to PGND pins.
(2) Specified by design.