SBAS940 December 2018 DAC8742H
The modem status register is a read/write register. When an event occurs, the corresponding bit to indicate that event is set to a logic 1 in this register. The status bits are sticky, meaning they are not cleared unless a 1 is written to the corresponding bit position, except for carrier detect, or CD, which responds based on the presences of a carrier, the FIFO level registers, which respond based on the conditions of the FIFOs, and JAB_OFF and JAB_ON which represent the current status of the jabber inibhior. CTS will assert after RTS is set and no carrier is present if not operating in full-duplex mode.
MODEM_STATUS is shown in Figure 25 and described in Table 6.
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|FIFO_M2D LEVEL||FIFO_M2D FULL||FIFO_M2D EMPTY||FIFO_D2M LEVEL||FIFO_D2M FULL||FIFO_D2M EMPTY||CD||CTS|
|15||RST||R/W||0||A reset has occurred|
|14||JAB_OFF||R/W||0||This bit goes high when the jabber inhibitor timeout period has expired|
|13||JAB_ON||R/W||0||This bit goes high when the jabber inhibitor has been triggered|
|12||GAP||R/W||0||A gap error in HART mode|
|11||FRAME||R/W||0||A frame error in HART mode or a 1/2 bit slip in FF/PA mode|
|10||PARITY||R/W||0||A Parity error in HART mode|
|9||WDT||R/W||0||The watch-dog timer has expired|
|8||CRC||R/W||0||An incorrect CRC word was provided in a read or write command|
|7||FIFO_M2D_LEVEL||R/W||0||The receive FIFO is at the programmed level|
|6||FIFO_M2D_FULL||R/W||0||The receive FIFO is full|
|5||FIFO_M2D_EMPTY||R/W||0||The receive FIFO is empty|
|4||FIFO_D2M_LEVEL||R/W||0||The transmit FIFO is at the programmed level|
|3||FIFO_D2M_FULL||R/W||0||The transmit FIFO is full|
|2||FIFO_D2M_EMPTY||R/W||0||The transmit FIFO is empty|
|1||CD||R||0||In HART mode, a valid carrier has been detected|
|0||CTS||R||0||In HART mode, the modem is cleared to send data and the modulator is active|