SBAS940 December 2018 DAC8742H
SPI interfaced devices include an interrupt request, or IRQ, pin to communicate the occurrence of a variety of events to the host controller. The behavior of the IRQ pin is controlled by the CONTROL register and MODEM IRQ MASK register.
The CONTROL register allows the host controller to configure the IRQ pin as level sensitive or edge sensitive via the IRQ LEVEL bit (bit 2). For both level sensitive and edge sensitive modes, the polarity of the IRQ pin can be set via the IRQ POLARITY bit (bit 3) in the CONTROL register.
The MODEM IRQ MASK register allows the controller to decide which events are able to trigger the IRQ pin to toggle. If a logic 0 is written to the respective bit, that event is allowed to toggle the IRQ pin. If a logic 1 is written to the respective bit, the event is masked from the IRQ pin.
When an event occurs the IRQ pin signal, in the case of level-sensitive configurations, is latched and the IRQ pin voltage stays at logic high until the status has been reset, or cleared, by reading the contents of the MODEM_STATUS register. In the case of edge-sensitive configurations a pulse is generated any time a new event is detected.