SBAS940 December 2018 DAC8742H
The SPI interface can operate on SCLK speeds up to 12.5 MHz, but the frame-rate must be greater than 2442 ns in HART mode and 3000 ns in FOUNDATION FIELDBUS and PROFIBUS PA mode. Frames must contain at least 24-bits without CRC enabled and 32-bits with CRC enabled. The data within the frame is right justified, meaning that upon the rising edge of CS the right-most, or last, 24-bits or 32-bits will be evaluated as the input data word. Two modes of SPI are supported by the interface: clock polarity 0 and clock phase 1 or clock polarity 1 and clock phase 0.
The SDO pin will output data on the rising edge of SCLK or the falling edge of CS. SDO will always provide information from the previous frame, if the previous frame was a read then the output data will be the requested data. If the previous write was a command or register write, that data will be repeated. This allows a method for the user to verify what was written to the device. If CRC is enabled and write data is being repeated on SDO, the CRC provided during the previous frame will be output – not a newly calculated CRC.
The SPI frame structure is shown in the figure below. The frame includes a read/write bit, followed by a 7-bit address, then 16-bit write data for a write frame or don’t care bits for a read frame. If CRC is enabled, an additional 8-bits are placed at the end of the frame containing the CRC word.
|Write Frame||0||7-Bit Address||Write Data|
|Read Frame||1||7-Bit Address||X|