SBAS940 December   2018 DAC8742H


  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Simplified Schematic
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  HART Modulator
      2. 7.3.2  HART Demodulator
      3. 7.3.3  FOUNDATION FIELDBUS / PROFIBUS PA Manchester Encoder
      4. 7.3.4  FOUNDATION FIELDBUS / PROFIBUS PA Manchester Decoder
      5. 7.3.5  Internal Reference
      6. 7.3.6  Clock Configuration
      7. 7.3.7  Reset and Power-Down
      8. 7.3.8  Full-Duplex Mode
      9. 7.3.9  I/O Selection
      10. 7.3.10 Jabber Inhibitor
    4. 7.4 Device Functional Modes
      1. 7.4.1 UART Interfaced HART
      3. 7.4.3 SPI Interfaced HART
      5. 7.4.5 Interface
        1. UART
          1. UART Carrier Detect
        2. SPI
          1. SPI Cyclic Redundancy Check
          2. SPI Interrupt Request
    5. 7.5 Register Maps
      1. 7.5.1 CONTROL Register (Offset = 2h) [reset = 0x8042]
        1. Table 4. CONTROL Register Field Descriptions
      2. 7.5.2 RESET Register (Offset = 7h) [reset = 0x0000]
        1. Table 5. RESET Register Field Descriptions
      3. 7.5.3 MODEM_STATUS Register (Offset = 20h) [reset = 0x0000]
        1. Table 6. MODEM_STATUS Register Field Descriptions
      4. 7.5.4 MODEM_IRQ_MASK Register (Offset = 21h) [reset = 0x0024]
        1. Table 7. MODEM_IRQ_MASK Register Field Descriptions
      5. 7.5.5 MODEM_CONTROL Register (Offset = 22h) [reset = 0x0048]
        1. Table 8. MODEM_CONTROL Register Field Descriptions
      6. 7.5.6 FIFO_D2M Register (Offset = 23h) [reset = 0x0200]
        1. Table 9. FIFO_D2M Register Field Descriptions
      7. 7.5.7 FIFO_M2D Register (Offset = 24h) [reset = 0x0200]
        1. Table 10. FIFO_M2D Register Field Descriptions
      8. 7.5.8 FIFO_LEVEL_SET Register (Offset = 25h) [reset = 0x0000]
        1. Table 11. FIFO_LEVEL_SET Register Field Descriptions
      9. 7.5.9 PAFF_JABBER Register (Offset = 27h) [reset = 0x0000]
        1. Table 12. PAFF_JABBER Register Field Descriptions
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Design Recommendations
      2. 8.1.2 Selecting the Crystal/Resonator
      3. 8.1.3 Included Functions and Filter Selection
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. DAC8742H HART Modem
        2. 2-Wire Current Loop
        3. Regulator
        4. DAC
        5. Amplifiers
        6. Diodes
        7. Passives
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information


FOUNDATION FIELDBUS and PROFIBUS PA are half-duplex communication protocols where only the encoder or decoder are active at any time and the DAC8742H arbitrates over which path is active. When interfacing the FOUNDATION FIELDBUS or PROFIBUS PA modem via the UART interface, data placed in the transmit FIFO is automatically placed on the FF/PA bus until the FIFO is empty any time the device is not receiving data, assuming correct data format.

When receiving data the decoder will expect a preamble byte(s) and a start delimiter byte. These bytes, as well as the stop byte, will be stripped from the UART communication and only the first data byte will be transmitted to start the data packet. The host controller must use a timer to detect the end of the packet. Each byte transmitted on the UART will be at 57.6 kHz BAUD and byte spacing of 256 us. If a new byte has not been started within 512 us it can be assumed that the incoming packet has ended.

The device expects to see a four byte sequence to initiate transmission: 0xEA followed by 0x80-0x9F, where bits 4:3 of the second byte configure an interrupt threshold for the transmit FIFO level and bits 2:0 set the number of preamble bytes to be transmitted. The third byte contains the information to configure the Jabber Inhibitor followed by the final byte of 0xAE. To send inverted Manchester encoded data the first byte, 0xEA, is inverted to 0x15 and the first three bits of the second byte are inverted such that the range of values for the second byte are from 0x60-0x7F. The functionality of bits 4:3 and 2:0 and the Jabber Inhibitor byte remain the same and the final byte is inverted to 0x51. The details concerning this four byte sequence are explained in the tables below.

B3 B2
Mode D7:D0 D7 D6 D5 D4 D3 D2 D1 D0
Non-inverted 1 1 1 0 1 0 1 0 1 0 0 D2M_LEVEL PRE_BYTES
Inverted 0 0 0 1 0 1 0 1 0 1 1 D2M_LEVEL PRE_BYTES
B1 B0
Mode D7:D0 D7 D6 D5 D4 D3 D2 D1 D0
Non-inverted JABBER_TIMEOUT 1 0 1 0 1 1 1 0
Inverted JABBER_TIMEOUT 0 1 0 1 0 0 0 1
D2M_LEVEL 0 0 Alarm on UART_RTS when transmit FIFO has less than 2 bytes loaded
0 1 Alarm on UART_RTS when transmit FIFO has less than 4 bytes loaded
1 0 Alarm on UART_RTS when transmit FIFO has less than 6 bytes loaded
1 1 Alarm on UART_RTS when transmit FIFO has less than 8 bytes loaded
PRE_BYTES Number of preamble bytes is equivalent to the straight binary decimal value in this register plus one

The JABBER_TIMEOUT bits control the timeout period for the Jabber Inhibitor. If a value of 0x0 is programmed the Jabber Inhibitor is disabled. Otherwise the timer will be programmed in 2.048ms increments such that the timeout can be calculated as shown below. If the Jabber Inhibitor triggers the CD pin will be taken high. The CD pin will be returned to logic low when the silence period of 3 seconds has ended.

Equation 1. TimeOut = JABBER_TIMEOUT x 2.048ms

The encoder will begin transmitting data once the following conditions are met: a valid four-byte transmission initiation sequence has been sent to the device, the FIFO is not empty, and the device is not receiving data. Transmission will begin by sending the preamble byte(s) followed by a start delimiter. Then, the encoder will begin to remove data from the FIFO – this creates at least a five-byte lag of the encoder with respect to the UART.

During transmission of a packet the UART must take care to ensure that the FIFO does not become empty before the packet is complete. The encoder transmits at a BAUD rate of 31.25 kHz or 256 µs per byte in the FIFO so the UART must keep up with this rate. The four-byte sequence that initiates a transmission includes setting a transmit FIFO threshold in bits 4:3. When the FIFO level is less than or equal to this threshold the UART_RTS pin will be taken high, this can be leveraged to ensure the FIFO is not prematurely empty. Once the FIFO is empty a stop delimiter is placed on the bus. Once the FIFO is empty a new packet can be initiated with a new four-byte transmission initiation sequence.

The device expects UART BAUD rate of 57.6 kHz. This BAUD rate is faster than the 31.25 kHz BAUD rate specified by FOUNDATION FIELDBUS and PROFIBUS PA, therefore FIFO overflow is possible. In order to prevent FIFO overflow, the UART_RTS pin FIFO threshold alarm can be leveraged by never adding more data to the FIFO than it can contain based on the programmed alarm threshold.