SBAS438C May 2008 – November 2019 DAC9881
When the RST pin is low, the device is in hardware reset, and the input register and DAC latch are set to the value defined by the RSTSEL pin. After RST goes high, the device is in normal operating mode, and the input register and DAC latch maintain the reset value until new data are written. When USB/BTC is connected to DGND, the device is in two's complement mode. In this mode, the LDAC pin cannot be kept at logic level 0 or toggled when a hardware reset is issued before writing a valid DAC data.