SBAS438C May 2008 – November 2019 DAC9881
Data are loaded into the device as a 24-bit word under the control of the serial clock input, SCLK. The timing diagrams for this operation are shown in timing diagrams section.
The CS input is a level-triggered input that acts as a frame synchronization signal and chip enable. Data can be transferred into the device only while CS is low. When CS is high, the SCLK and SDI signals are blocked out, and SDO is in high-Z status. To start the serial data transfer, CS should be taken low, observing the minimum delay from CS falling edge to SCLK rising edge, t2. After CS goes low, serial input data from SDI are clocked into the device input shift register on the rising edges of SCLK for 24 or more clock pulses. If a frame contains less than 24 bits of data, the frame is invalid. Invalid input data are not written into the input register and DAC, although the input register and DAC will continue to hold data from the preceding valid data cycle. If more than 24 bits of data are transmitted in one frame, the last 24 bits are written into the shift register and DAC. CS may be taken high after the rising edge of the 24th SCLK pulse, observing the minimum SCLK rising edge to CS rising edge time, t7. The contents of the shift register are transferred into the input register on the rising edge of CS. When data have been transferred into the input register of the DAC, the corresponding DAC register and DAC output can be updated by taking the LDAC pin low. Table 4 shows the input shift register data word format. D17 is the MSB of the 18-bit DAC data.