SBAS438C May   2008  – November 2019 DAC9881


  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Block Diagram
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: AVDD = 5 V
    6. 6.6  Electrical Characteristics: AVDD = 2.7 V
    7. 6.7  Timing Requirements—Standalone Operation Without SDO
    8. 6.8  Timing Requirements—Standalone Operation With SDO and Daisy-Chain Mode
    9. 6.9  Typical Characteristics: AVDD = 5 V
    10. 6.10 Typical Characteristics: AVDD = 2.7 V
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Analog Output
      2. 7.3.2  Reference Inputs
      3. 7.3.3  Output Range
      4. 7.3.4  Input Data Format
      5. 7.3.5  Hardware Reset
      6. 7.3.6  Power-On Reset
        1. Program Reset Value
      7. 7.3.7  Power Down
      8. 7.3.8  Double-Buffered Interface
        1. Load DAC Pin (LDAC)
          1. Synchronous Mode
          2. Asynchronous Mode
      9. 7.3.9  1.8-V to 5-V Logic Interface
      10. 7.3.10 Power-Supply Sequence
    4. 7.4 Device Functional Modes
      1. 7.4.1 Serial Interface
        1. Input Shift Register
          1. Stand-Alone Mode
          2. Daisy-Chain Mode
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Bipolar Operation Using the DAC9881
    2. 8.2 Typical Application
      1. 8.2.1 DAC9881 Sample-and-Hold Circuit
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curves
    3. 8.3 System Example
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Input Shift Register

Data are loaded into the device as a 24-bit word under the control of the serial clock input, SCLK. The timing diagrams for this operation are shown in timing diagrams section.

The CS input is a level-triggered input that acts as a frame synchronization signal and chip enable. Data can be transferred into the device only while CS is low. When CS is high, the SCLK and SDI signals are blocked out, and SDO is in high-Z status. To start the serial data transfer, CS should be taken low, observing the minimum delay from CS falling edge to SCLK rising edge, t2. After CS goes low, serial input data from SDI are clocked into the device input shift register on the rising edges of SCLK for 24 or more clock pulses. If a frame contains less than 24 bits of data, the frame is invalid. Invalid input data are not written into the input register and DAC, although the input register and DAC will continue to hold data from the preceding valid data cycle. If more than 24 bits of data are transmitted in one frame, the last 24 bits are written into the shift register and DAC. CS may be taken high after the rising edge of the 24th SCLK pulse, observing the minimum SCLK rising edge to CS rising edge time, t7. The contents of the shift register are transferred into the input register on the rising edge of CS. When data have been transferred into the input register of the DAC, the corresponding DAC register and DAC output can be updated by taking the LDAC pin low. Table 4 shows the input shift register data word format. D17 is the MSB of the 18-bit DAC data.

Table 4. Input Shift Register Data Word Format

BIT B23 B22 B21 B20 B19 B18 B17
B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
DATA X(1) X X X X X D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
X = don't care.