SBAS438C May 2008 – November 2019 DAC9881
When the SDOSEL pin is tied to IOVDD, the interface is in Stand-Alone mode. This mode provides serial readback for diagnostic purposes. The new input data (24 bits) are clocked into the device shift register and the existing data in the input register (24 bits) are shifted out from the SDO pin. If more than 24 SCLKs are clocked when CS is low, the contents of the input register are shifted out from the SDO pin, followed by zeroes; the last 24 bits of input data remain in the shift register. If less than 24 SCLKs are clocked while CS is low, the data from the SDO pin are part of the data in the input register and must be ignored. Refer to Figure 2 for further details.