DLPS048C March   2015  – June 2019 DLPC150


  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      DLP 0.2-Inch WVGA Chipset
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
    2. 5.1 DLPC150 Mechanical Data
      1. Table 1. I/O Type Subscript Definition
      2. Table 2. Internal Pullup and Pulldown Characteristics
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics Over Recommended Operating Conditions
    6. 6.6  Electrical Characteristics
    7. 6.7  High-Speed Sub-LVDS Electrical Characteristics
    8. 6.8  Low-Speed SDR Electrical Characteristics
    9. 6.9  System Oscillators Timing Requirements
    10. 6.10 Power-Up and Reset Timing Requirements
    11. 6.11 Parallel Interface Frame Timing Requirements
    12. 6.12 Parallel Interface General Timing Requirements
    13. 6.13 Flash Interface Timing Requirements
  7. Parameter Measurement Information
    1. 7.1 Host_irq Usage Model
    2. 7.2 Input Source
      1. 7.2.1 Parallel Interface Supports Two Data Transfer Formats
        1. Pdata Bus – Parallel Interface Bit Mapping Modes
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Interface Timing Requirements
        1. Parallel Interface
      2. 8.3.2 Serial Flash Interface
      3. 8.3.3 Serial Flash Programming
      4. 8.3.4 I2C Control Interface
      5. 8.3.5 DMD (Sub-LVDS) Interface
      6. 8.3.6 Calibration And Debug Support
      7. 8.3.7 DMD Interface Considerations
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 DLPC150 System Design Consideration – Application Notes
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. DLPC150 System Interfaces
          1. Control Interface
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 System Power-Up and Power-Down Sequence
    2. 10.2 DLPC150 Power-Up Initialization Sequence
    3. 10.3 DMD Fast Park Control (PARKZ)
    4. 10.4 Hot Plug Usage
    5. 10.5 Maximum Signal Transition Time
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 PCB Layout Guidelines For Internal Controller PLL Power
      2. 11.1.2 DLPC150 Reference Clock
        1. Recommended Crystal Oscillator Configuration
      3. 11.1.3 General PCB Recommendations
      4. 11.1.4 General Handling Guidelines for Unused CMOS-Type Pins
      5. 11.1.5 Maximum Pin-to-Pin, PCB Interconnects Etch Lengths
      6. 11.1.6 Number of Layer Changes
      7. 11.1.7 Stubs
      8. 11.1.8 Terminations
      9. 11.1.9 Routing Vias
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Device Nomenclature
        1. Device Markings
    2. 12.2 Related Links
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Package Option Addendum
      1. 13.1.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)

Serial Flash Interface

DLPC150 uses an external SPI serial flash memory device for configuration support. The minimum required size is dependent on the desired minimum number of sequences, CMT tables, and splash options while the maximum supported is 16 Mb.

For access to flash, the DLPC150 uses a single SPI interface operating at a programmable frequency complying to industry standard SPI flash protocol. The programmable SPI frequency is defined to be equal to 180 MHz/N, where N is a programmable value between 5 to 127 providing a range from 36.0 to 1.41732 MHz. Note that this results in a relatively large frequency step size in the upper range (for example, 36 MHz, 30 MHz, 25.7 MHz, 22.5 MHz, and so forth) and thus this must be taken into account when choosing a flash device.

The DLPC150 supports two independent SPI chip selects; however, the flash must be connected to SPI chip select zero (SPI0_CSZ0) because the boot routine is only executed from the device connected to chip select zero (SPI0_CSZ0). The boot routine uploads program code from flash to program memory, then transfers control to an auto-initialization routine within program memory. The DLPC150 asserts the HOST_IRQ output signal high while auto-initialization is in progress, then drives it low to signal its completion to the host processor. Only after auto-initialization is complete will the DLPC150 be ready to receive commands through I2C.

The DLPC150 should support any flash device that is compatible with the modes of operation, features, and performance as defined in Table 5 and Table 6.

Table 5. SPI Flash Required Features or Modes of Operation

SPI interface width Single
SPI protocol SPI mode 0
Fast READ addressing Auto-incrementing
Programming mode Page mode
Page size 256 B
Sector size 4 KB sector
Block size any
Block protection bits 0 = Disabled
Status register bit(0) Write in progress (WIP) \{also called flash busy\}
Status register bit(1) Write enable latch (WEN)
Status register bits(6:2) A value of 0 disables programming protection
Status register bit(7) Status register write protect (SRWP)
Status register bits(15:8)
(that is expansion status byte)
The DLPC150 only supports single-byte status register R/W command execution, and thus may not be compatible with flash devices that contain an expansion status byte. However, as long as expansion status byte is considered optional in the byte 3 position and any write protection control in this expansion status byte defaults to unprotected, then the device should be compatible with DLPC150.

To support flash devices with program protection defaults of either enabled or disabled, the DLPC150 always assumes the device default is enabled and goes through the process of disabling protection as part of the boot-up process. This process consists of:

  • A write enable (WREN) instruction executed to request write enable, followed by
  • A read status register (RDSR) instruction is then executed (repeatedly as needed) to poll the write enable latch (WEL) bit
  • After the write enable latch (WEL) bit is set, a write status register (WRSR) instruction is executed that writes 0 to all 8-bits (this disables all programming protection)

Prior to each program or erase instruction, the DLPC150 issues:

  • A write enable (WREN) instruction to request write enable, followed by
  • A read status register (RDSR) instruction (repeated as needed) to poll the write enable latch (WEL) bit
  • After the write enable latch (WEL) bit is set, the program or erase instruction is executed
  • Note the flash automatically clears the write enable status after each program and erase instruction

The specific instruction OpCode and timing compatibility requirements are listed in Table 8 and Table 7. Note however that DLPC150 does not read the flash’s electronic signature ID and thus cannot automatically adapt protocol and clock rate based on the ID.

Table 6. SPI Flash Instruction Opcode and Access Profile Compatibility Requirements

Fast READ (1 Output) 0x0B ADDRS(0) ADDRS(1) ADDRS(2) dummy DATA(0)(1)
Read status 0x05 n/a n/a STATUS(0)
Write status 0x01 STATUS(0)  (2)
Write enable 0x06
Page program 0x02 ADDRS(0) ADDRS(1) ADDRS(2) DATA(0)(1)
Sector erase (4KB) 0x20 ADDRS(0) ADDRS(1) ADDRS(2)
Chip erase 0xC7
Only the first data byte is show, data continues for the duration of the read.
DLPC150 does not support access to a second/ expansion Write Status byte.

The specific and timing compatibility requirements for a DLPC150 compatible flash are listed in Table 7 and Table 8.

Table 7. SPI Flash Key Timing Parameter Compatibility Requirements(1)(2)

Access frequency
(all commands)
FR fC ≤1.42 MHz
Chip select high time (also called chip select deselect time) tSHSL tCSH ≤200 ns
Output hold time tCLQX tHO ≥0 ns
Clock low to output valid time tCLQV tV ≤ 11 ns
Data in set-up time tDVCH tDSU ≤5 ns
Data in hold time tCHDX tDH ≤5 ns
The timing values are related to the specification of the flash device itself, not the DLPC150.
The DLPC150 does not drive the HOLD or WP (active low write protect) pins on the flash device, and thus these pins should be tied to a logic high on the PCB through an external pullup.

The DLPC150 supports 1.8-, 2.5-, or 3.3-V serial flash devices. To do so, VCC_FLSH must be supplied with the corresponding voltage. Table 8 contains a list of 1.8-, 2.5-, and 3.3-V compatible SPI serial flash devices supported by DLPC150.

Table 8. DLPC150 Verified Compatible SPI Flash Device Options(1)(2)

1.8-V Compatible Devices
4 Mb Winbond W25Q40BWUXIG 2 × 3 mm USON
4 Mb Macronix MX25U4033EBAI-12G 1.43 × 1.94 mm WLCSP
4 Mb Macronix MX25U4033EBAI-12G 1.68 × 1.99 mm WLCSP
2.5- or 3.3-V Compatible Devices
16 Mb Winbond W25Q16CLZPIG 5 × 6 mm WSON
64 Mb Winbond W25Q64FVZPIG 5 × 6 mm WSON
The flash supply voltage must match VCC_FLSH on the DLPC150. Special attention needs to be paid when ordering devices to be sure the desired supply voltage is attained as multiple voltage options are often available under the same base part number.
Beware when considering Numonyx (Micron) serial flash devices as they typically do not have the 4KB sector size needed to be DLPC150 compatible.