DLPS048C March   2015  – June 2019 DLPC150

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      DLP 0.2-Inch WVGA Chipset
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
    2. 5.1 DLPC150 Mechanical Data
      1. Table 1. I/O Type Subscript Definition
      2. Table 2. Internal Pullup and Pulldown Characteristics
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics Over Recommended Operating Conditions
    6. 6.6  Electrical Characteristics
    7. 6.7  High-Speed Sub-LVDS Electrical Characteristics
    8. 6.8  Low-Speed SDR Electrical Characteristics
    9. 6.9  System Oscillators Timing Requirements
    10. 6.10 Power-Up and Reset Timing Requirements
    11. 6.11 Parallel Interface Frame Timing Requirements
    12. 6.12 Parallel Interface General Timing Requirements
    13. 6.13 Flash Interface Timing Requirements
  7. 7 Parameter Measurement Information
    1. 7.1 Host_irq Usage Model
    2. 7.2 Input Source
      1. 7.2.1 Parallel Interface Supports Two Data Transfer Formats
        1. 7.2.1.1 Pdata Bus – Parallel Interface Bit Mapping Modes
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Interface Timing Requirements
        1. 8.3.1.1 Parallel Interface
      2. 8.3.2 Serial Flash Interface
      3. 8.3.3 Serial Flash Programming
      4. 8.3.4 I2C Control Interface
      5. 8.3.5 DMD (Sub-LVDS) Interface
      6. 8.3.6 Calibration And Debug Support
      7. 8.3.7 DMD Interface Considerations
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 DLPC150 System Design Consideration – Application Notes
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 DLPC150 System Interfaces
          1. 9.2.2.1.1 Control Interface
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 System Power-Up and Power-Down Sequence
    2. 10.2 DLPC150 Power-Up Initialization Sequence
    3. 10.3 DMD Fast Park Control (PARKZ)
    4. 10.4 Hot Plug Usage
    5. 10.5 Maximum Signal Transition Time
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 PCB Layout Guidelines For Internal Controller PLL Power
      2. 11.1.2 DLPC150 Reference Clock
        1. 11.1.2.1 Recommended Crystal Oscillator Configuration
      3. 11.1.3 General PCB Recommendations
      4. 11.1.4 General Handling Guidelines for Unused CMOS-Type Pins
      5. 11.1.5 Maximum Pin-to-Pin, PCB Interconnects Etch Lengths
      6. 11.1.6 Number of Layer Changes
      7. 11.1.7 Stubs
      8. 11.1.8 Terminations
      9. 11.1.9 Routing Vias
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Device Nomenclature
        1. 12.1.1.1 Device Markings
    2. 12.2 Related Links
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Package Option Addendum
      1. 13.1.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)

6.6 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted) (see (1)(2))
PARAMETER(3) TEST CONDITIONS MIN TYP MAX UNIT
VIH High-level input threshold voltage I2C buffer (I/O type 7) 0.7 × VCC_INTF  (1) V
1.8-V LVTTL (I/O type 1, 2, 3, 5, 6, 8, 9, 11, 12, 13) 1.17 3.6
1.8-V LVTTL (I/O type 1, 6) identified below: (2)
CMP_OUT; PARKZ; RESETZ; GPIO[19:05]; TRIG_OUT_1; TRIG_OUT_2		 1.3 3.6
2.5-V LVTTL (I/O type 5, 9, 11, 12, 13) 1.7 3.6
3.3-V LVTTL (I/O type 5, 9, 11, 12, 13) 2 3.6
VIL Low-level input threshold voltage I2C buffer (I/O type 7) –0.5 0.3 × VCC_INTF V
1.8-V LVTTL (I/O type 1, 2, 3, 5, 6, 8, 9, 11, 12, 13) –0.3 0.63
1.8-V LVTTL (I/O type 1, 6) identified below: (2)
CMP_OUT; PARKZ; RESETZ; GPIO[19:05]; TRIG_OUT_1; TRIG_OUT_2		 –0.3 0.5
2.5-V LVTTL (I/O type 5, 9, 11, 12, 13) –0.3 0.7
3.3-V LVTTL (I/O type 5, 9, 11, 12, 13) –0.3 0.8
VCM Steady-state common mode voltage 1.8 sub-LVDS (DMD high speed)
(I/O type 4)		 800 900 1000 mV
ǀVODǀ Differential output magnitude 1.8 sub-LVDS (DMD high speed)
(I/O type 4)		 200 mV
VOH High-level output voltage 1.8-V LVTTL (I/O type 1, 2, 3, 5, 6, 8, 9, 11, 12, 13) 1.35 V
2.5-V LVTTL (I/O type 5, 9, 11, 12, 13) 1.7
3.3-V LVTTL (I/O type 5, 9, 11, 12, 13) 2.4
1.8 sub-LVDS – DMD high speed (I/O type 4) 1
VOL Low-level output voltage I2C buffer (I/O type 7) VCC_INTF > 2 V 0.4 V
I2C buffer (I/O type 7) VCC_INTF < 2 V 0.2 × VCC_INTF
1.8-V LVTTL (I/O type 1, 2, 3, 5, 6, 8, 9, 11, 12, 13) 0.45
2.5 V LVTTL (I/O type 5, 9, 11, 12, 13) 0.7
3.3 V LVTTL (I/O type 5, 9, 11, 12, 13) 0.4
1.8 sub-LVDS – DMD high speed (I/O type 4) 0.8
IOH High-level output current 1.8-V LVTTL (I/O type 1, 2, 3, 5, 6, 8, 9, 11, 12, 13) 4 mA 2 mA
1.8-V LVTTL (I/O type 1, 2, 3, 5, 6, 8, 9, 11, 12, 13) 8 mA 3.5
1.8-V LVTTL (I/O type 1, 2, 3, 5, 6, 8, 9, 11, 12, 13) 24 mA 10.6
2.5-V LVTTL (I/O type 5) 4 mA 5.4
2.5-V LVTTL (I/O type 9, 13) 8 mA 10.8
2.5-V LVTTL (I/O type 5, 9, 11, 12, 13) 24 mA 28.7
3.3-V LVTTL (I/O type 5 ) 4 mA 7.8
3.3-V LVTTL (I/O type 9, 13) 8 mA 15
IOL Low-level output current I2C buffer (I/O type 7) 3 mA
1.8-V LVTTL (I/O type 1, 2, 3, 5, 6, 8, 9, 11, 12, 13) 4 mA 2.3
1.8-V LVTTL (I/O type 1, 2, 3, 5, 6, 8, 9, 11, 12, 13) 8 mA 4.6
1.8-V LVTTL (I/O type 1, 2, 3, 5, 6, 8, 9, 11, 12, 13) 24 mA 13.9
2.5-V LVTTL (I/O type 5) 4 mA 5.2
2.5-V LVTTL (I/O type 9, 13) 8 mA 10.4
2.5-V LVTTL (I/O type 5, 9, 11, 12, 13) 24 mA 31.1
3.3-V LVTTL (I/O type 5 ) 4 mA 4.4
3.3-V LVTTL (I/O type 9, 13) 8 mA 8.9
IOZ High-impedance leakage current I2C buffer (I/O type 7) 0.1 × VCC_INTF < VI
< 0.9 × VCC_INTF		 –10 10 µA
1.8-V LVTTL (I/O type 1, 2, 3, 5, 6, 8, 9, 11, 12, 13) –10 10
2.5-V LVTTL (I/O type 5, 9, 11, 12, 13) –10 10
3.3-V LVTTL (I/O type 5, 9, 11, 12, 13) –10 10
CI Input capacitance (including package) I2C buffer (I/O type 7) 5 pF
1.8-V LVTTL (I/O type 1, 2, 3, 5, 6, 8, 9, 11, 12, 13) 2.6 3.5
2.5-V LVTTL (I/O type 5, 9, 11, 12, 13) 2.6 3.5
3.3-V LVTTL (I/O type 5, 9, 11, 12, 13) 2.6 3.5
1.8 sub-LVDS – DMD high speed (I/O type 4) 3
(1) I/O is high voltage tolerant; that is, if VCC = 1.8 V, the input is 3.3-V tolerant, and if VCC = 3.3 V, the input is 5-V tolerant.
(2) DLPC150 controller pins: CMP_OUT; PARKZ; RESETZ; GPIO[19:05]; TRIG_OUT_1; TRIG_OUT_2 have slightly varied VIH and VIL range from other 1.8-V I/O.
(3) The number inside each parenthesis for the I/O refers to the type defined in Table 1.