DLPS156E january   2019  – april 2023 DLPC3436

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1. 5.1 Test Pins and General Control
    2. 5.2 Parallel Port Input
    3. 5.3 DSI Input Data and Clock
    4. 5.4 DMD Reset and Bias Control
    5. 5.5 DMD Sub-LVDS Interface
    6. 5.6 Peripheral Interface
    7. 5.7 GPIO Peripheral Interface
    8. 5.8 Clock and PLL Support
    9. 5.9 Power and Ground
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Electrical Characteristics
    6. 6.6  Pin Electrical Characteristics
    7. 6.7  Internal Pullup and Pulldown Electrical Characteristics
    8. 6.8  DMD Sub-LVDS Interface Electrical Characteristics
    9. 6.9  DMD Low-Speed Interface Electrical Characteristics
    10. 6.10 System Oscillator Timing Requirements
    11. 6.11 Power Supply and Reset Timing Requirements
    12. 6.12 Parallel Interface Frame Timing Requirements
    13. 6.13 Parallel Interface General Timing Requirements
    14. 6.14 Flash Interface Timing Requirements
    15. 6.15 Other Timing Requirements
    16. 6.16 DMD Sub-LVDS Interface Switching Characteristics
    17. 6.17 DMD Parking Switching Characteristics
    18. 6.18 Chipset Component Usage Specification
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Source Requirements
        1. 7.3.1.1 Input Frame Rates and 3-D Display Operation
          1. 7.3.1.1.1 Parallel Interface Data Transfer Format
        2. 7.3.1.2 3D Display
      2. 7.3.2 Device Startup
      3. 7.3.3 SPI Flash
        1. 7.3.3.1 SPI Flash Interface
        2. 7.3.3.2 SPI Flash Programming
      4. 7.3.4 I2C Interface
      5. 7.3.5 Content Adaptive Illumination Control (CAIC)
      6. 7.3.6 Local Area Brightness Boost (LABB)
      7. 7.3.7 3D Glasses Operation
      8. 7.3.8 Test Point Support
      9. 7.3.9 DMD Interface
        1. 7.3.9.1 Sub-LVDS (HS) Interface
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
    1. 9.1 PLL Design Considerations
    2. 9.2 System Power-Up and Power-Down Sequence
    3. 9.3 Power-Up Initialization Sequence
    4. 9.4 DMD Fast Park Control (PARKZ)
    5. 9.5 Hot Plug I/O Usage
    6. 9.6 Maximum Signal Transition Time
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 PLL Power Layout
      2. 10.1.2 Reference Clock Layout
        1. 10.1.2.1 Recommended Crystal Oscillator Configuration
      3. 10.1.3 Unused Pins
      4. 10.1.4 DMD Control and Sub-LVDS Signals
      5. 10.1.5 Layer Changes
      6. 10.1.6 Stubs
      7. 10.1.7 Terminations
      8. 10.1.8 Routing Vias
      9. 10.1.9 Thermal Considerations
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Device Nomenclature
        1. 11.1.2.1 Device Markings DLPC343x
        2. 11.1.2.2 Device Markings DLPC342x
        3. 11.1.2.3 Video Timing Parameter Definitions
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Related Links
    4. 11.4 Receiving Notification of Documentation Updates
    5. 11.5 Support Resources
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
      1. 12.1.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.1 Test Pins and General Control

PIN I/O TYPE(4) DESCRIPTION
NAME NO.
HWTEST_EN C10 I 6 Manufacturing test enable signal. Connect this signal directly to ground on the PCB for normal operation.
PARKZ C13 I 6 DMD fast park control (active low Input with a hysteresis buffer). This signal is used to quickly park the DMD when loss of power is imminent. The longest lifetime of the DMD may not be achieved with the fast park operation; therefore, this signal is intended to only be asserted when a normal park operation is unable to be completed. The PARKZ signal is typically provided from the DLPAxxxx interrupt output signal.
JTAGTCK P12 I 6 TI internal use. Leave this pin unconnected.
JTAGTDI P13 I 6 TI internal use. Leave this pin unconnected.
JTAGTDO1 N13(1) O 1 TI internal use. Leave this pin unconnected.
JTAGTDO2 N12(1) O 1 TI internal use. Leave this pin unconnected.
JTAGTMS1 M13 I 6 TI internal use. Leave this pin unconnected.
JTAGTMS2 N11 I 6 TI internal use. Leave this pin unconnected.
JTAGTRSTZ P11 I 6 TI internal use.
This pin must be tied to ground, through an external resistor for normal operation. Failure to tie this pin low during normal operation can cause start up and initialization problems.(2)
RESETZ C11 I 6 Power-on reset (active low input with a hysteresis buffer). Self-configuration starts when a low-to-high transition is detected on RESETZ. All controller power and clocks must be stable before this reset is deasserted. No signals are in their active state while RESETZ is asserted. This pin is typically connected to the RESETZ pin of the DLPA200x or RESET_Z of the DLPA200x.
TSTPT_0 R12 I/O 1 Test pins (includes weak internal pulldown). Pins are tristated while RESETZ is asserted low. Sampled as an input test mode selection control approximately 1.5 µs after deassertion of RESETZ, and then driven as outputs.(2)(3)

Normal use: reserved for test output. Leave open for normal use.
Note: An external pullup may put the DLPC34x36 in a test mode. See Section 7.3.8 for more information.
TSTPT_1 R13 I/O 1
TSTPT_2 R14 I/O 1
TSTPT_3 R15 I/O 1
TSTPT_4 P14 I/O 1
TSTPT_5 P15 I/O 1
TSTPT_6 N14 I/O 1
TSTPT_7 N15 I/O 1
(1) If the application design does not require an external pullup, and there is no external logic that can overcome the weak internal pulldown resistor, then this I/O pin can be left open or unconnected for normal operation. If the application design does not require an external pullup, but there is external logic that might overcome the weak internal pulldown resistor, then an external pulldown is recommended to ensure a logic low.
(2) External resistor must have a value of 8 kΩ or less to compensate for pins that provide internal pullup or pulldown resistors.
(3) If the application design does not require an external pullup and there is no external logic that can overcome the weak internal pulldown, then the TSTPT I/O can be left open (unconnected) for normal operation. If operation does not call for an external pullup, but there is external logic that might overcome the weak internal pulldown resistor, then an external pulldown resistor is recommended to ensure a logic low.
(4) See Table 5-3 for type definitions.