DLPS156F January   2019  – November 2024 DLPC3436

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
    1. 4.1 Test Pins and General Control
    2. 4.2 Parallel Port Input
    3. 4.3 DSI Input Data and Clock
    4. 4.4 DMD Reset and Bias Control
    5. 4.5 DMD SubLVDS Interface
    6. 4.6 Peripheral Interface
    7. 4.7 GPIO Peripheral Interface
    8. 4.8 Clock and PLL Support
    9. 4.9 Power and Ground
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Electrical Characteristics
    6. 5.6  Pin Electrical Characteristics
    7. 5.7  Internal Pullup and Pulldown Electrical Characteristics
    8. 5.8  DMD SubLVDS Interface Electrical Characteristics
    9. 5.9  DMD Low-Speed Interface Electrical Characteristics
    10. 5.10 System Oscillator Timing Requirements
    11. 5.11 Power Supply and Reset Timing Requirements
    12. 5.12 Parallel Interface Frame Timing Requirements
    13. 5.13 Parallel Interface General Timing Requirements
    14. 5.14 Flash Interface Timing Requirements
    15. 5.15 Other Timing Requirements
    16. 5.16 DMD SubLVDS Interface Switching Characteristics
    17. 5.17 DMD Parking Switching Characteristics
    18. 5.18 Chipset Component Usage Specification
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Input Source Requirements
        1. 6.3.1.1 Input Frame Rates and 3-D Display Operation
          1. 6.3.1.1.1 Parallel Interface Data Transfer Format
        2. 6.3.1.2 3D Display
      2. 6.3.2 Device Startup
      3. 6.3.3 SPI Flash
        1. 6.3.3.1 SPI Flash Interface
        2. 6.3.3.2 SPI Flash Programming
      4. 6.3.4 I2C Interface
      5. 6.3.5 Content Adaptive Illumination Control (CAIC)
      6. 6.3.6 Local Area Brightness Boost (LABB)
      7. 6.3.7 3D Glasses Operation
      8. 6.3.8 Test Point Support
      9. 6.3.9 DMD Interface
        1. 6.3.9.1 SubLVDS (HS) Interface
    4. 6.4 Device Functional Modes
    5. 6.5 Programming
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curve
  9. 8 Power Supply Recommendations
    1. 8.1 PLL Design Considerations
    2. 8.2 System Power-Up and Power-Down Sequence
    3. 8.3 Power-Up Initialization Sequence
    4. 8.4 DMD Fast Park Control (PARKZ)
    5. 8.5 Hot Plug I/O Usage
    6. 8.6 Maximum Signal Transition Time
  10. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 PLL Power Layout
      2. 9.1.2 Reference Clock Layout
        1. 9.1.2.1 Recommended Crystal Oscillator Configuration
      3. 9.1.3 Unused Pins
      4. 9.1.4 DMD Control and SubLVDS Signals
      5. 9.1.5 Layer Changes
      6. 9.1.6 Stubs
      7. 9.1.7 Terminations
      8. 9.1.8 Routing Vias
      9. 9.1.9 Thermal Considerations
    2. 9.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 Device Nomenclature
        1. 10.1.2.1 Device Markings DLPC343x
        2. 10.1.2.2 Device Markings DLPC342x
        3. 10.1.2.3 Video Timing Parameter Definitions
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Related Links
    4. 10.4 Receiving Notification of Documentation Updates
    5. 10.5 Support Resources
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
      1. 12.1.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4.1 Test Pins and General Control

PINI/OTYPE(4)DESCRIPTION
NAMENO.
HWTEST_ENC10I6Manufacturing test enable signal. Connect this signal directly to ground on the PCB for normal operation.
PARKZC13I6DMD fast park control (active low Input with a hysteresis buffer). This signal is used to quickly park the DMD when loss of power is imminent. The longest lifetime of the DMD may not be achieved with the fast park operation; therefore, this signal is intended to only be asserted when a normal park operation is unable to be completed. The PARKZ signal is typically provided from the DLPAxxxx interrupt output signal.
JTAGTCKP12I6TI internal use. Leave this pin unconnected.
JTAGTDIP13I6TI internal use. Leave this pin unconnected.
JTAGTDO1N13(1)O1TI internal use. Leave this pin unconnected.
JTAGTDO2N12(1)O1TI internal use. Leave this pin unconnected.
JTAGTMS1M13I6TI internal use. Leave this pin unconnected.
JTAGTMS2N11I6TI internal use. Leave this pin unconnected.
JTAGTRSTZP11I6TI internal use.
This pin must be tied to ground, through an external resistor for normal operation. Failure to tie this pin low during normal operation can cause start up and initialization problems.(2)
RESETZC11I6Power-on reset (active low input with a hysteresis buffer). Self-configuration starts when a low-to-high transition is detected on RESETZ. All controller power and clocks must be stable before this reset is deasserted. No signals are in their active state while RESETZ is asserted. This pin is typically connected to the RESETZ pin of the DLPA200x or RESET_Z of the DLPA200x.
TSTPT_0R12I/O1Test pins (includes weak internal pulldown). Pins are tristated while RESETZ is asserted low. Sampled as an input test mode selection control approximately 1.5µs after deassertion of RESETZ, and then driven as outputs.(2)(3)

Normal use: reserved for test output. Leave open for normal use.
Note: An external pullup may put the DLPC34x36 in a test mode. See Section 6.3.8 for more information.
TSTPT_1R13I/O1
TSTPT_2R14I/O1
TSTPT_3R15I/O1
TSTPT_4P14I/O1
TSTPT_5P15I/O1
TSTPT_6N14I/O1
TSTPT_7N15I/O1
(1) If the application design does not require an external pullup, and there is no external logic that can overcome the weak internal pulldown resistor, then this I/O pin can be left open or unconnected for normal operation. If the application design does not require an external pullup, but there is external logic that might overcome the weak internal pulldown resistor, then use an external pulldown to maintain a logic low.
(2) External resistors must have a value of 8kΩ or less to compensate for pins that provide internal pullup or pulldown resistors.
(3) If the application design does not require an external pullup and there is no external logic that can overcome the weak internal pulldown, then the TSTPT I/O can be left open (unconnected) for normal operation. If the operation does not call for an external pullup, but there is external logic that might overcome the weak internal pulldown resistor, then use an external pulldown resistor to maintain a logic low.
(4) See Table 4-3 for type definitions.