DLPS156E january   2019  – april 2023 DLPC3436

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1. 5.1 Test Pins and General Control
    2. 5.2 Parallel Port Input
    3. 5.3 DSI Input Data and Clock
    4. 5.4 DMD Reset and Bias Control
    5. 5.5 DMD Sub-LVDS Interface
    6. 5.6 Peripheral Interface
    7. 5.7 GPIO Peripheral Interface
    8. 5.8 Clock and PLL Support
    9. 5.9 Power and Ground
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Electrical Characteristics
    6. 6.6  Pin Electrical Characteristics
    7. 6.7  Internal Pullup and Pulldown Electrical Characteristics
    8. 6.8  DMD Sub-LVDS Interface Electrical Characteristics
    9. 6.9  DMD Low-Speed Interface Electrical Characteristics
    10. 6.10 System Oscillator Timing Requirements
    11. 6.11 Power Supply and Reset Timing Requirements
    12. 6.12 Parallel Interface Frame Timing Requirements
    13. 6.13 Parallel Interface General Timing Requirements
    14. 6.14 Flash Interface Timing Requirements
    15. 6.15 Other Timing Requirements
    16. 6.16 DMD Sub-LVDS Interface Switching Characteristics
    17. 6.17 DMD Parking Switching Characteristics
    18. 6.18 Chipset Component Usage Specification
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Source Requirements
        1. 7.3.1.1 Input Frame Rates and 3-D Display Operation
          1. 7.3.1.1.1 Parallel Interface Data Transfer Format
        2. 7.3.1.2 3D Display
      2. 7.3.2 Device Startup
      3. 7.3.3 SPI Flash
        1. 7.3.3.1 SPI Flash Interface
        2. 7.3.3.2 SPI Flash Programming
      4. 7.3.4 I2C Interface
      5. 7.3.5 Content Adaptive Illumination Control (CAIC)
      6. 7.3.6 Local Area Brightness Boost (LABB)
      7. 7.3.7 3D Glasses Operation
      8. 7.3.8 Test Point Support
      9. 7.3.9 DMD Interface
        1. 7.3.9.1 Sub-LVDS (HS) Interface
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
    1. 9.1 PLL Design Considerations
    2. 9.2 System Power-Up and Power-Down Sequence
    3. 9.3 Power-Up Initialization Sequence
    4. 9.4 DMD Fast Park Control (PARKZ)
    5. 9.5 Hot Plug I/O Usage
    6. 9.6 Maximum Signal Transition Time
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 PLL Power Layout
      2. 10.1.2 Reference Clock Layout
        1. 10.1.2.1 Recommended Crystal Oscillator Configuration
      3. 10.1.3 Unused Pins
      4. 10.1.4 DMD Control and Sub-LVDS Signals
      5. 10.1.5 Layer Changes
      6. 10.1.6 Stubs
      7. 10.1.7 Terminations
      8. 10.1.8 Routing Vias
      9. 10.1.9 Thermal Considerations
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Device Nomenclature
        1. 11.1.2.1 Device Markings DLPC343x
        2. 11.1.2.2 Device Markings DLPC342x
        3. 11.1.2.3 Video Timing Parameter Definitions
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Related Links
    4. 11.4 Receiving Notification of Documentation Updates
    5. 11.5 Support Resources
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
      1. 12.1.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.3.1 SPI Flash Interface

The DLPC34x6 controller requires an external SPI serial flash memory device to store the firmware. Follow the below guidelines and requirements in addition to the requirements listed in the Flash Interface Timing Requirements section.

The controller supports a maximum flash size of 128 Mb (16 MB). See Table 7-5 for example compatible flash options. The minimum required flash size depends on the size of the utilized firmware. The firmware size depends upon a variety of factors including the number of sequences, lookup tables, and splash images.

The DLPC34x6 controller uses a single SPI interface that complies to industry standard SPI flash protocol. The device will begin accessing the flash at a nominal 1.42-MHz frequency before running at a nominal 30-MHz rate. The flash device must support these rates.

The controller has two independent SPI chip select (CS) control lines. Ensure the flash device's chip select pin is connected to SPI0_CSZ0 as the controller's boot routine is executed from the device connected to chip select zero. The boot routine uploads program code from flash memory to program memory then transfers control to an auto-initialization routine within program memory.

The DLPC34x6 is designed to support any flash device that is compatible with the modes of operation, features, and performance as defined in Table 7-2, Table 7-3, and Table 7-4.

Table 7-2 Additional DLPC34x6 SPI Flash Requirements
FEATURE DLPC34x6 REQUIREMENT
SPI interface width Single
SPI polarity and phase settings SPI mode 0
Fast READ addressing Auto-incrementing
Programming mode Page mode
Page size 256 B
Sector size 4-KB sector
Block size Any
Block protection bits 0 = Disabled
Status register bit(0) Write in progress (WIP), also called flash busy
Status register bit(1) Write enable latch (WEN)
Status register bits(6:2) A value of 0 disables programming protection
Status register bit(7) Status register write protect (SRWP)
Status register bits(15:8)
(that is expansion status byte)		 Because the DLPC34x6 controller supports only single-byte status register R/W command execution, it may not be compatible with flash devices that contain an expansion status byte. However, as long as the expansion status byte is considered optional in the byte 3 position and any write protection control in this expansion status byte defaults to unprotected, then the flash device is likely compatible with the DLPC34x6.

The DLPC34x6 controller is intended to support flash devices with program protection defaults of either enabled or disabled. The controller assumes the default is enabled and proceeds to disable any program protection as part of the boot process.

The DLPC34x6 issues these commands during the boot process:

  • A write enable (WREN) instruction to request write enable, followed by
  • A read status register (RDSR) instruction (repeated as needed) to poll the write enable latch (WEL) bit
  • After the write enable latch (WEL) bit is set, a write status register (WRSR) instruction that writes 0 to all 8 bits (this disables all programming protection)

Prior to each program or erase instruction, the DLPC34x6 controller issues similar commands:

  • A write enable (WREN) instruction to request write enable, followed by
  • A read status register (RDSR) instruction (repeated as needed) to poll the write enable latch (WEL) bit
  • After the write enable latch (WEL) bit is set, the program or erase instruction

Note that the flash device automatically clears the write enable status after each program and erase instruction.

Table 7-3, and Table 7-4 list the specific instruction OpCode and timing compatibility requirements. The DLPC34x6 controller does not adapt protocol or clock rate based on the flash type connected.

Table 7-3 SPI Flash Instruction OpCode and Access Profile Compatibility Requirements
SPI FLASH COMMAND BYTE 1
(OPCODE)		 BYTE 2 BYTE 3 BYTE 4 BYTE 5 BYTE 6
Fast READ (1 output) 0x0B ADDRS(0) ADDRS(1) ADDRS(2) dummy DATA(0)(1)
Read status 0x05 N/A N/A STATUS(0)
Write status 0x01 STATUS(0) See (2)
Write enable 0x06
Page program 0x02 ADDRS(0) ADDRS(1) ADDRS(2) DATA(0)(1)
Sector erase (4 KB) 0x20 ADDRS(0) ADDRS(1) ADDRS(2)
Chip erase 0xC7
(1) Shows the first data byte only. Data continues.
(2) Access to a second (expansion) write status byte not supported by the DLPC34x6 controller.

Table 7-4 and the Flash Interface Timing Requirements section list the specific timing compatibility requirements for a DLPC34x6 compatible flash device.

Table 7-4 SPI Flash Key Timing Parameter Compatibility Requirements
SPI FLASH TIMING PARAMETER (1) (2) SYMBOL ALTERNATE SYMBOL MIN MAX UNIT
Access frequency (all commands) FR fC ≤ 1.4 ≥ 30.1 MHz
Chip select high time (also called chip select deselect time) tSHSL tCSH ≤ 200 ns
Output hold time tCLQX tHO ≥ 0 ns
Clock low to output valid time tCLQV tV ≤ 11 ns
Data in set-up time tDVCH tDSU ≤ 5 ns
Data in hold time tCHDX tDH ≤ 5 ns

In order for the DLPC34x6 controller to support 1.8-V, 2.5-V, or 3.3-V serial flash devices, the VCC_FLSH pin must be supplied with the corresponding voltage. Table 7-5 contains a list of validated 1.8-V, 2.5-V, or 3.3-V compatible SPI serial flash devices supported by the DLPC34x6 controller.

Table 7-5 DLPC34x6 Compatible SPI Flash Device Options (3.3-V Compatible Devices)(1)
DVT(2)DENSITY (Mb)VENDORPART NUMBERPACKAGE SIZE
Yes32 MbWinbondW25Q32FVSSIG5.2 mm × 7.9 mm, 8-pin SOIC
Yes64 MbWinbondW25Q64FVSSIG5.2 mm × 7.9 mm, 8-pin SOIC
(1) The flash supply voltage must match VCC_FLSH on the DLPC34x6. Special attention needs to be paid when ordering devices to be sure the desired supply voltage is attained as multiple voltage options are often available under the same base part number.
(2) All of the flash devices shown are compatible with the DLPC34x6, but only those marked with yes in the DVT column have been validated during TI validation testing using a TI reference design. Those marked with no can be used at the ODM’s own risk. Other parts than those shown can be used if the timing conditions are met.