The DP83822 also supports Reduced Gigabit Media Independent Interface (RGMII) as specified by RGMII version 2.0. RGMII is designed to reduce the number of pins required to connect the MAC and PHY. To accomplish this goal, the control signals are multiplexed. Both rising and falling edges of the clock are used to sample the control signal pin on the transmit and receive paths. For 10-Mbps operation, RX_CLK and TX_CLK operate at 2.5 MHz. For 100-Mbps operation, RX_CLK and TX_CLK operate at 25 MHz.
The RGMII signals are summarized below:
|Transmit and Receive Signals||TX_CTRL|
During packet reception, RX_CLK may be stretched on either the positive or negative pulse to accommodate the transition from the internal free running clock to a recovered clock (data synchronous). Additionally, when the speed of the PHY changes, a similar clock stretching of the positive or negative pulses is allowed to prevent clock glitches. Data may be duplicated on the falling edge of the clock because double data rate (DDR) is only required for 1-Gbps operation, which is not supported by the DP83822.
The DP83822 supports in-band status indication. To help simplify detection of link status, speed and duplex, the DP83822 provides inter-frame signals on RX_D[3:0] pins as specified in Table 8-5 below.
Note: In-band status only valid when RX_DV is low
1 = Full-Duplex
0 = Half-Duplex
|RX_CLK Clock Speed:|
00 = 2.5-MHz (10 Mbps)
01 = 25-MHz (100 Mbps)
10 = Reserved
11 = Reserved
1 = Valid link established
0 = Link not established