|TX_CLK||2||O, Hi-Z||MII Transmit Clock: MII Transmit Clock provides a 25-MHz reference clock for 100-Mbps speed and a 2.5-MHz reference clock for 10-Mbps speed. Note that in MII mode, this clock has constant phase referenced to the reference clock. Applications requiring such constant phase may use this feature.|
|Hi-Z||Unused in RMII Mode|
|I, PD||RGMII Transmit Clock: The clock is
sourced from the MAC layer to the PHY. When
operating at 100-Mbps speed, this clock must be
25-MHz. When operating at 10-Mbps speed, this
clock must be 2.5-MHz.
Note : When in reset, TX_CLK is an output pin and low value is driven on it. Only once device is out of reset, TX_CLK is configured as input.
|TX_EN / TX_CTRL||3||I, PD||Transmit Enable: TX_EN is presented
on the rising edge of the TX_CLK. TX_EN indicates
the presence of valid data inputs on TX_D[3:0] in
MII mode and on TX_D[1:0] in RMII mode. TX_EN is
an active high signal.
RGMII Transmit Control: TX_CTRL combines transmit enable and transmit error signals. TX_EN is presented on the rising edge of TX_CLK and TX_ER on the falling edge of TX_CLK.
|TX_D0||4||I, PD||Transmit Data: In MII mode, the transmit data nibble received from the MAC is synchronous to the rising edge of TX_CLK. In RMII mode, TX_D[1:0] received from the MAC is synchronous to the rising edge of the reference clock. In RGMII mode, the transmit data nibble received from the MAC is synchronous to the rising edge of TX_CLK.|
|RX_CLK||25||O||MII Receive Clock: MII Receive Clock
provides a 25-MHz reference clock for 100-Mbps
speed and a 2.5-MHz reference clock for 10-Mbps
speed, which is derived from the received data
Unused in RMII Mode
RGMII Receive Clock:RGMII Receive Clock provides a 25-MHz reference clock for 100-Mbps speed and a 2.5-MHz reference clock for 10-Mbps speed, which is derived from the receive data stream.
|RX_DV / RX_CTRL||26||O, S-PD||Receive Data Valid: This pin
indicates valid data is present on the RX_D[3:0]
for MII mode and on RX_D[1:0] in RMII mode,
independent from Carrier Sense.
RGMII Receive Control: RX_CTRL combines receive data valid and receive error signals. RX_DV is presented on the rising edge of RX_CLK and RX_ER on the falling edge of RX_CLK.
|RX_ER||28||O, S-PU||Receive Error: This pin indicates
that an error symbol has been detected within a
received packet in both MII and RMII mode. In MII
mode, RX_ER is asserted high synchronously to the
rising edge of RX_CLK. In RMII mode, RX_ER is
asserted high synchronously to the rising edge of
the reference clock. This pin is not required to
be used by the MAC in MII or RMII because the PHY
is corrupting data on a receive error.
Unused in RGMII Mode
|RX_D0||30||O, S-PD||Receive Data: Symbols received on the cable are decoded and presented on these pins synchronous to the rising edge of RX_CLK. They contain valid data when RX_DV is asserted. A nibble RX_D[3:0] is received in MII and RGMII modes. 2-bits RX_D[1:0] is received in RMII Mode. PHY address pins PHY_AD[4:1] are multiplexed with RX_D[3:0], and are pulled-down. PHY_AD (LSB of the address) is multiplexed with COL on pin 29, and is pulled up. If no external pullup or pulldown is present, the default PHY address is 0x01.|
|RX_D3 / GPIO3||1|
|CRS / CRS_DV||27||O, S-PU||Carrier Sense: In MII mode this pin
is asserted high when the receive or transmit
medium is non-idle.
Carrier Sense / Receive Data Valid: In RMII mode, this pin combines the RMII Carrier and Receive Data Valid indications.
Unused in RGMII Mode
|COL / GPIO2||29||I/O, S-PU||Collision Detect: For Full-Duplex
mode, this pin is always LOW. In Half-Duplex
mode, this pin is asserted HIGH only when both
transmit and receive media are non-idle.
Unused in RMII Mode
|SERIAL MANAGEMENT INTERFACE|
|MDC||20||I||Management Data Clock: Synchronous clock to the MDIO serial management input/output data. This clock may be asynchronous to the MAC transmit and receive clocks. The maximum clock rate is 25 MHz. There is no minimum clock rate.|
|MDIO||19||I/O||Management Data I/O: Bidirectional management data signal that may be sourced by the management station or the PHY. This pin requires a 2.2-kΩ pullup resistor.|
|INT/PWDN||8||I/O, OD||Interrupt / Power Down: Register
access is required for this pin to be configured
either as power down or as an interrupt. The
default function of this pin is power down. When
this pin is configured for a power down function,
an active low signal on this pin places the device
in power-down mode.
When this pin is configured as an interrupt pin, this pin is asserted low when an interrupt condition occurs. The pin has an open-drain output with a weak internal pullup. Some applications may require an external pullup resistor.
|RESET||18||I, PU||RESET: This pin is an active low reset input that initializes or re-initializes all the internal registers of the PHY. Asserting this pin low for at least 10 µs will force a reset process to occur.|
|XI||23||I||Crystal / Oscillator Input
MII reference clock: Reference clock 25-MHz ±100 ppm-tolerance crystal or oscillator input. The device supports either an external crystal resonator connected across pins XI and XO, or an external CMOS-level oscillator connected to pin XI only.
RMII reference clock: Reference clock 50-MHz ±100 ppm-tolerance CMOS-level oscillator in RMII Slave mode. Reference clock 25-MHz ±100 ppm-tolerance crystal or oscillator in RMII Master mode.
RGMII reference clock:Reference clock 25-MHz ±100 ppm-tolerance crystal or oscillator input. The device supports either an external crystal resonator connected across pins XI and XO, or an external CMOS-level oscillator connected to pin XI only.
|XO||22||O||Crystal Output: Reference Clock output. XO pin is used for crystal only. This pin should be left floating when a CMOS-level oscillator is connected to XI.|
|GPIO AND LED INTERFACE|
|LED_0||17||O, S-PU||Mode 1 (Default): LINK Indication,
LED indicates the status of the link. When the
link is good, LED is ON. When the link is down,
LED is OFF.
Mode 2: ACT Indication, LED indicates transmit and receive activity in addition to the status of the link. The LED is ON when link is good. The LED blinks when the transmitter or receiver is active.
|LED_1 / GPIO1||24||I/O, S-PD||Mode 1 (Default): This pin is
Mode 2: SPEED Indication, LED indicates the speed of the link. If speed is 100 Mbps, LED is ON. If speed is 10 Mbps, LED is OFF. External Pull resistors are required when LED is connected to this pin.
GPIO1: This pin can be used as a GPIO when using register access.
Signal Detect: This pin acts as Signal Detect in 100BASE-FX mode and shall be connected with Optical Transceiver. Signal Detect high level will be the VDDIO voltage level.
|COL / GPIO2||29||I/O, S, PU||MII Mode: COL pin can be used to
drive an LED when operating in Full-Duplex mode.
Register access is required for LED
RMII Mode: This pin can be used as an LED when using register access.
RGMII Mode:This pin can be used as an LED when using register access.
GPIO2: This pin can be used as a GPIO when using register access.
|RX_D3 / GPIO3||1||I/O, S-PD||MII Mode: RX_D3 will remain as RX_D3
because it is required for MII mode.
RMII Mode: RX_D3 pin can be configured to drive an LED. Register access is required for LED configuration.
RGMII Mode:RX_D3 will remain as RX_D3 because it is required for RGMII mode.
GPIO3: This pin can be used as a GPIO when using register access.
|MEDIA DEPENDENT INTERFACE|
|TD_M||11||A||Differential Transmit Output (PMD): These differential outputs can be automatically configured to either 10BASE-Te, 100BASE-TX, or 100BASE-FX signaling or forced into a specific signaling mode.|
|RD_M||9||A||Differential Receive Input (PMD): These differential inputs are automatically configured to accept either 10BASE-Te, 100BASE-TX, or 100BASE-FX signaling or forced into a specific signaling mode.|
|POWER AND GROUND PINS|
|VDDIO||21||P||I/O Supply: 3.3 V, 2.5 V, or 1.8 V|
|AVD||14||P||Analog Supply: 3.3 V or 1.8 V|
|RBIAS||16||I||Bias Resistor Connection. A 4.87-kΩ ±1% resistor must be connected from RBIAS to GND.|
|LED_1 / GPIO1||24||I/O, S-PD||This pin can be left floating when not in used. External Pull resistors are required when LED is connected to this pin.|