7.6.76 SOR1_Register Register (Offset = 0x467) [reset = 0x101]
SOR1_Register is shown in Table 88.
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Table 88. SOR1_Register Register Field Descriptions
Bit |
Field |
Type |
Reset |
Description |
15 |
RESERVED |
R |
0x0 |
Reserved
|
14 |
CRS_DV/RX_DV |
|
0x0 |
Reserved
|
13 |
CFG_PHY_AD_1 |
|
0x0 |
Latched Value of PhyAddress[1]
|
12 |
CFG_PHY_AD_0 |
|
0x0 |
Latched Value of PhyAddress[0]
|
11 |
RESERVED |
R |
0x0 |
Reserved
|
10 |
RESERVED |
R |
0x0 |
Reserved
|
9 |
RESERVED |
R |
0x0 |
Reserved
|
8 |
CFG_AMDIX |
|
0x1 |
1 = Auto MDI 0 = Manual MDI
|
7 |
RESERVED |
R |
0x0 |
Reserved
|
6 |
RESERVED |
R |
0x0 |
Reserved
|
5 |
RESERVED |
R |
0x0 |
Reserved
|
4 |
RESERVED |
R |
0x0 |
Reserved
|
3 |
CFG_RMII_Master/Slave |
|
0x0 |
0 = RMII Master : 25MHz clock reference at XI 1 = RMII Slave : 50MHz clock reference at XI
|
2 |
RESERVED |
R |
0x0 |
Reserved
|
1 |
RESERVED |
R |
0x0 |
Reserved
|
0 |
Autonegotiation_enable |
|
0x1 |
1: Auto Neg Enable 0: Auto Neg Disable
|