SPRSP50 December   2019 DRA829V

ADVANCE INFORMATION for pre-production products; subject to change without notice.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. 4.3.1  ADC
        1. 4.3.1.1 MCU Domain
      2. 4.3.2  DDRSS
        1. 4.3.2.1 MAIN Domain
      3. 4.3.3  GPIO
        1. 4.3.3.1 MAIN Domain
        2. 4.3.3.2 WKUP Domain
      4. 4.3.4  I2C
        1. 4.3.4.1 MAIN Domain
        2. 4.3.4.2 MCU Domain
        3. 4.3.4.3 WKUP Domain
      5. 4.3.5  I3C
        1. 4.3.5.1 MAIN Domain
        2. 4.3.5.2 MCU Domain
      6. 4.3.6  MCAN
        1. 4.3.6.1 MAIN Domain
        2. 4.3.6.2 MCU Domain
      7. 4.3.7  MCSPI
        1. 4.3.7.1 MAIN Domain
        2. 4.3.7.2 MCU Domain
      8. 4.3.8  UART
        1. 4.3.8.1 MAIN Domain
        2. 4.3.8.2 MCU Domain
        3. 4.3.8.3 WKUP Domain
      9. 4.3.9  MDIO
        1. 4.3.9.1 MCU Domain
      10. 4.3.10 CPSW2G
        1. 4.3.10.1 MCU Domain
      11. 4.3.11 CPSW9G
        1. 4.3.11.1 MAIN Domain
      12. 4.3.12 ECAP
        1. 4.3.12.1 MAIN Domain
      13. 4.3.13 EQEP
        1. 4.3.13.1 MAIN Domain
      14. 4.3.14 EHRPWM
        1. 4.3.14.1 MAIN Domain
      15. 4.3.15 USB
        1. 4.3.15.1 MAIN Domain
      16. 4.3.16 SERDES
        1. 4.3.16.1 MAIN Domain
      17. 4.3.17 OSPI
        1. 4.3.17.1 MCU Domain
      18. 4.3.18 Hyperbus
        1. 4.3.18.1 MCU Domain
      19. 4.3.19 GPMC
        1. 4.3.19.1 MAIN Domain
      20. 4.3.20 MMC
        1. 4.3.20.1 MAIN Domain
      21. 4.3.21 CPTS
        1. 4.3.21.1 MAIN Domain
      22. 4.3.22 UFS
        1. 4.3.22.1 MAIN Domain
      23. 4.3.23 PRU_ICSSG
        1. 4.3.23.1 MAIN Domain
      24. 4.3.24 MLB
        1. 4.3.24.1 MAIN Domain
      25. 4.3.25 MCASP
        1. 4.3.25.1 MAIN Domain
      26. 4.3.26 DSS
        1. 4.3.26.1 MAIN Domain
      27. 4.3.27 DP
        1. 4.3.27.1 MAIN Domain
      28. 4.3.28 Camera Adaptor Layer (CAL) Subsystem
        1. 4.3.28.1 MAIN Domain
      29. 4.3.29 DSI_TX
        1. 4.3.29.1 MAIN Domain
      30. 4.3.30 VPFE
        1. 4.3.30.1 MAIN Domain
      31. 4.3.31 DMTIMER
        1. 4.3.31.1 MAIN Domain
        2. 4.3.31.2 MCU Domain
      32. 4.3.32 Emulation and Debug
        1. 4.3.32.1 MAIN Domain
      33. 4.3.33 System and Miscellaneous
        1. 4.3.33.1 Boot Mode Configuration
          1. 4.3.33.1.1 MAIN Domain
          2. 4.3.33.1.2 MCU Domain
        2. 4.3.33.2 Clock
          1. 4.3.33.2.1 MAIN Domain
          2. 4.3.33.2.2 WKUP Domain
        3. 4.3.33.3 System
          1. 4.3.33.3.1 MAIN Domain
          2. 4.3.33.3.2 WKUP Domain
        4. 4.3.33.4 EFUSE
      34. 4.3.34 Power Supply
    4. 4.4 Pin Multiplexing
    5. 4.5 Connections for Unused Pins
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
      1. 5.1.1 ESD Ratings
      2. 5.1.2 Power-On-Hour (POH) Limits
      3. 5.1.3 Recommended Operating Conditions
      4. 5.1.4 Operating Performance Points
        1. 5.1.4.1 Core Clock Specifications
      5. 5.1.5 Power Consumption Summary
      6. 5.1.6 Electrical Characteristics
        1. Table 5-3  DDR DC Electrical Characteristics
        2. Table 5-4  I2C OPEN DRAIN DC Electrical Characteristics
        3. Table 5-5  Analog OSC Buffers DC Electrical Characteristics
        4. Table 5-6  UHS-I MMC (8-bit PHY) Buffers DC Electrical Characteristics
        5. Table 5-7  SDIO Buffers DC Electrical Characteristics
        6. Table 5-8  DPHY CSI2 Buffers DC Electrical Characteristics
        7. Table 5-9  Analog ADC DC Electrical Characteristics
        8. Table 5-10 AUXPHY DP Buffers DC Electrical Characteristics
        9. Table 5-11 MLB LVDS Buffers DC Electrical Characteristics
        10. Table 5-12 LVCMOS Buffers DC Electrical Characteristics
        11. 5.1.6.1    USBHS Buffers DC Electrical Characteristics
        12. 5.1.6.2    SERDES Buffers DC Electrical Characteristics
      7. 5.1.7 VPP Specifications for One-Time Programmable (OTP) eFuses
        1. Table 5-13 Recommended Operating Conditions for OTP eFuse Programming
        2. 5.1.7.1    Hardware Requirements
        3. 5.1.7.2    Programming Sequence
        4. 5.1.7.3    Impact to Your Hardware Warranty
      8. 5.1.8 Thermal Resistance Characteristics
        1. 5.1.8.1 Thermal Resistance Characteristics for ALF Package
    2. 5.2 Timing and Switching Characteristics
      1. 5.2.1 Timing Parameters and Information
      2. 5.2.2 Power Supply Sequencing
        1. 5.2.2.1 Power Supply Slew Rate Requirement
        2. 5.2.2.2 Power-Up Sequencing
        3. 5.2.2.3 Power-Down Sequencing
      3. 5.2.3 Reset Timing
        1. 5.2.3.1 Reset Electrical Data/Timing
      4. 5.2.4 Clock Specifications
        1. 5.2.4.1 Input Clocks / Oscillators
          1. 5.2.4.1.1 WKUP_OSC0 Internal Oscillator Clock Source
          2. 5.2.4.1.2 WKUP_OSC0 LVCMOS Digital Clock Source
          3. 5.2.4.1.3 Auxiliary OSC1 Internal Oscillator Clock Source
          4. 5.2.4.1.4 Auxiliary OSC1 LVCMOS Digital Clock Source
          5. 5.2.4.1.5 Auxiliary OSC1 Not Used
          6. 5.2.4.1.6 WKUP_LFOSC0 Internal Oscillator Clock Source
          7. 5.2.4.1.7 WKUP_LFOSC0 Not Used
        2. 5.2.4.2 Output Clocks
        3. 5.2.4.3 PLLs
        4. 5.2.4.4 System Clocks Operating Frequency Ranges
        5. 5.2.4.5 Device Inputs and Outputs Module Clocks Frequencies
        6. 5.2.4.6 Recommended Clock and Control Signal Transition Behavior
        7. 5.2.4.7 Interface Clock Specifications
          1. 5.2.4.7.1 Interface Clock Terminology
          2. 5.2.4.7.2 Interface Clock Frequency
      5. 5.2.5 Peripherals
        1. 5.2.5.1  ATL
          1. Table 5-29 Switching Characteristics Over Recommended Operating Conditions for ATL_CLK[x]
          2. Table 5-30 Timing Requirements for ATL_AWS[x]
          3. Table 5-31 Timing Requirements for ATL_BWS[x]
          4. Table 5-32 Switching Characteristics Over Recommended Operating Conditions for ATCLKOUT[x]
        2. 5.2.5.2  VPFE
        3. 5.2.5.3  CPSW2G
          1. 5.2.5.3.1 CPSW2G MDIO Interface Timings
          2. 5.2.5.3.2 CPSW2G RMII Timings
            1. Table 5-36 Timing Requirements for RMII[x]_REFCLK – RMII Mode
            2. Table 5-37 Timing Requirements for RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RXER – RMII Mode
            3. Table 5-38 Switching Characteristics for RMII[x]_TXD[1:0], and RMII[x]_TXEN – RMII Mode
          3. 5.2.5.3.3 CPSW2G RGMII Timings
            1. Table 5-39 Timing Requirements for RGMII[x]_RCLK – RGMII Mode
            2. Table 5-40 Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL – RGMII Mode
            3. Table 5-41 Switching Characteristics for RGMII[x]_TCLK – RGMII Mode
            4. Table 5-42 Switching Characteristics for RGMII[x]_TD[3:0], and RGMII[x]_TCTL – RGMII Mode
        4. 5.2.5.4  CPSW9G
          1. 5.2.5.4.1 CPSW9G MDIO Interface Timings
          2. 5.2.5.4.2 CPSW9G RMII Timings
            1. Table 5-45 Timing Requirements for RMII[x]_REFCLK – RMII Mode
            2. Table 5-46 Timing Requirements for RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RXER – RMII Mode
            3. Table 5-47 Switching Characteristics for RMII[x]_TXD[1:0], and RMII[x]_TXEN – RMII Mode
          3. 5.2.5.4.3 CPSW9G RGMII Timings
            1. Table 5-48 Timing Requirements for RGMII[x]_RCLK – RGMII Mode
            2. Table 5-49 Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL – RGMII Mode
            3. Table 5-50 Switching Characteristics for RGMII[x]_TCLK – RGMII Mode
            4. Table 5-51 Switching Characteristics for RGMII[x]_TD[3:0], and RGMII[x]_TCTL – RGMII Mode
        5. 5.2.5.5  CSI2
          1. 5.2.5.5.1 CSI-2 MIPI D-PHY
        6. 5.2.5.6  DDRSS
        7. 5.2.5.7  DSS
        8. 5.2.5.8  eCAP
          1. Table 5-55 Timing Requirements for eCAP
          2. Table 5-56 Switching Characteristics for eCAP
        9. 5.2.5.9  eHRPWM
          1. Table 5-57 Timing Requirements for eHRPWM
          2. Table 5-58 Switching Characteristics for eHRPWM
        10. 5.2.5.10 eQEP
          1. Table 5-59 Timing Requirements for eQEP
          2. Table 5-60 Switching Characteristics for eQEP
        11. 5.2.5.11 GPIO
          1. Table 5-61 GPIO Timing Requirements
          2. Table 5-62 GPIO Switching Characteristics
        12. 5.2.5.12 GPMC
          1. 5.2.5.12.1 GPMC and NOR Flash — Synchronous Mode
            1. Table 5-63 GPMC and NOR Flash Timing Requirements — Synchronous Mode
            2. Table 5-64 GPMC and NOR Flash Switching Characteristics – Synchronous Mode
          2. 5.2.5.12.2 GPMC and NOR Flash — Asynchronous Mode
            1. Table 5-65 GPMC and NOR Flash Timing Requirements – Asynchronous Mode
            2. Table 5-66 GPMC and NOR Flash Switching Characteristics – Asynchronous Mode
          3. 5.2.5.12.3 GPMC and NAND Flash — Asynchronous Mode
            1. Table 5-67 GPMC and NAND Flash Timing Requirements – Asynchronous Mode
            2. Table 5-68 GPMC and NAND Flash Switching Characteristics – Asynchronous Mode
        13. 5.2.5.13 HyperBus
          1. Table 5-69 Timing Requirements for HyperBus Initialization
          2. Table 5-70 HyperBus 166 MHz Switching Characteristics
          3. Table 5-71 HyperBus 100 MHz Switching Characteristics
        14. 5.2.5.14 I2C
          1. Table 5-72 Timing Requirements for I2C Input Timings
          2. Table 5-74 Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings
        15. 5.2.5.15 I3C
        16. 5.2.5.16 MCAN
        17. 5.2.5.17 MCASP
          1. Table 5-79 Timing Requirements for MCASP
        18. 5.2.5.18 MLB
        19. 5.2.5.19 MCSPI
          1. 5.2.5.19.1 MCSPI — Master Mode
            1. Table 5-81 Timing Requirements for SPI – Master Mode
          2. 5.2.5.19.2 MCSPI — Slave Mode
            1. Table 5-82 Timing Requirements for SPI – Slave Mode
        20. 5.2.5.20 eMMC/SD/SDIO
          1. 5.2.5.20.1 MMCSD0 - eMMC Interface
            1. 5.2.5.20.1.1 Standard SDR Mode
              1. Table 5-83 Timing Requirements for MMCSD0 – Default Speed Mode
              2. Table 5-84 Switching Characteristics for MMCSD0 – Default Speed Mode
            2. 5.2.5.20.1.2 High Speed SDR Mode
              1. Table 5-85 Timing Requirements for MMCSD0 – High Speed SDR Mode
              2. Table 5-86 Switching Characteristics for MMC0 – JC64 High Speed SDR Mode
            3. 5.2.5.20.1.3 High Speed DDR Mode
              1. Table 5-87 Timing Requirements for MMCSD0 – High Speed DDR Mode
              2. Table 5-88 Switching Characteristics for MMCSD0 – High Speed DDR Mode
            4. 5.2.5.20.1.4 HS200 Mode
              1. Table 5-89 Switching Characteristics for MMCSD0 – HS200 Mode
            5. 5.2.5.20.1.5 HS400 Mode
              1. Table 5-90 Switching Characteristics for MMCSD0 – HS400 Mode
          2. 5.2.5.20.2 MMCSDi — MMCSD1 and MMCSD2 — SD/SDIO Interface
            1. 5.2.5.20.2.1 Default speed Mode
            2. 5.2.5.20.2.2 High Speed Mode
            3. 5.2.5.20.2.3 UHS–I SDR12 Mode
            4. 5.2.5.20.2.4 UHS–I SDR25 Mode
            5. 5.2.5.20.2.5 UHS–I SDR50 Mode
            6. 5.2.5.20.2.6 UHS–I DDR50 Mode
        21. 5.2.5.21 NAVSS
          1. Table 5-104 Timing Requirements for CPTS Input
          2. Table 5-105 Switching Characteristics for CPTS Output
        22. 5.2.5.22 OSPI
          1. 5.2.5.22.1 OSPI With Data Training
            1. Table 5-106 OSPI Switching Characteristics – Data Training
          2. 5.2.5.22.2 OSPI Without Data Training
            1. Table 5-107 OSPI Switching Characteristics – DDR Mode
            2. Table 5-108 OSPI Switching Characteristics – SDR Mode
            3. Table 5-109 OSPI Timing Requirements – DDR Mode
            4. Table 5-110 OSPI Timing Requirements – SDR Mode
        23. 5.2.5.23 OLDI
          1. Table 5-112 OLDI Switching Characteristics
        24. 5.2.5.24 PCIE
        25. 5.2.5.25 PRU_ICSSG
          1. 5.2.5.25.1 Programmable Real-Time Unit (PRU_ICSSG PRU)
            1. 5.2.5.25.1.1 PRU_ICSSG PRU Direct Input/Output Mode Electrical Data and Timing
              1. Table 5-113 PRU_ICSSG PRU Timing Requirements – Direct Input Mode
              2. Table 5-114 PRU_ICSSG PRU Switching Characteristics – Direct Output Mode
            2. 5.2.5.25.1.2 PRU_ICSSG PRU Parallel Capture Mode Electrical Data and Timing
              1. Table 5-115 PRU_ICSSG PRU Timing Requirements – Parallel Capture Mode
            3. 5.2.5.25.1.3 PRU_ICSSG PRU Shift Mode Electrical Data and Timing
              1. Table 5-116 PRU_ICSSG PRU Timing Requirements – Shift In Mode
              2. Table 5-117 PRU_ICSSG PRU Switching Characteristics – Shift Out Mode
            4. 5.2.5.25.1.4 PRU_ICSSG PRU Sigma Delta and Peripheral Interface Modes Electrical Data and Timing
              1. Table 5-118 PRU_ICSSG PRU Timing Requirements – Sigma Delta Mode
              2. Table 5-119 PRU_ICSSG PRU Timing Requirements – Peripheral Interface Mode
              3. Table 5-120 PRU_ICSSG PRU Switching Characteristics – Peripheral Interface Mode
          2. 5.2.5.25.2 PRU_ICSSG Pulse Width Modulation (PWM)
            1. 5.2.5.25.2.1 PRU_ICSSG PWM Electrical Data and Timing
              1. Table 5-121 PRU_ICSSG PWM Switching Characteristics
          3. 5.2.5.25.3 PRU_ICSSG Industrial Ethernet Peripheral (PRU_ICSSG IEP)
            1. 5.2.5.25.3.1 PRU_ICSSG IEP Electrical Data and Timing
              1. Table 5-122 PRU_ICSSG IEP Timing Requirements – Input Validated with SYNC
              2. Table 5-123 PRU_ICSSG IEP Timing Requirements – Digital IOs
              3. Table 5-124 PRU_ICSSG IEP Timing Requirements – LATCH_INx
          4. 5.2.5.25.4 PRU_ICSSG Universal Asynchronous Receiver Transmitter (PRU_ICSSG UART)
            1. 5.2.5.25.4.1 PRU_ICSSG UART Electrical Data and Timing
              1. Table 5-125 PRU_ICSSG UART Timing Requirements
              2. Table 5-126 PRU_ICSSG UART Switching Characteristics
          5. 5.2.5.25.5 PRU_ICSSG Enhanced Capture Peripheral (PRU_ICSSG ECAP)
            1. 5.2.5.25.5.1 PRU_ICSSG ECAP Electrical Data and Timing
              1. Table 5-127 PRU_ICSSG ECAP Timing Requirements
              2. Table 5-128 PRU_ICSSG ECAP Switching Characteristics
          6. 5.2.5.25.6 PRU_ICSSG RGMII, MII_RT, and Switch
            1. 5.2.5.25.6.1 PRU_ICSSG MDIO Electrical Data and Timing
              1. Table 5-129 PRU_ICSSG MDIO Timing Requirements – MDIO_DATA
              2. Table 5-130 PRU_ICSSG MDIO Switching Characteristics – MDIO_CLK
              3. Table 5-131 PRU_ICSSG MDIO Switching Characteristics – MDIO_DATA
            2. 5.2.5.25.6.2 PRU_ICSSG RGMII Electrical Data and Timing
              1. Table 5-132 PRU_ICSSG RGMII Timing Requirements – RGMII_RCLK
              2. Table 5-133 PRU_ICSSG RGMII Timing Requirements – RGMII_RD[3:0] and RGMII_RCTL
              3. Table 5-134 PRU_ICSSG RGMII Switching Characteristics – RGMII_TCLK
              4. Table 5-135 PRU_ICSSG RGMII Switching Characteristics – RGMII_TD[3:0] and RGMII_TCTL
            3. 5.2.5.25.6.3 PRU_ICSSG MII_RT Electrical Data and Timing
              1. Table 5-136 PRU_ICSSG MII_RT Timing Requirements – MII_RXCLK
              2. Table 5-137 PRU_ICSSG MII_RT Timing Requirements – MII_TXCLK
              3. Table 5-138 PRU_ICSSG MII_RT Timing Requirements – MII_RXD[3:0], MII_RXDV, and MII_RXER
              4. Table 5-139 PRU_ICSSG MII_RT Switching Characteristics – MII_TXD[3:0] and MII_TXEN
        26. 5.2.5.26 Timers
          1. Table 5-140 Timing Requirements for Timers
          2. Table 5-141 Switching Characteristics for Timers
        27. 5.2.5.27 UART
          1. Table 5-142 Timing Requirements for UART
          2. Table 5-143 Switching Characteristics Over Recommended Operating Conditions for UART
        28. 5.2.5.28 USB
      6. 5.2.6 Emulation and Debug
        1. 5.2.6.1 Debug Trace
        2. 5.2.6.2 IEEE 1149.1 Standard–Test–Access Port (JTAG)
          1. 5.2.6.2.1 JTAG Electrical Data and Timing
            1. Table 5-145 Timing Requirements for IEEE 1149.1 JTAG
            2. Table 5-146 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
  6. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 Processor Subsystems
      1. 6.2.1 Arm Cortex-A72
      2. 6.2.2 Arm Cortex-R5F
    3. 6.3 Accelerators and Coprocessors
      1. 6.3.1 PRU_ICSSG
        1. 6.3.1.1 PRU_ICSSG PRU Cores
        2. 6.3.1.2 PRU_ICSSG Broadside Accelerators
        3. 6.3.1.3 PRU_ICSSG Local INTC
        4. 6.3.1.4 PRU_ICSSG UART Module
        5. 6.3.1.5 PRU_ICSSG ECAP Module
        6. 6.3.1.6 PRU_ICSSG PWM Module
        7. 6.3.1.7 PRU_ICSSG MII_G_RT Module
        8. 6.3.1.8 PRU_ICSSG MII MDIO Module
        9. 6.3.1.9 PRU_ICSSG IEP
    4. 6.4 Other Subsystems
      1. 6.4.1 MSMC
      2. 6.4.2 NAVSS
        1. 6.4.2.1 NAVSS0
        2. 6.4.2.2 MCU_NAVSS
      3. 6.4.3 PDMA Controller
      4. 6.4.4 Peripherals
        1. 6.4.4.1  ADC
        2. 6.4.4.2  ATL
        3. 6.4.4.3  AASRC
        4. 6.4.4.4  CSI
          1. 6.4.4.4.1 Camera Streaming Interface Receiver (CSI_RX_IF) and MIPI DPHY Receiver (DPHY_RX)
          2. 6.4.4.4.2 Camera Streaming Interface Transmitter (CSI_TX_IF)
        5. 6.4.4.5  CPSW2G
        6. 6.4.4.6  CPSW9G
        7. 6.4.4.7  DCC
        8. 6.4.4.8  DDRSS
        9. 6.4.4.9  DSS
          1. 6.4.4.9.1 DSI
          2. 6.4.4.9.2 eDP
        10. 6.4.4.10 VPFE
        11. 6.4.4.11 eCAP
        12. 6.4.4.12 EPWM
        13. 6.4.4.13 ELM
        14. 6.4.4.14 ESM
        15. 6.4.4.15 eQEP
        16. 6.4.4.16 GPIO
        17. 6.4.4.17 GPMC
        18. 6.4.4.18 Hyperbus
        19. 6.4.4.19 I2C
        20. 6.4.4.20 I3C
        21. 6.4.4.21 MCAN
        22. 6.4.4.22 MCASP
        23. 6.4.4.23 MLBSS
        24. 6.4.4.24 MCRC Controller
        25. 6.4.4.25 MCSPI
        26. 6.4.4.26 MMC/SD
        27. 6.4.4.27 OSPI
        28. 6.4.4.28 PCIE
        29. 6.4.4.29 SerDes
        30. 6.4.4.30 WWDT
        31. 6.4.4.31 Timers
        32. 6.4.4.32 UART
        33. 6.4.4.33 USB
        34. 6.4.4.34 UFS
  7. 7Applications, Implementation, and Layout
    1. 7.1 Power Supply Mapping
    2. 7.2 Device Connection and Layout Fundamentals
      1. 7.2.1 Power Supply Decoupling and Bulk Capacitors
        1. 7.2.1.1 Power Distribution Network Implementation Guidance
      2. 7.2.2 External Oscillator
      3. 7.2.3 JTAG and EMU
      4. 7.2.4 Reset
      5. 7.2.5 Unused Pins
      6. 7.2.6 Hardware Design Guide for AM752x/DRA829/TDA4VM Devices
    3. 7.3 Peripheral- and Interface-Specific Design Information
      1. 7.3.1 LPDDR4 Board Design and Layout Guidelines
      2. 7.3.2 OSPI and QSPI Board Design and Layout Guidelines
        1. 7.3.2.1 No Loopback and Internal Pad Loopback
        2. 7.3.2.2 External Board Loopback
        3. 7.3.2.3 DQS (only available in Octal Flash devices)
      3. 7.3.3 USB VBUS Design Guidelines
      4. 7.3.4 System Power Supply Monitor Design Guidelines
      5. 7.3.5 High Speed Differential Signal Routing Guidance
      6. 7.3.6 External Capacitors
      7. 7.3.7 Thermal Solution Guidance
  8. 8Device and Documentation Support
    1. 8.1 Device Nomenclature
      1. 8.1.1 Standard Package Symbolization
      2. 8.1.2 Device Naming Convention
    2. 8.2 Tools and Software
    3. 8.3 Documentation Support
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ALF|827
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Device Overview