SPRSP35J Data sheet

SPRSP35J February 2019 – August 2021 DRA829J , DRA829V

PRODUCTION DATA

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)

ALF|827

Thermal pad, mechanical data (Package|Pins)

Orderable Information

7.10.5.12.1.2 GPMC and NOR Flash Switching Characteristics – Synchronous Mode

NO.⁽²⁾	PARAMETER	DESCRIPTION	MODE⁽¹⁹⁾	MIN	MAX	MIN	MAX	UNIT
NO.⁽²⁾	PARAMETER	DESCRIPTION	MODE⁽¹⁹⁾	100 MHz⁽²³⁾		133 MHz⁽²³⁾		UNIT
F0	tc(clk)	Period, output clock GPMC_CLK⁽¹⁸⁾	div_by_1_mode;	10		7.52		ns
F1	t_w(clkH)	Typical pulse duration, output clock GPMC_CLK high	div_by_1_mode	0.475*P⁽¹⁵⁾- 0.3		0.475*P⁽¹⁵⁾- 0.3		ns
F1	t_w(clkL)	Typical pulse duration, output clock GPMC_CLK low	div_by_1_mode	0.475*P⁽¹⁵⁾- 0.3		0.475*P⁽¹⁵⁾- 0.3		ns
F2	t_d(clkH-csnV)	Delay time, output clock GPMC_CLK rising edge to output chip select GPMC_CSn[i] transition⁽¹⁴⁾	div_by_1_mode no extra_delay	F⁽⁶⁾-2.2	F+3.75	F⁽⁶⁾-2.2	F⁽⁶⁾+3.75	ns
F3	t_{d(clkH-CSn[i]V)}	Delay time, output clock GPMC_CLK rising edge to output chip select GPMC_CSn[i] invalid⁽¹⁴⁾	div_by_1_mode no extra_delay	E⁽⁵⁾-2.2	E⁽⁵⁾+3.75	E⁽⁵⁾-2.2	E⁽⁵⁾+3.75	ns
F4	t_d(aV-clk)	Delay time, output address GPMC_A[27:1] valid to output clock GPMC_CLK first edge	div_by_1_mode	B⁽²⁾-2.3	B⁽²⁾+4.5	B⁽²⁾-2.3	B⁽²⁾+4.5	ns
F5	t_d(clkH-aIV)	Delay time, output clock GPMC_CLK rising edge to output address GPMC_A[27:1] invalid	div_by_1_mode;	-2.3	4.5	-2.3	4.5	ns
F6	t_{d(be[x]nV-clk)}	Delay time, output lower byte enable and command latch enable GPMC_BE0n_CLE, output upper byte enable GPMC_BE1n valid to output clock GPMC_CLK first edge	div_by_1_mode	B⁽²⁾-2.3	B⁽²⁾+1.9	B⁽²⁾-2.3	B⁽²⁾+1.9	ns
F7	t_{d(clkH-be[x]nIV)}	Delay time, output clock GPMC_CLK rising edge to output lower byte enable and command latch enable GPMC_BE0n_CLE, output upper byte enable GPMC_BE1n invalid⁽¹¹⁾	div_by_1_mode	D⁽⁴⁾-2.3	D⁽⁴⁾+1.9	D⁽⁴⁾-2.3	D⁽⁴⁾+1.9	ns
F7	t_{d(clkL-be[x]nIV)}	Delay time, GPMC_CLK falling edge to GPMC_BE0n_CLE, GPMC_BE1n invalid⁽¹²⁾	div_by_1_mode	D⁽⁴⁾-2.3	D⁽⁴⁾+1.9	D⁽⁴⁾-2.3	D⁽⁴⁾+1.9	ns
F7	t_{d(clkL-be[x]nIV).}	Delay time, GPMC_CLK falling edge to GPMC_BE0n_CLE, GPMC_BE1n invalid⁽¹³⁾	div_by_1_mode	D⁽⁴⁾-2.3	D⁽⁴⁾+1.9	D⁽⁴⁾-2.3	D⁽⁴⁾+1.9	ns
F8	t_d(clkH-advn)	Delay time, output clock GPMC_CLK rising edge to output address valid and address latch enable GPMC_ADVn_ALE transition	div_by_1_mode no extra_delay	G⁽⁷⁾-2.3	G⁽⁷⁾+4.5	G⁽⁷⁾-2.3	G⁽⁷⁾+4.5	ns
F9	t_{d(clkH-advnIV)}	Delay time, output clock GPMC_CLK rising edge to output address valid and address latch enable GPMC_ADVn_ALE invalid	div_by_1_mode; no extra_delay	D⁽⁴⁾-2.3	D⁽⁴⁾+4.5	D⁽⁴⁾-2.3	D⁽⁴⁾+4.5	ns
F10	t_d(clkH-oen)	Delay time, output clock GPMC_CLK rising edge to output enable GPMC_OEn_REn transition	div_by_1_mode no extra_delay	H⁽⁸⁾-2.3	H⁽⁸⁾+3.5	H⁽⁸⁾-2.3	H⁽⁸⁾+3.5	ns
F11	t_{d(clkH-oenIV)}	Delay time, output clock GPMC_CLK rising edge to output enable GPMC_OEn_REn invalid	div_by_1_mode no extra_delay	E⁽⁸⁾-2.3	E⁽⁸⁾+3.5	E⁽⁸⁾-2.3	E⁽⁸⁾+ 3.5	ns
F14	t_d(clkH-wen)	Delay time, output clock GPMC_CLK rising edge to output write enable GPMC_WEn transition	div_by_1_mode no extra_delay	I⁽⁹⁾- 2.3	I⁽⁹⁾+4.5	I⁽⁹⁾- 2.3	I⁽⁹⁾+4.5	ns
F15	t_d(clkH-do)	Delay time, output clock GPMC_CLK rising edge to output data GPMC_AD[15:0] transition⁽¹¹⁾	div_by_1_mode	J⁽¹⁰⁾-2.3	J⁽¹⁰⁾+2.7	J⁽¹⁰⁾-2.3	J⁽¹⁰⁾+2.7	ns
F15	t_d(clkL-do)	Delay time, GPMC_CLK falling edge to GPMC_AD[15:0] data bus transition⁽¹²⁾	div_by_1_mode	J⁽¹⁰⁾-2.3	J⁽¹⁰⁾+2.7	J⁽¹⁰⁾-2.3	J⁽¹⁰⁾+2.7	ns
F15	t_d(clkL-do).	Delay time, GPMC_CLK falling edge to GPMC_AD[15:0] data bus transition⁽¹³⁾	div_by_1_mode	J⁽¹⁰⁾-2.3	J⁽¹⁰⁾+2.7	J⁽¹⁰⁾-2.3	J⁽¹⁰⁾+2.7	ns
F17	t_{d(clkH-be[x]n)}	Delay time, output clock GPMC_CLK rising edge to output lower byte enable and command latch enable GPMC_BE0n_CLE transition⁽¹¹⁾	div_by_1_mode	J⁽¹⁰⁾-2.3	J⁽¹⁰⁾+1.9	J⁽¹⁰⁾-2.3	J⁽¹⁰⁾+1.9	ns
F17	t_{d(clkL-be[x]n)}	Delay time, GPMC_CLK falling edge to GPMC_BE0n_CLE, GPMC_BE1n transition⁽¹²⁾	div_by_1_mode	J⁽¹⁰⁾-2.3	J⁽¹⁰⁾+1.9	J⁽¹⁰⁾-2.3	J⁽¹⁰⁾+1.9	ns
F17	t_{d(clkL-be[x]n).}	Delay time, GPMC_CLK falling edge to GPMC_BE0n_CLE, GPMC_BE1n transition⁽¹³⁾	div_by_1_mode	J⁽¹⁰⁾-2.3	J⁽¹⁰⁾+1.9	J⁽¹⁰⁾-2.3	J⁽¹⁰⁾+1.9	ns
F18	t_w(csnV)	Pulse duration, output chip select GPMC_CSn[i] low⁽¹⁴⁾	Read	A⁽¹⁾		A⁽¹⁾		ns
F18	t_w(csnV)	Pulse duration, output chip select GPMC_CSn[i] low⁽¹⁴⁾	Write	A⁽¹⁾		A⁽¹⁾		ns
F19	t_w(be[x]nV)	Pulse duration, output lower byte enable and command latch enable GPMC_BE0n_CLE, output upper byte enable GPMC_BE1n low	Read	C⁽³⁾		C⁽³⁾		ns
F19	t_w(be[x]nV)		Write	C⁽³⁾		C⁽³⁾		ns
F20	t_w(advnV)	Pulse duration, output address valid and address latch enable GPMC_ADVn_ALE low	Read	K⁽¹⁶⁾		K⁽¹⁶⁾		ns
F20	t_w(advnV)		Write	K⁽¹⁶⁾		K⁽¹⁶⁾		ns

(1) For single read: A = (CSRdOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁷⁾
For burst read: A = (CSRdOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁷⁾
For burst write: A = (CSWrOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁷⁾
With n being the page burst access number.

(2) B = ClkActivationTime × GPMC_FCLK⁽¹⁷⁾

(3) For single read: C = RdCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁷⁾
For burst read: C = (RdCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁷⁾
For burst write: C = (WrCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁷⁾
With n being the page burst access number.

(4) For single read: D = (RdCycleTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁷⁾
For burst read: D = (RdCycleTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁷⁾
For burst write: D = (WrCycleTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁷⁾

(5) For single read: E = (CSRdOffTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁷⁾
For burst read: E = (CSRdOffTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁷⁾
For burst write: E = (CSWrOffTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁷⁾

(6) For csn falling edge (CS activated):

Case GPMCFCLKDIVIDER = 0:
- F = 0.5 × CSExtraDelay × GPMC_FCLK⁽¹⁷⁾
Case GPMCFCLKDIVIDER = 1:
- F = 0.5 × CSExtraDelay × GPMC_FCLK⁽¹⁷⁾ if (ClkActivationTime and CSOnTime are odd) or (ClkActivationTime and CSOnTime are even)
- F = (1 + 0.5 × CSExtraDelay) × GPMC_FCLK⁽¹⁷⁾ otherwise
Case GPMCFCLKDIVIDER = 2:
- F = 0.5 × CSExtraDelay × GPMC_FCLK⁽¹⁷⁾ if ((CSOnTime - ClkActivationTime) is a multiple of 3)
- F = (1 + 0.5 × CSExtraDelay) × GPMC_FCLK⁽¹⁷⁾ if ((CSOnTime - ClkActivationTime - 1) is a multiple of 3)
- F = (2 + 0.5 × CSExtraDelay) × GPMC_FCLK⁽¹⁷⁾ if ((CSOnTime - ClkActivationTime - 2) is a multiple of 3)

(7) For ADV falling edge (ADV activated):

Case GPMCFCLKDIVIDER = 0:
- G = 0.5 × ADVExtraDelay × GPMC_FCLK⁽¹⁷⁾
Case GPMCFCLKDIVIDER = 1:
- G = 0.5 × ADVExtraDelay × GPMC_FCLK⁽¹⁷⁾ if (ClkActivationTime and ADVOnTime are odd) or (ClkActivationTime and ADVOnTime are even)
- G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK⁽¹⁷⁾ otherwise
Case GPMCFCLKDIVIDER = 2:
- G = 0.5 × ADVExtraDelay × GPMC_FCLK⁽¹⁷⁾ if ((ADVOnTime - ClkActivationTime) is a multiple of 3)
- G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK⁽¹⁷⁾ if ((ADVOnTime - ClkActivationTime - 1) is a multiple of 3)
- G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK⁽¹⁷⁾ if ((ADVOnTime - ClkActivationTime - 2) is a multiple of 3)

For ADV rising edge (ADV deactivated) in Reading mode:

Case GPMCFCLKDIVIDER = 0:
- G = 0.5 × ADVExtraDelay × GPMC_FCLK⁽¹⁷⁾
Case GPMCFCLKDIVIDER = 1:
- G = 0.5 × ADVExtraDelay × GPMC_FCLK⁽¹⁷⁾ if (ClkActivationTime and ADVRdOffTime are odd) or (ClkActivationTime and ADVRdOffTime are even)
- G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK⁽¹⁷⁾ otherwise
Case GPMCFCLKDIVIDER = 2:
- G = 0.5 × ADVExtraDelay × GPMC_FCLK⁽¹⁷⁾ if ((ADVRdOffTime - ClkActivationTime) is a multiple of 3)
- G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK⁽¹⁷⁾ if ((ADVRdOffTime - ClkActivationTime - 1) is a multiple of 3)
- G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK⁽¹⁷⁾ if ((ADVRdOffTime - ClkActivationTime - 2) is a multiple of 3)

For ADV rising edge (ADV deactivated) in Writing mode:

Case GPMCFCLKDIVIDER = 0:
- G = 0.5 × ADVExtraDelay × GPMC_FCLK⁽¹⁷⁾
Case GPMCFCLKDIVIDER = 1:
- G = 0.5 × ADVExtraDelay × GPMC_FCLK⁽¹⁷⁾ if (ClkActivationTime and ADVWrOffTime are odd) or (ClkActivationTime and ADVWrOffTime are even)
- G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK⁽¹⁷⁾ otherwise
Case GPMCFCLKDIVIDER = 2:
- G = 0.5 × ADVExtraDelay × GPMC_FCLK⁽¹⁷⁾ if ((ADVWrOffTime - ClkActivationTime) is a multiple of 3)
- G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK⁽¹⁷⁾ if ((ADVWrOffTime - ClkActivationTime - 1) is a multiple of 3)
- G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK⁽¹⁷⁾ if ((ADVWrOffTime - ClkActivationTime - 2) is a multiple of 3)

(8) For OE falling edge (OE activated) and IO DIR rising edge (Data Bus input direction):

Case GPMCFCLKDIVIDER = 0:
- H = 0.5 × OEExtraDelay × GPMC_FCLK⁽¹⁷⁾
Case GPMCFCLKDIVIDER = 1:
- H = 0.5 × OEExtraDelay × GPMC_FCLK⁽¹⁷⁾ if (ClkActivationTime and OEOnTime are odd) or (ClkActivationTime and OEOnTime are even)
- H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK⁽¹⁷⁾ otherwise
Case GPMCFCLKDIVIDER = 2:
- H = 0.5 × OEExtraDelay × GPMC_FCLK⁽¹⁷⁾ if ((OEOnTime - ClkActivationTime) is a multiple of 3)
- H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK⁽¹⁷⁾ if ((OEOnTime - ClkActivationTime - 1) is a multiple of 3)
- H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK⁽¹⁷⁾ if ((OEOnTime - ClkActivationTime - 2) is a multiple of 3)

For OE rising edge (OE deactivated):

Case GPMCFCLKDIVIDER = 0:
- H = 0.5 × OEExtraDelay × GPMC_FCLK⁽¹⁷⁾
Case GPMCFCLKDIVIDER = 1:
- H = 0.5 × OEExtraDelay × GPMC_FCLK⁽¹⁷⁾ if (ClkActivationTime and OEOffTime are odd) or (ClkActivationTime and OEOffTime are even)
- H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK⁽¹⁷⁾ otherwise
Case GPMCFCLKDIVIDER = 2:
- H = 0.5 × OEExtraDelay × GPMC_FCLK⁽¹⁷⁾ if ((OEOffTime - ClkActivationTime) is a multiple of 3)
- H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK⁽¹⁷⁾ if ((OEOffTime - ClkActivationTime - 1) is a multiple of 3)
- H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK⁽¹⁷⁾ if ((OEOffTime - ClkActivationTime - 2) is a multiple of 3)

(9) For WE falling edge (WE activated):

Case GPMCFCLKDIVIDER = 0:
- I = 0.5 × WEExtraDelay × GPMC_FCLK⁽¹⁷⁾
Case GPMCFCLKDIVIDER = 1:
- I = 0.5 × WEExtraDelay × GPMC_FCLK⁽¹⁷⁾ if (ClkActivationTime and WEOnTime are odd) or (ClkActivationTime and WEOnTime are even)
- I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK⁽¹⁷⁾ otherwise
Case GPMCFCLKDIVIDER = 2:
- I = 0.5 × WEExtraDelay × GPMC_FCLK⁽¹⁷⁾ if ((WEOnTime - ClkActivationTime) is a multiple of 3)
- I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK⁽¹⁷⁾ if ((WEOnTime - ClkActivationTime - 1) is a multiple of 3)
- I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK⁽¹⁷⁾ if ((WEOnTime - ClkActivationTime - 2) is a multiple of 3)

For WE rising edge (WE deactivated):

Case GPMCFCLKDIVIDER = 0:
- I = 0.5 × WEExtraDelay × GPMC_FCLK ⁽¹⁷⁾
Case GPMCFCLKDIVIDER = 1:
- I = 0.5 × WEExtraDelay × GPMC_FCLK⁽¹⁷⁾ if (ClkActivationTime and WEOffTime are odd) or (ClkActivationTime and WEOffTime are even)
- I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK⁽¹⁷⁾ otherwise
Case GPMCFCLKDIVIDER = 2:
- I = 0.5 × WEExtraDelay × GPMC_FCLK⁽¹⁷⁾ if ((WEOffTime - ClkActivationTime) is a multiple of 3)
- I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK⁽¹⁷⁾ if ((WEOffTime - ClkActivationTime - 1) is a multiple of 3)
- I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK⁽¹⁷⁾ if ((WEOffTime - ClkActivationTime - 2) is a multiple of 3)

(10) J = GPMC_FCLK⁽¹⁷⁾

(11) First transfer only for CLK DIV 1 mode.

(12) Half cycle; for all data after initial transfer for CLK DIV 1 mode.

(13) Half cycle of GPMC_CLKOUT; for all data for modes other than CLK DIV 1 mode. GPMC_CLKOUT divide down from GPMC_FCLK.

(14) In GPMC_CSn[i], i is equal to 0, 1, 2, or 3. In GPMC_WAIT[j], j is equal to 0, 1, 2, or 3.

(15) P = GPMC_CLK period in ns

(16) For read: K = (ADVRdOffTime - ADVOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁷⁾
For write: K = (ADVWrOffTime - ADVOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁷⁾

(17) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.

(18) Related to the GPMC_CLK output clock maximum and minimum frequencies programmable in the GPMC module by setting the GPMC_CONFIG1_i configuration register bit field GPMCFCLKDIVIDER.

(19) For div_by_1_mode:

GPMC_CONFIG1_i register: GPMCFCLKDIVIDER = 0h:
- GPMC_CLK frequency = GPMC_FCLK frequency

For no extra_delay:

GPMC_CONFIG2_i Register: CSEXTRADELAY = 0h = CSn Timing control signal is not delayed
GPMC_CONFIG4_i Register: WEEXTRADELAY = 0h = nWE timing control signal is not delayed
GPMC_CONFIG4_i Register: OEEXTRADELAY = 0h = nOE timing control signal is not delayed
GPMC_CONFIG3_i Register: ADVEXTRADELAY = 0h = nADV timing control signal is not delayed

(23) For 100 MHz: