The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (A_IPROPI). The IPROPI output current can be calculated by Equation 1. The I_LSx in Equation 1 is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of I_LSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs.

The A_ERR parameter in the Electrical Characteristics table is the error associated with the A_IPROPI gain. A_ERR indicates the combined effect of offset error added to the I_OUT current and gain error.

Depending on the application, high accuracy current sense output is required down to 10 mA current. The GAINSEL feature allows optimizing the design for different end applications by reducing OCP limit and increasing current mirror gain at lower motor currents. The current mirror gain A_IPROPI depends on the GAINSEL pin setting, as shown in Table 8-3.

The motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown in Figure 8-5. The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because the current flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again.

Figure 8-5 Integrated Current Sensing

The IPROPI pin is connected to an external resistor (R_IPROPI) to ground to generate a proportional voltage (V_IPROPI) on the IPROPI pin with the I_IPROPI analog current output. This allows for the load current to be measured as the voltage drop across the R_IPROPI resistor with a standard analog to digital converter (ADC). The R_IPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized.

Additionally, the DRV8213 device implements an internal IPROPI voltage clamp circuit to limit V_IPROPI with respect to V_VREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. For the DSG package, V_VREF is set at 510 mV internally. TI recommends designing for at least 1.25 V of headroom between V_VM and the maximum V_IPROPI voltage to be measured by the ADC, V_{IPROPI_MAX}. This maintains good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if V_VM is 4.55 V to 11 V, V_{IPROPI_MAX} can be as high as 3.3 V. However, if V_VM is 3.3 V, then VIPROPI has good accuracy up to 2.05 V.

The corresponding IPROPI voltage to the output current can be calculated by Equation 2.

The IPROPI output bandwidth is limited by the sense delay time (t_DELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready.

If the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the logic tables in 3.7-A Brushed DC Motor Driver with DRV8213 4-A Brushed DC Motor Driver with Integrated Current Sense, Current Regulation and Stall Detection DRV8213 4-A Brushed DC Motor Driver with Integrated Current Sense, Current Regulation and Stall Detection Features Features Applications Applications Description Description Table of Contents Table of Contents Revision History Revision History Device Comparison Device Comparison Pin Configuration and Functions Pin Configuration and Functions Specifications Specifications Absolute Maximum Ratings Absolute Maximum Ratings ESD Ratings ESD Ratings Recommended Operating Conditions Recommended Operating Conditions Thermal Information Thermal Information Electrical Characteristics Electrical Characteristics Timing Diagrams Timing Diagrams Typical Operating Characteristics Typical Operating Characteristics Detailed Description Detailed Description Overview Overview Functional Block Diagram Functional Block Diagram External Components External Components Feature Description Feature Description Bridge Control Bridge Control Current Sense and Regulation (IPROPI) Current Sense and Regulation (IPROPI) Current Sensing and Current Mirror Gain Selection Current Sensing and Current Mirror Gain Selection Current Regulation Current Regulation Hardware Stall Detection Hardware Stall Detection Protection Circuits Protection Circuits Overcurrent Protection (OCP) Overcurrent Protection (OCP) Thermal Shutdown (TSD) Thermal Shutdown (TSD) VM Undervoltage Lockout (UVLO) VM Undervoltage Lockout (UVLO) Device Functional Modes Device Functional Modes Active Mode Active Mode Low-Power Sleep Mode Low-Power Sleep Mode Fault Mode Fault Mode Pin Diagrams Pin Diagrams Logic-Level Inputs Logic-Level Inputs Tri-Level Input Tri-Level Input Application and Implementation Application and Implementation Application Information Application Information Typical Application Typical Application Brushed DC Motor Brushed DC Motor Design Requirements Design Requirements Detailed Design Procedure Detailed Design Procedure Motor Voltage Motor Voltage Motor Current Motor Current Stall Detection Stall Detection Detailed Design Procedure Detailed Design Procedure Hardware Stall Detection Application Description Hardware Stall Detection Application Description Hardware Stall Detection Timing Hardware Stall Detection Timing Hardware Stall Threshold Selection Hardware Stall Threshold Selection Software Stall Detection Application Description Software Stall Detection Application Description Software Stall Detection Timing Software Stall Detection Timing Software Stall Threshold Selection Software Stall Threshold Selection Application Curves Application Curves Thermal Performance Thermal Performance Steady-State Thermal Performance Steady-State Thermal Performance Transient Thermal Performance Transient Thermal Performance Power Supply Recommendations Power Supply Recommendations Bulk Capacitance Bulk Capacitance Layout Layout Layout Guidelines Layout Guidelines Device and Documentation Support Device and Documentation Support Documentation Support Documentation Support Related Documentation Related Documentation Receiving Notification of Documentation Updates Receiving Notification of Documentation Updates Community Resources Community Resources Trademarks Trademarks Mechanical, Packaging, and Orderable Information Mechanical, Packaging, and Orderable Information Tape and Reel Information Tape and Reel Information IMPORTANT NOTICE AND DISCLAIMER IMPORTANT NOTICE AND DISCLAIMER DRV8213 4-A Brushed DC Motor Driver with Integrated Current Sense, Current Regulation and Stall Detection DRV8213 4-A Brushed DC Motor Driver with Integrated Current Sense, Current Regulation and Stall DetectionDRV8213 Features N-channel H-bridge brushed DC motor driver 1.65-V to 11-V operating supply voltage range 240-mΩ RDS(on) (High-Side + Low-Side) High output current capability: 4-A Peak PWM control interface, up to 100 kHz switching Supports 1.8-V, 3.3-V, and 5-V logic inputs Integrated current sensing and current regulation Analog current sense output (IPROPI) Gain select (GAINSEL) feature for - High accuracy current sensing down to 10 mA Optimized RDS(ON) and overcurrent limit for different current ranges Configurable inrush time (RTE Package only) Internal charge pump Long battery life with low-power sleep mode < 60 nA maximum sleep current Small package footprint Integrated protection features VM undervoltage lockout (UVLO) Auto-retry overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection (RTE Package only) Features N-channel H-bridge brushed DC motor driver 1.65-V to 11-V operating supply voltage range 240-mΩ RDS(on) (High-Side + Low-Side) High output current capability: 4-A Peak PWM control interface, up to 100 kHz switching Supports 1.8-V, 3.3-V, and 5-V logic inputs Integrated current sensing and current regulation Analog current sense output (IPROPI) Gain select (GAINSEL) feature for - High accuracy current sensing down to 10 mA Optimized RDS(ON) and overcurrent limit for different current ranges Configurable inrush time (RTE Package only) Internal charge pump Long battery life with low-power sleep mode < 60 nA maximum sleep current Small package footprint Integrated protection features VM undervoltage lockout (UVLO) Auto-retry overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection (RTE Package only) N-channel H-bridge brushed DC motor driver 1.65-V to 11-V operating supply voltage range 240-mΩ RDS(on) (High-Side + Low-Side) High output current capability: 4-A Peak PWM control interface, up to 100 kHz switching Supports 1.8-V, 3.3-V, and 5-V logic inputs Integrated current sensing and current regulation Analog current sense output (IPROPI) Gain select (GAINSEL) feature for - High accuracy current sensing down to 10 mA Optimized RDS(ON) and overcurrent limit for different current ranges Configurable inrush time (RTE Package only) Internal charge pump Long battery life with low-power sleep mode < 60 nA maximum sleep current Small package footprint Integrated protection features VM undervoltage lockout (UVLO) Auto-retry overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection (RTE Package only) N-channel H-bridge brushed DC motor driver 1.65-V to 11-V operating supply voltage range 240-mΩ RDS(on) (High-Side + Low-Side) High output current capability: 4-A Peak PWM control interface, up to 100 kHz switching Supports 1.8-V, 3.3-V, and 5-V logic inputs Integrated current sensing and current regulation Analog current sense output (IPROPI) Gain select (GAINSEL) feature for - High accuracy current sensing down to 10 mA Optimized RDS(ON) and overcurrent limit for different current ranges Configurable inrush time (RTE Package only) Internal charge pump Long battery life with low-power sleep mode < 60 nA maximum sleep current Small package footprint Integrated protection features VM undervoltage lockout (UVLO) Auto-retry overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection (RTE Package only) N-channel H-bridge brushed DC motor driver 1.65-V to 11-V operating supply voltage range1.65-V to 11-V 240-mΩ RDS(on) (High-Side + Low-Side)240-mΩDS(on)High output current capability: 4-A PeakPWM control interface, up to 100 kHz switchingSupports 1.8-V, 3.3-V, and 5-V logic inputsIntegrated current sensing and current regulationAnalog current sense output (IPROPI)IPROPIGain select (GAINSEL) feature for - High accuracy current sensing down to 10 mA Optimized RDS(ON) and overcurrent limit for different current ranges GAINSEL High accuracy current sensing down to 10 mA Optimized RDS(ON) and overcurrent limit for different current ranges High accuracy current sensing down to 10 mA 10 mAOptimized RDS(ON) and overcurrent limit for different current rangesDS(ON)Configurable inrush time (RTE Package only) Internal charge pumpInternalLong battery life with low-power sleep mode < 60 nA maximum sleep current < 60 nA maximum sleep current < 60 nA maximum sleep current< 60 nASmall package footprintIntegrated protection features VM undervoltage lockout (UVLO) Auto-retry overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection (RTE Package only) VM undervoltage lockout (UVLO) Auto-retry overcurrent protection (OCP) Thermal shutdown (TSD) Stall detection (RTE Package only) VM undervoltage lockout (UVLO)Auto-retry overcurrent protection (OCP)Thermal shutdown (TSD) Stall detection (RTE Package only)Stall detection Applications Brushed DC motor, solenoid, & relay driving Water and gas meters Electronic smart lock Electronic and robotic toys Infusion pumps and other portable medical equipments Electric toothbrush Beauty & grooming Portable printers Point-of-sale (POS) devices Other battery powered DC motor applications Applications Brushed DC motor, solenoid, & relay driving Water and gas meters Electronic smart lock Electronic and robotic toys Infusion pumps and other portable medical equipments Electric toothbrush Beauty & grooming Portable printers Point-of-sale (POS) devices Other battery powered DC motor applications Brushed DC motor, solenoid, & relay driving Water and gas meters Electronic smart lock Electronic and robotic toys Infusion pumps and other portable medical equipments Electric toothbrush Beauty & grooming Portable printers Point-of-sale (POS) devices Other battery powered DC motor applications Brushed DC motor, solenoid, & relay driving Water and gas meters Electronic smart lock Electronic and robotic toys Infusion pumps and other portable medical equipments Electric toothbrush Beauty & grooming Portable printers Point-of-sale (POS) devices Other battery powered DC motor applications Brushed DC motor, solenoid, & relay driving Brushed DC motor, solenoid, & relay driving Water and gas meters Watergas meters Electronic smart lock Electronic smart lock Electronic and robotic toys Electronic and robotic toys Infusion pumps and other portable medical equipments Infusion pumps and other portable medical equipments Electric toothbrush Electric toothbrush Beauty & grooming Beauty & grooming Portable printers Portable printers Point-of-sale (POS) devices Point-of-sale (POS) devices Other battery powered DC motor applications Other battery powered DC motor applications Description The DRV8213 is an integrated motor driver with N-channel H-bridge, charge pump, current sense output, current regulation, and protection circuitry. The tripler charge pump allows the device to operate down to 1.65 V to accommodate 1.8-V supply rails and low-battery conditions. The charge pump integrates all capacitors and allows for 100% duty cycle operation. An internal current mirror implements current sensing and regulation. This eliminates the need for a large power shunt resistor, saving board area and reducing system cost. The IPROPI current sense output allows a microcontroller to detect motor stall or changes in load conditions. The gain select (GAINSEL) feature allows high accuracy current sensing down to 10 mA average motor current. Using the VREF pin, this device can regulate the motor current during startup and high-load events without interaction from a microcontroller. The RTE package supports sensorless motor stall detection and reporting to microcontroller. A low-power sleep mode achieves ultra-low quiescent current by shutting down most of the internal circuitry. Internal protection features include undervoltage lockout, overcurrent, and overtemperature. Device Information GUID-1212A970-11DF-4174-809C-3B290CE3D1B1.html#unique_4_Connect_42_DEVINFONOTE PART NUMBER PACKAGE BODY SIZE (NOM) DRV8213DSG WSON (8) 2.00 mm × 2.00 mm DRV8213RTE WQFN (16) 3.00 mm × 3.00 mm For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic (RTE Package) Description The DRV8213 is an integrated motor driver with N-channel H-bridge, charge pump, current sense output, current regulation, and protection circuitry. The tripler charge pump allows the device to operate down to 1.65 V to accommodate 1.8-V supply rails and low-battery conditions. The charge pump integrates all capacitors and allows for 100% duty cycle operation. An internal current mirror implements current sensing and regulation. This eliminates the need for a large power shunt resistor, saving board area and reducing system cost. The IPROPI current sense output allows a microcontroller to detect motor stall or changes in load conditions. The gain select (GAINSEL) feature allows high accuracy current sensing down to 10 mA average motor current. Using the VREF pin, this device can regulate the motor current during startup and high-load events without interaction from a microcontroller. The RTE package supports sensorless motor stall detection and reporting to microcontroller. A low-power sleep mode achieves ultra-low quiescent current by shutting down most of the internal circuitry. Internal protection features include undervoltage lockout, overcurrent, and overtemperature. Device Information GUID-1212A970-11DF-4174-809C-3B290CE3D1B1.html#unique_4_Connect_42_DEVINFONOTE PART NUMBER PACKAGE BODY SIZE (NOM) DRV8213DSG WSON (8) 2.00 mm × 2.00 mm DRV8213RTE WQFN (16) 3.00 mm × 3.00 mm For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic (RTE Package) The DRV8213 is an integrated motor driver with N-channel H-bridge, charge pump, current sense output, current regulation, and protection circuitry. The tripler charge pump allows the device to operate down to 1.65 V to accommodate 1.8-V supply rails and low-battery conditions. The charge pump integrates all capacitors and allows for 100% duty cycle operation. The DRV8213 is an integrated motor driver with N-channel H-bridge, charge pump, current sense output, current regulation, and protection circuitry. The tripler charge pump allows the device to operate down to 1.65 V to accommodate 1.8-V supply rails and low-battery conditions. The charge pump integrates all capacitors and allows for 100% duty cycle operation.DRV8213 An internal current mirror implements current sensing and regulation. This eliminates the need for a large power shunt resistor, saving board area and reducing system cost. The IPROPI current sense output allows a microcontroller to detect motor stall or changes in load conditions. The gain select (GAINSEL) feature allows high accuracy current sensing down to 10 mA average motor current. Using the VREF pin, this device can regulate the motor current during startup and high-load events without interaction from a microcontroller. The RTE package supports sensorless motor stall detection and reporting to microcontroller. An internal current mirror implements current sensing and regulation. This eliminates the need for a large power shunt resistor, saving board area and reducing system cost. The IPROPI current sense output allows a microcontroller to detect motor stall or changes in load conditions. The gain select (GAINSEL) feature allows high accuracy current sensing down to 10 mA average motor current. Using the VREF pin, this device can regulate the motor current during startup and high-load events without interaction from a microcontroller. The RTE package supports sensorless motor stall detection and reporting to microcontroller. A low-power sleep mode achieves ultra-low quiescent current by shutting down most of the internal circuitry. Internal protection features include undervoltage lockout, overcurrent, and overtemperature. A low-power sleep mode achieves ultra-low quiescent current by shutting down most of the internal circuitry. Internal protection features include undervoltage lockout, overcurrent, and overtemperature. Device Information GUID-1212A970-11DF-4174-809C-3B290CE3D1B1.html#unique_4_Connect_42_DEVINFONOTE PART NUMBER PACKAGE BODY SIZE (NOM) DRV8213DSG WSON (8) 2.00 mm × 2.00 mm DRV8213RTE WQFN (16) 3.00 mm × 3.00 mm For all available packages, see the orderable addendum at the end of the data sheet. Device Information GUID-1212A970-11DF-4174-809C-3B290CE3D1B1.html#unique_4_Connect_42_DEVINFONOTE PART NUMBER PACKAGE BODY SIZE (NOM) DRV8213DSG WSON (8) 2.00 mm × 2.00 mm DRV8213RTE WQFN (16) 3.00 mm × 3.00 mm Device Information GUID-1212A970-11DF-4174-809C-3B290CE3D1B1.html#unique_4_Connect_42_DEVINFONOTE #GUID-1212A970-11DF-4174-809C-3B290CE3D1B1/DEVINFONOTE #GUID-1212A970-11DF-4174-809C-3B290CE3D1B1/DEVINFONOTE PART NUMBER PACKAGE BODY SIZE (NOM) DRV8213DSG WSON (8) 2.00 mm × 2.00 mm DRV8213RTE WQFN (16) 3.00 mm × 3.00 mm PART NUMBER PACKAGE BODY SIZE (NOM) PART NUMBER PACKAGE BODY SIZE (NOM) PART NUMBERPACKAGEBODY SIZE (NOM) DRV8213DSG WSON (8) 2.00 mm × 2.00 mm DRV8213RTE WQFN (16) 3.00 mm × 3.00 mm DRV8213DSG WSON (8) 2.00 mm × 2.00 mm DRV8213DSGWSON (8)2.00 mm × 2.00 mm DRV8213RTE WQFN (16) 3.00 mm × 3.00 mm DRV8213RTEWQFN (16)3.00 mm × 3.00 mm For all available packages, see the orderable addendum at the end of the data sheet. For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic (RTE Package) Simplified Schematic (RTE Package) Simplified Schematic (RTE Package) Table of Contents yes Table of Contents yes yes yes Revision History DATE REVISION NOTES * Initial Release Revision History DATE REVISION NOTES * Initial Release DATE REVISION NOTES * Initial Release DATE REVISION NOTES * Initial Release DATE REVISION NOTES * Initial Release DATE REVISION NOTES DATE REVISION NOTES DATEREVISIONNOTES * Initial Release * Initial Release *Initial Release Device Comparison Device Comparison Table Part Number Package Supply (VM, Volts) RDS(on) (mΩ) Current Regulation Current Sense Output Stall Detection Package Size DRV8213 RTE 1.65 to 11 240 Yes Yes Yes 3 mm x 3 mm DRV8213 DSG 1.65 to 11 240 Yes Yes No 2 mm x 2 mm DRV8212/P DSG 1.65 to 11 280 No No No 2 mm x 2 mm DRV8210/P DSG 1.65 to 11 1000 No No No 2 mm x 2 mm DRV8837 DSG 0 to 11 280 No No No 2 mm x 2 mm DRV8837C DSG 0 to 11 1000 No No No 2 mm x 2 mm Device Comparison Device Comparison Table Part Number Package Supply (VM, Volts) RDS(on) (mΩ) Current Regulation Current Sense Output Stall Detection Package Size DRV8213 RTE 1.65 to 11 240 Yes Yes Yes 3 mm x 3 mm DRV8213 DSG 1.65 to 11 240 Yes Yes No 2 mm x 2 mm DRV8212/P DSG 1.65 to 11 280 No No No 2 mm x 2 mm DRV8210/P DSG 1.65 to 11 1000 No No No 2 mm x 2 mm DRV8837 DSG 0 to 11 280 No No No 2 mm x 2 mm DRV8837C DSG 0 to 11 1000 No No No 2 mm x 2 mm Device Comparison Table Part Number Package Supply (VM, Volts) RDS(on) (mΩ) Current Regulation Current Sense Output Stall Detection Package Size DRV8213 RTE 1.65 to 11 240 Yes Yes Yes 3 mm x 3 mm DRV8213 DSG 1.65 to 11 240 Yes Yes No 2 mm x 2 mm DRV8212/P DSG 1.65 to 11 280 No No No 2 mm x 2 mm DRV8210/P DSG 1.65 to 11 1000 No No No 2 mm x 2 mm DRV8837 DSG 0 to 11 280 No No No 2 mm x 2 mm DRV8837C DSG 0 to 11 1000 No No No 2 mm x 2 mm Device Comparison Table Part Number Package Supply (VM, Volts) RDS(on) (mΩ) Current Regulation Current Sense Output Stall Detection Package Size DRV8213 RTE 1.65 to 11 240 Yes Yes Yes 3 mm x 3 mm DRV8213 DSG 1.65 to 11 240 Yes Yes No 2 mm x 2 mm DRV8212/P DSG 1.65 to 11 280 No No No 2 mm x 2 mm DRV8210/P DSG 1.65 to 11 1000 No No No 2 mm x 2 mm DRV8837 DSG 0 to 11 280 No No No 2 mm x 2 mm DRV8837C DSG 0 to 11 1000 No No No 2 mm x 2 mm Device Comparison Table Part Number Package Supply (VM, Volts) RDS(on) (mΩ) Current Regulation Current Sense Output Stall Detection Package Size DRV8213 RTE 1.65 to 11 240 Yes Yes Yes 3 mm x 3 mm DRV8213 DSG 1.65 to 11 240 Yes Yes No 2 mm x 2 mm DRV8212/P DSG 1.65 to 11 280 No No No 2 mm x 2 mm DRV8210/P DSG 1.65 to 11 1000 No No No 2 mm x 2 mm DRV8837 DSG 0 to 11 280 No No No 2 mm x 2 mm DRV8837C DSG 0 to 11 1000 No No No 2 mm x 2 mm Part Number Package Supply (VM, Volts) RDS(on) (mΩ) Current Regulation Current Sense Output Stall Detection Package Size Part Number Package Supply (VM, Volts) RDS(on) (mΩ) Current Regulation Current Sense Output Stall Detection Package Size Part Number Package PackageSupply (VM, Volts)RDS(on) (mΩ)DS(on) Current Regulation Current Regulation Current Sense Output Current Sense OutputStall DetectionPackage Size DRV8213 RTE 1.65 to 11 240 Yes Yes Yes 3 mm x 3 mm DRV8213 DSG 1.65 to 11 240 Yes Yes No 2 mm x 2 mm DRV8212/P DSG 1.65 to 11 280 No No No 2 mm x 2 mm DRV8210/P DSG 1.65 to 11 1000 No No No 2 mm x 2 mm DRV8837 DSG 0 to 11 280 No No No 2 mm x 2 mm DRV8837C DSG 0 to 11 1000 No No No 2 mm x 2 mm DRV8213 RTE 1.65 to 11 240 Yes Yes Yes 3 mm x 3 mm DRV8213 DRV8213RTE1.65 to 11240 Yes Yes Yes Yes Yes Yes3 mm x 3 mm DRV8213 DSG 1.65 to 11 240 Yes Yes No 2 mm x 2 mm DRV8213 DRV8213 DSG DSG1.65 to 11240 Yes Yes Yes Yes Yes Yes No No2 mm x 2 mm DRV8212/P DSG 1.65 to 11 280 No No No 2 mm x 2 mm DRV8212/P DRV8212P DSG DSG1.65 to 11 280 280 No No No No No No2 mm x 2 mm DRV8210/P DSG 1.65 to 11 1000 No No No 2 mm x 2 mm DRV8210/P DRV8210/P DRV8210P DSG DSG 1.65 to 11 1.65 to 11 1000 1000 No No No No No No2 mm x 2 mm DRV8837 DSG 0 to 11 280 No No No 2 mm x 2 mm DRV8837 DRV8837DSG0 to 11280NoNoNo2 mm x 2 mm DRV8837C DSG 0 to 11 1000 No No No 2 mm x 2 mm DRV8837C DRV8837CDSG0 to 111000NoNoNo2 mm x 2 mm Pin Configuration and Functions DSG Package (WSON) Top View RTE Package (WQFN) Top View Pin Functions PIN TYPE DESCRIPTION NAME DSG RTE GND 4 9 PWR Device ground. Connect to system ground. IMODE — 15 I Current regulation mode configuration. Tri-level input. See . IN1 6 13 I Controls the H-bridge output. Has internal pulldown. Logic input. See . IN2 5 12 I Controls the H-bridge output. Has internal pulldown. Logic input. See . IPROPI 8 1 PWR Analog current output proportional to load current. See . nFAULT — 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. Connect to nSTALL pin to reduce number of external components. See . nSTALL — 3 OD Stall detection enable and stall indicator output. Pulled low during a stall condition. Connect an external pullup resistor for open-drain operation. Connect to nFAULT pin to reduce number of external components. Connect to GND to disable stall detection. See . OUT1 2 6 O H-bridge output. Connect directly to the motor or other inductive load. OUT2 3 8 O H-bridge output. Connect directly to the motor or other inductive load. PGND — 7 PWR Device power ground. Connect to system ground. SMODE — 11 I Stall detection response configuration. Tri-level input. See . TINRUSH — 10 O Sets timing for stall detection to ignore motor inrush current. Connect to a ceramic capacitor to system ground. See . VCC — 2 PWR Logic power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor rated for VCC. VM 1 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. VREF — 16 I Analog input to set current regulation and stall detection level. For the DSG package, VREF is internally fixed at 510 mV. For information on current regulation, see . For more information on stall detection, see . GAINSEL 7 14 I Configures IPROPI gain factor depeding on the output current range. Tri-level input. PAD — — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. Pin Configuration and Functions DSG Package (WSON) Top View RTE Package (WQFN) Top View Pin Functions PIN TYPE DESCRIPTION NAME DSG RTE GND 4 9 PWR Device ground. Connect to system ground. IMODE — 15 I Current regulation mode configuration. Tri-level input. See . IN1 6 13 I Controls the H-bridge output. Has internal pulldown. Logic input. See . IN2 5 12 I Controls the H-bridge output. Has internal pulldown. Logic input. See . IPROPI 8 1 PWR Analog current output proportional to load current. See . nFAULT — 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. Connect to nSTALL pin to reduce number of external components. See . nSTALL — 3 OD Stall detection enable and stall indicator output. Pulled low during a stall condition. Connect an external pullup resistor for open-drain operation. Connect to nFAULT pin to reduce number of external components. Connect to GND to disable stall detection. See . OUT1 2 6 O H-bridge output. Connect directly to the motor or other inductive load. OUT2 3 8 O H-bridge output. Connect directly to the motor or other inductive load. PGND — 7 PWR Device power ground. Connect to system ground. SMODE — 11 I Stall detection response configuration. Tri-level input. See . TINRUSH — 10 O Sets timing for stall detection to ignore motor inrush current. Connect to a ceramic capacitor to system ground. See . VCC — 2 PWR Logic power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor rated for VCC. VM 1 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. VREF — 16 I Analog input to set current regulation and stall detection level. For the DSG package, VREF is internally fixed at 510 mV. For information on current regulation, see . For more information on stall detection, see . GAINSEL 7 14 I Configures IPROPI gain factor depeding on the output current range. Tri-level input. PAD — — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. DSG Package (WSON) Top View DSG Package (WSON) Top View DSG Package (WSON) Top View DSG Package (WSON) Top View DSG Package(WSON)Top View RTE Package (WQFN) Top View Pin Functions PIN TYPE DESCRIPTION NAME DSG RTE GND 4 9 PWR Device ground. Connect to system ground. IMODE — 15 I Current regulation mode configuration. Tri-level input. See . IN1 6 13 I Controls the H-bridge output. Has internal pulldown. Logic input. See . IN2 5 12 I Controls the H-bridge output. Has internal pulldown. Logic input. See . IPROPI 8 1 PWR Analog current output proportional to load current. See . nFAULT — 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. Connect to nSTALL pin to reduce number of external components. See . nSTALL — 3 OD Stall detection enable and stall indicator output. Pulled low during a stall condition. Connect an external pullup resistor for open-drain operation. Connect to nFAULT pin to reduce number of external components. Connect to GND to disable stall detection. See . OUT1 2 6 O H-bridge output. Connect directly to the motor or other inductive load. OUT2 3 8 O H-bridge output. Connect directly to the motor or other inductive load. PGND — 7 PWR Device power ground. Connect to system ground. SMODE — 11 I Stall detection response configuration. Tri-level input. See . TINRUSH — 10 O Sets timing for stall detection to ignore motor inrush current. Connect to a ceramic capacitor to system ground. See . VCC — 2 PWR Logic power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor rated for VCC. VM 1 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. VREF — 16 I Analog input to set current regulation and stall detection level. For the DSG package, VREF is internally fixed at 510 mV. For information on current regulation, see . For more information on stall detection, see . GAINSEL 7 14 I Configures IPROPI gain factor depeding on the output current range. Tri-level input. PAD — — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. RTE Package (WQFN) Top View RTE Package (WQFN) Top View RTE Package (WQFN) Top View RTE Package(WQFN)Top View Pin Functions PIN TYPE DESCRIPTION NAME DSG RTE GND 4 9 PWR Device ground. Connect to system ground. IMODE — 15 I Current regulation mode configuration. Tri-level input. See . IN1 6 13 I Controls the H-bridge output. Has internal pulldown. Logic input. See . IN2 5 12 I Controls the H-bridge output. Has internal pulldown. Logic input. See . IPROPI 8 1 PWR Analog current output proportional to load current. See . nFAULT — 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. Connect to nSTALL pin to reduce number of external components. See . nSTALL — 3 OD Stall detection enable and stall indicator output. Pulled low during a stall condition. Connect an external pullup resistor for open-drain operation. Connect to nFAULT pin to reduce number of external components. Connect to GND to disable stall detection. See . OUT1 2 6 O H-bridge output. Connect directly to the motor or other inductive load. OUT2 3 8 O H-bridge output. Connect directly to the motor or other inductive load. PGND — 7 PWR Device power ground. Connect to system ground. SMODE — 11 I Stall detection response configuration. Tri-level input. See . TINRUSH — 10 O Sets timing for stall detection to ignore motor inrush current. Connect to a ceramic capacitor to system ground. See . VCC — 2 PWR Logic power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor rated for VCC. VM 1 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. VREF — 16 I Analog input to set current regulation and stall detection level. For the DSG package, VREF is internally fixed at 510 mV. For information on current regulation, see . For more information on stall detection, see . GAINSEL 7 14 I Configures IPROPI gain factor depeding on the output current range. Tri-level input. PAD — — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. Pin Functions PIN TYPE DESCRIPTION NAME DSG RTE GND 4 9 PWR Device ground. Connect to system ground. IMODE — 15 I Current regulation mode configuration. Tri-level input. See . IN1 6 13 I Controls the H-bridge output. Has internal pulldown. Logic input. See . IN2 5 12 I Controls the H-bridge output. Has internal pulldown. Logic input. See . IPROPI 8 1 PWR Analog current output proportional to load current. See . nFAULT — 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. Connect to nSTALL pin to reduce number of external components. See . nSTALL — 3 OD Stall detection enable and stall indicator output. Pulled low during a stall condition. Connect an external pullup resistor for open-drain operation. Connect to nFAULT pin to reduce number of external components. Connect to GND to disable stall detection. See . OUT1 2 6 O H-bridge output. Connect directly to the motor or other inductive load. OUT2 3 8 O H-bridge output. Connect directly to the motor or other inductive load. PGND — 7 PWR Device power ground. Connect to system ground. SMODE — 11 I Stall detection response configuration. Tri-level input. See . TINRUSH — 10 O Sets timing for stall detection to ignore motor inrush current. Connect to a ceramic capacitor to system ground. See . VCC — 2 PWR Logic power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor rated for VCC. VM 1 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. VREF — 16 I Analog input to set current regulation and stall detection level. For the DSG package, VREF is internally fixed at 510 mV. For information on current regulation, see . For more information on stall detection, see . GAINSEL 7 14 I Configures IPROPI gain factor depeding on the output current range. Tri-level input. PAD — — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. PIN TYPE DESCRIPTION NAME DSG RTE PIN TYPE DESCRIPTION PINTYPEDESCRIPTION NAME DSG RTE NAMEDSGRTE GND 4 9 PWR Device ground. Connect to system ground. IMODE — 15 I Current regulation mode configuration. Tri-level input. See . IN1 6 13 I Controls the H-bridge output. Has internal pulldown. Logic input. See . IN2 5 12 I Controls the H-bridge output. Has internal pulldown. Logic input. See . IPROPI 8 1 PWR Analog current output proportional to load current. See . nFAULT — 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. Connect to nSTALL pin to reduce number of external components. See . nSTALL — 3 OD Stall detection enable and stall indicator output. Pulled low during a stall condition. Connect an external pullup resistor for open-drain operation. Connect to nFAULT pin to reduce number of external components. Connect to GND to disable stall detection. See . OUT1 2 6 O H-bridge output. Connect directly to the motor or other inductive load. OUT2 3 8 O H-bridge output. Connect directly to the motor or other inductive load. PGND — 7 PWR Device power ground. Connect to system ground. SMODE — 11 I Stall detection response configuration. Tri-level input. See . TINRUSH — 10 O Sets timing for stall detection to ignore motor inrush current. Connect to a ceramic capacitor to system ground. See . VCC — 2 PWR Logic power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor rated for VCC. VM 1 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. VREF — 16 I Analog input to set current regulation and stall detection level. For the DSG package, VREF is internally fixed at 510 mV. For information on current regulation, see . For more information on stall detection, see . GAINSEL 7 14 I Configures IPROPI gain factor depeding on the output current range. Tri-level input. PAD — — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. GND 4 9 PWR Device ground. Connect to system ground. GND 4 4 9 9PWRDevice ground. Connect to system ground. IMODE — 15 I Current regulation mode configuration. Tri-level input. See . IMODE—15ICurrent regulation mode configuration. Tri-level input. See . IN1 6 13 I Controls the H-bridge output. Has internal pulldown. Logic input. See . IN1 6 613IControls the H-bridge output. Has internal pulldown. Logic input. See . IN2 5 12 I Controls the H-bridge output. Has internal pulldown. Logic input. See . IN2 5 512IControls the H-bridge output. Has internal pulldown. Logic input. See . IPROPI 8 1 PWR Analog current output proportional to load current. See . IPROPI 8 81PWRAnalog current output proportional to load current. See . nFAULT — 4 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. Connect to nSTALL pin to reduce number of external components. See . nFAULT— 4 4ODFault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. Connect to nSTALL pin to reduce number of external components. See . nSTALL — 3 OD Stall detection enable and stall indicator output. Pulled low during a stall condition. Connect an external pullup resistor for open-drain operation. Connect to nFAULT pin to reduce number of external components. Connect to GND to disable stall detection. See . nSTALL— 3 3ODStall detection enable and stall indicator output. Pulled low during a stall condition. Connect an external pullup resistor for open-drain operation. Connect to nFAULT pin to reduce number of external components. Connect to GND to disable stall detection. See . OUT1 2 6 O H-bridge output. Connect directly to the motor or other inductive load. OUT1 2 26OH-bridge output. Connect directly to the motor or other inductive load. OUT2 3 8 O H-bridge output. Connect directly to the motor or other inductive load. OUT2 3 38OH-bridge output. Connect directly to the motor or other inductive load. PGND — 7 PWR Device power ground. Connect to system ground. PGND—7PWRDevice power ground. Connect to system ground. SMODE — 11 I Stall detection response configuration. Tri-level input. See . SMODE— 11 11IStall detection response configuration. Tri-level input. See . TINRUSH — 10 O Sets timing for stall detection to ignore motor inrush current. Connect to a ceramic capacitor to system ground. See . TINRUSH— 10 10OSets timing for stall detection to ignore motor inrush current. Connect to a ceramic capacitor to system ground. See . VCC — 2 PWR Logic power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor rated for VCC. VCC— 2 2PWRLogic power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor rated for VCC. VM 1 5 PWR Motor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. VM 1 15PWRMotor power supply. Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor as well as sufficient bulk capacitance rated for VM. VREF — 16 I Analog input to set current regulation and stall detection level. For the DSG package, VREF is internally fixed at 510 mV. For information on current regulation, see . For more information on stall detection, see . VREF—16IAnalog input to set current regulation and stall detection level. For the DSG package, VREF is internally fixed at 510 mV. For information on current regulation, see . For more information on stall detection, see . GAINSEL 7 14 I Configures IPROPI gain factor depeding on the output current range. Tri-level input. GAINSEL GAINSEL 7 7 14 14 I I Configures IPROPI gain factor depeding on the output current range. Tri-level input. Configures IPROPI gain factor depeding on the output current range. Tri-level input. PAD — — — Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. PAD———Thermal pad. Connect to board ground. For good thermal dissipation, use large ground planes on multiple layers, and multiple nearby vias connecting those planes. Specifications Absolute Maximum Ratings over operating temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000288937/MD_ABSMAX_FOOTER1_SF1_SF1 MIN MAX UNIT Power supply pin voltage VM -0.5 12 V Logic power supply pin voltage VCC -0.5 5.75 V Power supply transient voltage ramp VM, VCC 0 2 V/µs Voltage difference between ground pins GND, PGND -0.6 0.6 V Logic pin voltage IN1, IN2, GAINSEL, nSLEEP, IMODE, SMODE -0.3 5.75 V Open-drain output pin voltage nFAULT, nSTALL -0.3 5.75 V Timing capacitor current output pin voltage TINRUSH -0.3 VVCC V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Reference input pin voltage VREF 0.3 5.75 V Output pin voltage OUTx -VSD VVM+VSD V Output current OUTx Internally Limited Internally Limited A Ambient temperature, TA –40 125 °C Junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000288925/MD_ESDRATINGS_COMMERCIAL_FOOTER1 ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000288925/MD_ESDRATINGS_COMMERCIAL_FOOTER2 ±500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ± 2000 V may actually have higher performance. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ± 500 V may actually have higher performance. Recommended Operating Conditions over operating temperature range (unless otherwise noted) MIN NOM MAX UNIT VVM Power supply voltage, DSG VM 1.65 11 V VVM Power supply voltage, RTE VM 0 11 V VVCC Power supply voltage, RTE VCC 1.65 5.5 V VIN Logic input voltage IN1, IN2, nSLEEP, IMODE, SMODE, GAINSEL 0 5.5 V fPWM PWM frequency IN1, IN2 0 100 kHz VOD Open drain pullup voltage nFAULT, nSTALL 0 5.5 V IOD Open drain output current nFAULT, nSTALL 0 5 mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000288938/MD_ROC_FOOTER1_SF1_SF2_SF1 Peak output current OUTx 0 4 A IIPROPI Current sense output current IPROPI 0 1 mA VVREF Current limit reference voltage VREF 0 min (3.3, VVM - 1.25) V TA Operating ambient temperature –40 125 °C TJ Operating junction temperature –40 150 °C Power dissipation and thermal limits must be observed Thermal Information THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000288929/MD_THERMAL_2PKG_FOOTER1 DEVICE DEVICE UNIT DSG (WSON) RTE (WQFN) 8 PINS 16 PINS RθJA Junction-to-ambient thermal resistance 65.9 50.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance 75.2 52.0 °C/W RθJB Junction-to-board thermal resistance 28.7 25.5 °C/W ΨJT Junction-to-top characterization parameter 2.0 1.8 °C/W ΨJB Junction-to-board characterization parameter 28.7 25.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 12.0 11.2 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Electrical Characteristics DSG: 1.65 V ≤ VVM ≤ 11 V, RTE: 0 V ≤ VVM ≤ 11 V and 1.65 V ≤ VVCC ≤ 5.5 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted).Typical values are at TJ = 27°C, VVM = 5 V, VVCC = 3.3 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES, DSG (VM) IVMQ VM sleep mode current IN1 = IN2 = 0 V, after waiting tAUTOSLEEP, VVM = 5 V, TJ = 27°C 20 60 nA IVM VM active mode current IN1 = 3.3 V, IN2 = 0 V 1.2 1.9 mA tWAKE Turnon time Sleep mode to active mode delay 250 μs tAUTOSLEEP Autosleep turnoff time Active mode to autosleep mode delay 0.7 1 1.3 ms fVCP Charge pump switching frequency 6000 kHz POWER SUPPLIES, RTE (VM, VCC) IVMQ VM sleep mode current IN1 = IN2 = 0 V, after waiting tAUTOSLEEP, VVM = 5 V, VVCC = 3.3 V, TJ = 27°C 10 20 nA IVM VM active mode current IN1 = 3.3 V, IN2 = 0 V, VVM = 5 V, VVCC = 3.3 V 0.83 1 mA IVCCQ VCC sleep mode current IN1 = IN2 = 0 V, after waiting tAUTOSLEEP, VVM = 5 V, VVCC = 3.3 V, TJ = 27°C 6 12 nA IVCC VCC active mode current IN1 = 3.3 V, IN2 = 0 V, VVM = 5 V, VVCC = 3.3 V 0.46 0.6 mA tWAKE Turnon time Sleep mode to active mode delay 250 μs tAUTOSLEEP Autosleep turnoff time Active mode to autosleep mode delay 0.75 0.9 1.05 ms LOGIC-LEVEL INPUTS (IN1, IN2) VIL Input logic low voltage 0 0.4 V VIH Input logic high voltage 1.45 5.5 V VHYS Input hysteresis 40 mV IIL Input logic low current VI = 0 V -1 1 µA IIH Input logic high current VINx = 5 V 15 35 µA VnSTALL = VCC 40 nA RPD Input pulldown resistance, INx 200 kΩ tDEGLITCH Input logic deglitch, INx 50 ns TRI-LEVEL INPUTS (IMODE, SMODE) VTHYS Tri-level input logic low voltage 0 0.4 V ITIL Tri-level input Hi-Z voltage 0.75 1.05 V ITIZ Tri-level input logic high voltage 1.45 5.5 V RTPD Tri-level pulldown resistance to GND 83 kΩ ITPU Tri-level pullup current to VCC 10.5 µA OPEN-DRAIN OUTPUTS (nFAULT, nSTALL) VOL Output logic low voltage IOD = 5 mA 0.4 V IOZ Output logic high current VOD = VCC -1 1 µA DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A 120 280 mΩ RDS(ON)_LS Low-side MOSFET on resistance, 350mA to 2A GAINSEL = Low 120 260 mΩ RDS(ON)_LS Low-side MOSFET on resistance, 60mA to 350mA GAINSEL = High-Z 460 900 mΩ RDS(ON)_LS Low-side MOSFET on resistance, 10mA to 60mA GAINSEL = High 2100 4000 mΩ VSD Body diode forward voltage IOUTx = -1 A 0.9 V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 70 ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 40 ns tPDR Input high to output high propagation delay Input to OUTx 450 ns tPDF Input low to output low propagation delay Input to OUTx 450 ns tDEAD Output dead time 500 ns CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage SMODE = Open for RTE package and for DSG package 470 510 550 mV AIPROPI_H Current scaling factor GAINSEL = Low 205 µA/A AIPROPI_M Current scaling factor GAINSEL = High-Z 1050 µA/A AIPROPI_L Current scaling factor GAINSEL = High 4900 µA/A AERR_H Current mirror total error, 350 mA to 2 A GAINSEL = Low, VIPROPI ≤ min(VM-1.25 V, 3.3 V), 3.3 V ≤ VVM ≤ 11 V -6 6 % AERR_H Current mirror total error, 350 mA to 2 A GAINSEL = Low, VIPROPI ≤ min(VM-1.25 V, 3.3 V), 1.65 V ≤ VVM ≤ 3.3 V -6 6 % AERR_M Current mirror total error, 60 mA to 350 mA GAINSEL = High-Z, VIPROPI ≤ min(VM-1.25 V, 3.3 V), 3.3 V ≤ VVM ≤ 11 V -6 6 % GAINSEL = High-Z, VIPROPI ≤ min(VM-1.25 V, 3.3 V), 1.65 V ≤ VVM ≤ 3.3 V -6 6 % AERR_L Current mirror total error, 10 mA to 60 mA GAINSEL = High, VIPROPI ≤ min(VM-1.25 V, 3.3 V), 3.3 V ≤ VVM ≤ 11 V -6 6 % GAINSEL = High, VIPROPI ≤ min(VM-1.25 V, 3.3 V), 1.65 V ≤ VVM ≤ 3.3 V -6 6 % tOFF Current regulation off time 20 µs tBLANK Current regulation blanking time 1.8 µs tDELAY Current sense delay time 1.5 µs tDEG Current regulation and stall detection deglitch time 2 µs HARDWARE STALL DETECTION (TINRUSH) VTINRUSH_trip Threshold voltage for setting tINRUSH timing 0.97 1 1.03 V ITINRUSH Current sourced out of the TINRUSH pin Inputs transition to a state other than IN1=IN2=0, VTINRUSH <  VTINRUSH_trip 8 10 12 µA tdischarge TINRUSH capacitor discharge time 0.8 nF ≤ CTINRUSH ≤ 0.8 µF 100 µs tSTALL_RETRY IN1/IN2 = 0/0 duration to recover from Stall (retry type) 350 900 µs PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO), DSG Supply rising 1.65 V Supply falling 1.30 V VUVLO_VCC VCC supply undervoltage lockout (UVLO), RTE Supply rising 1.65 V Supply falling 1.30 V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 150 mV tUVLO Supply undervoltage deglitch time VVM falling (DSG) or VVCC falling (RTE) to OUTx disabled 10 µs IOCP Overcurrent protection trip point, 350mA to 2A 4 A IOCP Overcurrent protection trip point, 60mA to 350mA 0.8 A IOCP Overcurrent protection trip point, 10mA to 60mA 0.16 A tOCP Overcurrent protection deglitch time 4.2 µs tRETRY Fault retry time 1.5 ms TTSD Thermal shutdown temperature 165 175 185 °C THYS Thermal shutdown hysteresis 17 °C Timing Diagrams Input-to-Output Timing Typical Operating Characteristics High-Side MOSFET ON Resistance (DSG Package) Low-Side MOSFET ON Resistance with GAINSEL = Low (DSG Package) Low-Side MOSFET ON Resistance with GAINSEL = High-Z (DSG Package) Low-Side MOSFET ON Resistance with GAINSEL = High (DSG Package) High-Side MOSFET ON Resistance (RTE Package) Low-Side MOSFET ON Resistance with GAINSEL = Low (RTE Package) Low-Side MOSFET ON Resistance with GAINSEL = High-Z (RTE Package) Low-Side MOSFET ON Resistance with GAINSEL = High (RTE Package) Specifications Absolute Maximum Ratings over operating temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000288937/MD_ABSMAX_FOOTER1_SF1_SF1 MIN MAX UNIT Power supply pin voltage VM -0.5 12 V Logic power supply pin voltage VCC -0.5 5.75 V Power supply transient voltage ramp VM, VCC 0 2 V/µs Voltage difference between ground pins GND, PGND -0.6 0.6 V Logic pin voltage IN1, IN2, GAINSEL, nSLEEP, IMODE, SMODE -0.3 5.75 V Open-drain output pin voltage nFAULT, nSTALL -0.3 5.75 V Timing capacitor current output pin voltage TINRUSH -0.3 VVCC V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Reference input pin voltage VREF 0.3 5.75 V Output pin voltage OUTx -VSD VVM+VSD V Output current OUTx Internally Limited Internally Limited A Ambient temperature, TA –40 125 °C Junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Absolute Maximum Ratings over operating temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000288937/MD_ABSMAX_FOOTER1_SF1_SF1 MIN MAX UNIT Power supply pin voltage VM -0.5 12 V Logic power supply pin voltage VCC -0.5 5.75 V Power supply transient voltage ramp VM, VCC 0 2 V/µs Voltage difference between ground pins GND, PGND -0.6 0.6 V Logic pin voltage IN1, IN2, GAINSEL, nSLEEP, IMODE, SMODE -0.3 5.75 V Open-drain output pin voltage nFAULT, nSTALL -0.3 5.75 V Timing capacitor current output pin voltage TINRUSH -0.3 VVCC V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Reference input pin voltage VREF 0.3 5.75 V Output pin voltage OUTx -VSD VVM+VSD V Output current OUTx Internally Limited Internally Limited A Ambient temperature, TA –40 125 °C Junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. over operating temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000288937/MD_ABSMAX_FOOTER1_SF1_SF1 MIN MAX UNIT Power supply pin voltage VM -0.5 12 V Logic power supply pin voltage VCC -0.5 5.75 V Power supply transient voltage ramp VM, VCC 0 2 V/µs Voltage difference between ground pins GND, PGND -0.6 0.6 V Logic pin voltage IN1, IN2, GAINSEL, nSLEEP, IMODE, SMODE -0.3 5.75 V Open-drain output pin voltage nFAULT, nSTALL -0.3 5.75 V Timing capacitor current output pin voltage TINRUSH -0.3 VVCC V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Reference input pin voltage VREF 0.3 5.75 V Output pin voltage OUTx -VSD VVM+VSD V Output current OUTx Internally Limited Internally Limited A Ambient temperature, TA –40 125 °C Junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C over operating temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000288937/MD_ABSMAX_FOOTER1_SF1_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000288937/MD_ABSMAX_FOOTER1_SF1_SF1 MIN MAX UNIT Power supply pin voltage VM -0.5 12 V Logic power supply pin voltage VCC -0.5 5.75 V Power supply transient voltage ramp VM, VCC 0 2 V/µs Voltage difference between ground pins GND, PGND -0.6 0.6 V Logic pin voltage IN1, IN2, GAINSEL, nSLEEP, IMODE, SMODE -0.3 5.75 V Open-drain output pin voltage nFAULT, nSTALL -0.3 5.75 V Timing capacitor current output pin voltage TINRUSH -0.3 VVCC V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Reference input pin voltage VREF 0.3 5.75 V Output pin voltage OUTx -VSD VVM+VSD V Output current OUTx Internally Limited Internally Limited A Ambient temperature, TA –40 125 °C Junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C MIN MAX UNIT MIN MAX UNIT MINMAXUNIT Power supply pin voltage VM -0.5 12 V Logic power supply pin voltage VCC -0.5 5.75 V Power supply transient voltage ramp VM, VCC 0 2 V/µs Voltage difference between ground pins GND, PGND -0.6 0.6 V Logic pin voltage IN1, IN2, GAINSEL, nSLEEP, IMODE, SMODE -0.3 5.75 V Open-drain output pin voltage nFAULT, nSTALL -0.3 5.75 V Timing capacitor current output pin voltage TINRUSH -0.3 VVCC V Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Reference input pin voltage VREF 0.3 5.75 V Output pin voltage OUTx -VSD VVM+VSD V Output current OUTx Internally Limited Internally Limited A Ambient temperature, TA –40 125 °C Junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C Power supply pin voltage VM -0.5 12 V Power supply pin voltageVM-0.512V Logic power supply pin voltage VCC -0.5 5.75 V Logic power supply pin voltageVCC-0.55.75V Power supply transient voltage ramp VM, VCC 0 2 V/µs Power supply transient voltage rampVM, VCC02V/µs Voltage difference between ground pins GND, PGND -0.6 0.6 V Voltage difference between ground pinsGND, PGND-0.60.6V Logic pin voltage IN1, IN2, GAINSEL, nSLEEP, IMODE, SMODE -0.3 5.75 V Logic pin voltageIN1, IN2, GAINSEL, nSLEEP, IMODE, SMODE-0.35.75V Open-drain output pin voltage nFAULT, nSTALL -0.3 5.75 V Open-drain output pin voltagenFAULT, nSTALL-0.35.75V Timing capacitor current output pin voltage TINRUSH -0.3 VVCC V Timing capacitor current output pin voltageTINRUSH-0.3VVCC VCCV Proportional current output pin voltage, VM  ≥ 5.45 V IPROPI -0.3 5.75 V Proportional current output pin voltage, VM  ≥ 5.45 VIPROPI-0.35.75V Proportional current output pin voltage, VM  < 5.45 V -0.3 VVM + 0.3 V Proportional current output pin voltage, VM  < 5.45 V-0.3VVM + 0.3VMV Reference input pin voltage VREF 0.3 5.75 V Reference input pin voltageVREF0.35.75V Output pin voltage OUTx -VSD VVM+VSD V Output pin voltageOUTx-VSD SDVVM+VSD VMSDV Output current OUTx Internally Limited Internally Limited A Output currentOUTxInternally LimitedInternally LimitedA Ambient temperature, TA –40 125 °C Ambient temperature, TA A–40125°C Junction temperature, TJ –40 150 °C Junction temperature, TJ J–40150°C Storage temperature, Tstg –65 150 °C Storage temperature, Tstg stg–65150°C Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.Absolute Maximum RatingRecommended Operating Condition ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000288925/MD_ESDRATINGS_COMMERCIAL_FOOTER1 ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000288925/MD_ESDRATINGS_COMMERCIAL_FOOTER2 ±500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ± 2000 V may actually have higher performance. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ± 500 V may actually have higher performance. ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000288925/MD_ESDRATINGS_COMMERCIAL_FOOTER1 ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000288925/MD_ESDRATINGS_COMMERCIAL_FOOTER2 ±500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ± 2000 V may actually have higher performance. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ± 500 V may actually have higher performance. VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000288925/MD_ESDRATINGS_COMMERCIAL_FOOTER1 ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000288925/MD_ESDRATINGS_COMMERCIAL_FOOTER2 ±500 VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000288925/MD_ESDRATINGS_COMMERCIAL_FOOTER1 ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000288925/MD_ESDRATINGS_COMMERCIAL_FOOTER2 ±500 VALUE UNIT VALUE UNIT VALUEUNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000288925/MD_ESDRATINGS_COMMERCIAL_FOOTER1 ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000288925/MD_ESDRATINGS_COMMERCIAL_FOOTER2 ±500 V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000288925/MD_ESDRATINGS_COMMERCIAL_FOOTER1 ±2000 V V(ESD) (ESD)Electrostatic dischargeHuman body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000288925/MD_ESDRATINGS_COMMERCIAL_FOOTER1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000288925/MD_ESDRATINGS_COMMERCIAL_FOOTER1±2000V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000288925/MD_ESDRATINGS_COMMERCIAL_FOOTER2 ±500 Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000288925/MD_ESDRATINGS_COMMERCIAL_FOOTER2 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000288925/MD_ESDRATINGS_COMMERCIAL_FOOTER2±500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ± 2000 V may actually have higher performance. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ± 500 V may actually have higher performance. JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ± 2000 V may actually have higher performance.JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ± 500 V may actually have higher performance. Recommended Operating Conditions over operating temperature range (unless otherwise noted) MIN NOM MAX UNIT VVM Power supply voltage, DSG VM 1.65 11 V VVM Power supply voltage, RTE VM 0 11 V VVCC Power supply voltage, RTE VCC 1.65 5.5 V VIN Logic input voltage IN1, IN2, nSLEEP, IMODE, SMODE, GAINSEL 0 5.5 V fPWM PWM frequency IN1, IN2 0 100 kHz VOD Open drain pullup voltage nFAULT, nSTALL 0 5.5 V IOD Open drain output current nFAULT, nSTALL 0 5 mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000288938/MD_ROC_FOOTER1_SF1_SF2_SF1 Peak output current OUTx 0 4 A IIPROPI Current sense output current IPROPI 0 1 mA VVREF Current limit reference voltage VREF 0 min (3.3, VVM - 1.25) V TA Operating ambient temperature –40 125 °C TJ Operating junction temperature –40 150 °C Power dissipation and thermal limits must be observed Recommended Operating Conditions over operating temperature range (unless otherwise noted) MIN NOM MAX UNIT VVM Power supply voltage, DSG VM 1.65 11 V VVM Power supply voltage, RTE VM 0 11 V VVCC Power supply voltage, RTE VCC 1.65 5.5 V VIN Logic input voltage IN1, IN2, nSLEEP, IMODE, SMODE, GAINSEL 0 5.5 V fPWM PWM frequency IN1, IN2 0 100 kHz VOD Open drain pullup voltage nFAULT, nSTALL 0 5.5 V IOD Open drain output current nFAULT, nSTALL 0 5 mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000288938/MD_ROC_FOOTER1_SF1_SF2_SF1 Peak output current OUTx 0 4 A IIPROPI Current sense output current IPROPI 0 1 mA VVREF Current limit reference voltage VREF 0 min (3.3, VVM - 1.25) V TA Operating ambient temperature –40 125 °C TJ Operating junction temperature –40 150 °C Power dissipation and thermal limits must be observed over operating temperature range (unless otherwise noted) MIN NOM MAX UNIT VVM Power supply voltage, DSG VM 1.65 11 V VVM Power supply voltage, RTE VM 0 11 V VVCC Power supply voltage, RTE VCC 1.65 5.5 V VIN Logic input voltage IN1, IN2, nSLEEP, IMODE, SMODE, GAINSEL 0 5.5 V fPWM PWM frequency IN1, IN2 0 100 kHz VOD Open drain pullup voltage nFAULT, nSTALL 0 5.5 V IOD Open drain output current nFAULT, nSTALL 0 5 mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000288938/MD_ROC_FOOTER1_SF1_SF2_SF1 Peak output current OUTx 0 4 A IIPROPI Current sense output current IPROPI 0 1 mA VVREF Current limit reference voltage VREF 0 min (3.3, VVM - 1.25) V TA Operating ambient temperature –40 125 °C TJ Operating junction temperature –40 150 °C over operating temperature range (unless otherwise noted) MIN NOM MAX UNIT VVM Power supply voltage, DSG VM 1.65 11 V VVM Power supply voltage, RTE VM 0 11 V VVCC Power supply voltage, RTE VCC 1.65 5.5 V VIN Logic input voltage IN1, IN2, nSLEEP, IMODE, SMODE, GAINSEL 0 5.5 V fPWM PWM frequency IN1, IN2 0 100 kHz VOD Open drain pullup voltage nFAULT, nSTALL 0 5.5 V IOD Open drain output current nFAULT, nSTALL 0 5 mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000288938/MD_ROC_FOOTER1_SF1_SF2_SF1 Peak output current OUTx 0 4 A IIPROPI Current sense output current IPROPI 0 1 mA VVREF Current limit reference voltage VREF 0 min (3.3, VVM - 1.25) V TA Operating ambient temperature –40 125 °C TJ Operating junction temperature –40 150 °C MIN NOM MAX UNIT MIN NOM MAX UNIT MINNOMMAXUNIT VVM Power supply voltage, DSG VM 1.65 11 V VVM Power supply voltage, RTE VM 0 11 V VVCC Power supply voltage, RTE VCC 1.65 5.5 V VIN Logic input voltage IN1, IN2, nSLEEP, IMODE, SMODE, GAINSEL 0 5.5 V fPWM PWM frequency IN1, IN2 0 100 kHz VOD Open drain pullup voltage nFAULT, nSTALL 0 5.5 V IOD Open drain output current nFAULT, nSTALL 0 5 mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000288938/MD_ROC_FOOTER1_SF1_SF2_SF1 Peak output current OUTx 0 4 A IIPROPI Current sense output current IPROPI 0 1 mA VVREF Current limit reference voltage VREF 0 min (3.3, VVM - 1.25) V TA Operating ambient temperature –40 125 °C TJ Operating junction temperature –40 150 °C VVM Power supply voltage, DSG VM 1.65 11 V VVM VMPower supply voltage, DSGVM1.6511V VVM Power supply voltage, RTE VM 0 11 V VVM VMPower supply voltage, RTEVM011V VVCC Power supply voltage, RTE VCC 1.65 5.5 V VVCC VCCPower supply voltage, RTEVCC1.655.5V VIN Logic input voltage IN1, IN2, nSLEEP, IMODE, SMODE, GAINSEL 0 5.5 V VIN INLogic input voltageIN1, IN2, nSLEEP, IMODE, SMODE, GAINSEL 05.5V fPWM PWM frequency IN1, IN2 0 100 kHz fPWM PWMPWM frequencyIN1, IN20100kHz VOD Open drain pullup voltage nFAULT, nSTALL 0 5.5 V VOD ODOpen drain pullup voltagenFAULT, nSTALL05.5V IOD Open drain output current nFAULT, nSTALL 0 5 mA IOD ODOpen drain output currentnFAULT, nSTALL05mA IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000288938/MD_ROC_FOOTER1_SF1_SF2_SF1 Peak output current OUTx 0 4 A IOUT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000288938/MD_ROC_FOOTER1_SF1_SF2_SF1 OUT#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000288938/MD_ROC_FOOTER1_SF1_SF2_SF1Peak output currentOUTx04A IIPROPI Current sense output current IPROPI 0 1 mA IIPROPI IPROPICurrent sense output currentIPROPI01mA VVREF Current limit reference voltage VREF 0 min (3.3, VVM - 1.25) V VVREF VREFCurrent limit reference voltageVREF0min (3.3, VVM - 1.25)VMV TA Operating ambient temperature –40 125 °C TA AOperating ambient temperature–40125°C TJ Operating junction temperature –40 150 °C TJ JOperating junction temperature–40150°C Power dissipation and thermal limits must be observed Power dissipation and thermal limits must be observed Thermal Information THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000288929/MD_THERMAL_2PKG_FOOTER1 DEVICE DEVICE UNIT DSG (WSON) RTE (WQFN) 8 PINS 16 PINS RθJA Junction-to-ambient thermal resistance 65.9 50.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance 75.2 52.0 °C/W RθJB Junction-to-board thermal resistance 28.7 25.5 °C/W ΨJT Junction-to-top characterization parameter 2.0 1.8 °C/W ΨJB Junction-to-board characterization parameter 28.7 25.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 12.0 11.2 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Thermal Information THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000288929/MD_THERMAL_2PKG_FOOTER1 DEVICE DEVICE UNIT DSG (WSON) RTE (WQFN) 8 PINS 16 PINS RθJA Junction-to-ambient thermal resistance 65.9 50.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance 75.2 52.0 °C/W RθJB Junction-to-board thermal resistance 28.7 25.5 °C/W ΨJT Junction-to-top characterization parameter 2.0 1.8 °C/W ΨJB Junction-to-board characterization parameter 28.7 25.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 12.0 11.2 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000288929/MD_THERMAL_2PKG_FOOTER1 DEVICE DEVICE UNIT DSG (WSON) RTE (WQFN) 8 PINS 16 PINS RθJA Junction-to-ambient thermal resistance 65.9 50.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance 75.2 52.0 °C/W RθJB Junction-to-board thermal resistance 28.7 25.5 °C/W ΨJT Junction-to-top characterization parameter 2.0 1.8 °C/W ΨJB Junction-to-board characterization parameter 28.7 25.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 12.0 11.2 °C/W THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000288929/MD_THERMAL_2PKG_FOOTER1 DEVICE DEVICE UNIT DSG (WSON) RTE (WQFN) 8 PINS 16 PINS RθJA Junction-to-ambient thermal resistance 65.9 50.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance 75.2 52.0 °C/W RθJB Junction-to-board thermal resistance 28.7 25.5 °C/W ΨJT Junction-to-top characterization parameter 2.0 1.8 °C/W ΨJB Junction-to-board characterization parameter 28.7 25.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 12.0 11.2 °C/W THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000288929/MD_THERMAL_2PKG_FOOTER1 DEVICE DEVICE UNIT DSG (WSON) RTE (WQFN) 8 PINS 16 PINS THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000288929/MD_THERMAL_2PKG_FOOTER1 DEVICE DEVICE UNIT THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000288929/MD_THERMAL_2PKG_FOOTER1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000288929/MD_THERMAL_2PKG_FOOTER1DEVICEDEVICEUNIT DSG (WSON) RTE (WQFN) DSG (WSON)RTE (WQFN) 8 PINS 16 PINS 8 PINS16 PINS RθJA Junction-to-ambient thermal resistance 65.9 50.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance 75.2 52.0 °C/W RθJB Junction-to-board thermal resistance 28.7 25.5 °C/W ΨJT Junction-to-top characterization parameter 2.0 1.8 °C/W ΨJB Junction-to-board characterization parameter 28.7 25.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 12.0 11.2 °C/W RθJA Junction-to-ambient thermal resistance 65.9 50.7 °C/W RθJA θJA Junction-to-ambient thermal resistance65.950.7°C/W RθJC(top) Junction-to-case (top) thermal resistance 75.2 52.0 °C/W RθJC(top) θJC(top)Junction-to-case (top) thermal resistance75.252.0°C/W RθJB Junction-to-board thermal resistance 28.7 25.5 °C/W RθJB θJBJunction-to-board thermal resistance28.725.5°C/W ΨJT Junction-to-top characterization parameter 2.0 1.8 °C/W ΨJT JTJunction-to-top characterization parameter2.01.8°C/W ΨJB Junction-to-board characterization parameter 28.7 25.4 °C/W ΨJB JBJunction-to-board characterization parameter28.725.4°C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 12.0 11.2 °C/W RθJC(bot) θJC(bot)Junction-to-case (bottom) thermal resistance12.011.2°C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.Semiconductor and IC Package Thermal Metrics Electrical Characteristics DSG: 1.65 V ≤ VVM ≤ 11 V, RTE: 0 V ≤ VVM ≤ 11 V and 1.65 V ≤ VVCC ≤ 5.5 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted).Typical values are at TJ = 27°C, VVM = 5 V, VVCC = 3.3 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES, DSG (VM) IVMQ VM sleep mode current IN1 = IN2 = 0 V, after waiting tAUTOSLEEP, VVM = 5 V, TJ = 27°C 20 60 nA IVM VM active mode current IN1 = 3.3 V, IN2 = 0 V 1.2 1.9 mA tWAKE Turnon time Sleep mode to active mode delay 250 μs tAUTOSLEEP Autosleep turnoff time Active mode to autosleep mode delay 0.7 1 1.3 ms fVCP Charge pump switching frequency 6000 kHz POWER SUPPLIES, RTE (VM, VCC) IVMQ VM sleep mode current IN1 = IN2 = 0 V, after waiting tAUTOSLEEP, VVM = 5 V, VVCC = 3.3 V, TJ = 27°C 10 20 nA IVM VM active mode current IN1 = 3.3 V, IN2 = 0 V, VVM = 5 V, VVCC = 3.3 V 0.83 1 mA IVCCQ VCC sleep mode current IN1 = IN2 = 0 V, after waiting tAUTOSLEEP, VVM = 5 V, VVCC = 3.3 V, TJ = 27°C 6 12 nA IVCC VCC active mode current IN1 = 3.3 V, IN2 = 0 V, VVM = 5 V, VVCC = 3.3 V 0.46 0.6 mA tWAKE Turnon time Sleep mode to active mode delay 250 μs tAUTOSLEEP Autosleep turnoff time Active mode to autosleep mode delay 0.75 0.9 1.05 ms LOGIC-LEVEL INPUTS (IN1, IN2) VIL Input logic low voltage 0 0.4 V VIH Input logic high voltage 1.45 5.5 V VHYS Input hysteresis 40 mV IIL Input logic low current VI = 0 V -1 1 µA IIH Input logic high current VINx = 5 V 15 35 µA VnSTALL = VCC 40 nA RPD Input pulldown resistance, INx 200 kΩ tDEGLITCH Input logic deglitch, INx 50 ns TRI-LEVEL INPUTS (IMODE, SMODE) VTHYS Tri-level input logic low voltage 0 0.4 V ITIL Tri-level input Hi-Z voltage 0.75 1.05 V ITIZ Tri-level input logic high voltage 1.45 5.5 V RTPD Tri-level pulldown resistance to GND 83 kΩ ITPU Tri-level pullup current to VCC 10.5 µA OPEN-DRAIN OUTPUTS (nFAULT, nSTALL) VOL Output logic low voltage IOD = 5 mA 0.4 V IOZ Output logic high current VOD = VCC -1 1 µA DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A 120 280 mΩ RDS(ON)_LS Low-side MOSFET on resistance, 350mA to 2A GAINSEL = Low 120 260 mΩ RDS(ON)_LS Low-side MOSFET on resistance, 60mA to 350mA GAINSEL = High-Z 460 900 mΩ RDS(ON)_LS Low-side MOSFET on resistance, 10mA to 60mA GAINSEL = High 2100 4000 mΩ VSD Body diode forward voltage IOUTx = -1 A 0.9 V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 70 ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 40 ns tPDR Input high to output high propagation delay Input to OUTx 450 ns tPDF Input low to output low propagation delay Input to OUTx 450 ns tDEAD Output dead time 500 ns CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage SMODE = Open for RTE package and for DSG package 470 510 550 mV AIPROPI_H Current scaling factor GAINSEL = Low 205 µA/A AIPROPI_M Current scaling factor GAINSEL = High-Z 1050 µA/A AIPROPI_L Current scaling factor GAINSEL = High 4900 µA/A AERR_H Current mirror total error, 350 mA to 2 A GAINSEL = Low, VIPROPI ≤ min(VM-1.25 V, 3.3 V), 3.3 V ≤ VVM ≤ 11 V -6 6 % AERR_H Current mirror total error, 350 mA to 2 A GAINSEL = Low, VIPROPI ≤ min(VM-1.25 V, 3.3 V), 1.65 V ≤ VVM ≤ 3.3 V -6 6 % AERR_M Current mirror total error, 60 mA to 350 mA GAINSEL = High-Z, VIPROPI ≤ min(VM-1.25 V, 3.3 V), 3.3 V ≤ VVM ≤ 11 V -6 6 % GAINSEL = High-Z, VIPROPI ≤ min(VM-1.25 V, 3.3 V), 1.65 V ≤ VVM ≤ 3.3 V -6 6 % AERR_L Current mirror total error, 10 mA to 60 mA GAINSEL = High, VIPROPI ≤ min(VM-1.25 V, 3.3 V), 3.3 V ≤ VVM ≤ 11 V -6 6 % GAINSEL = High, VIPROPI ≤ min(VM-1.25 V, 3.3 V), 1.65 V ≤ VVM ≤ 3.3 V -6 6 % tOFF Current regulation off time 20 µs tBLANK Current regulation blanking time 1.8 µs tDELAY Current sense delay time 1.5 µs tDEG Current regulation and stall detection deglitch time 2 µs HARDWARE STALL DETECTION (TINRUSH) VTINRUSH_trip Threshold voltage for setting tINRUSH timing 0.97 1 1.03 V ITINRUSH Current sourced out of the TINRUSH pin Inputs transition to a state other than IN1=IN2=0, VTINRUSH <  VTINRUSH_trip 8 10 12 µA tdischarge TINRUSH capacitor discharge time 0.8 nF ≤ CTINRUSH ≤ 0.8 µF 100 µs tSTALL_RETRY IN1/IN2 = 0/0 duration to recover from Stall (retry type) 350 900 µs PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO), DSG Supply rising 1.65 V Supply falling 1.30 V VUVLO_VCC VCC supply undervoltage lockout (UVLO), RTE Supply rising 1.65 V Supply falling 1.30 V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 150 mV tUVLO Supply undervoltage deglitch time VVM falling (DSG) or VVCC falling (RTE) to OUTx disabled 10 µs IOCP Overcurrent protection trip point, 350mA to 2A 4 A IOCP Overcurrent protection trip point, 60mA to 350mA 0.8 A IOCP Overcurrent protection trip point, 10mA to 60mA 0.16 A tOCP Overcurrent protection deglitch time 4.2 µs tRETRY Fault retry time 1.5 ms TTSD Thermal shutdown temperature 165 175 185 °C THYS Thermal shutdown hysteresis 17 °C Electrical Characteristics DSG: 1.65 V ≤ VVM ≤ 11 V, RTE: 0 V ≤ VVM ≤ 11 V and 1.65 V ≤ VVCC ≤ 5.5 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted).Typical values are at TJ = 27°C, VVM = 5 V, VVCC = 3.3 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES, DSG (VM) IVMQ VM sleep mode current IN1 = IN2 = 0 V, after waiting tAUTOSLEEP, VVM = 5 V, TJ = 27°C 20 60 nA IVM VM active mode current IN1 = 3.3 V, IN2 = 0 V 1.2 1.9 mA tWAKE Turnon time Sleep mode to active mode delay 250 μs tAUTOSLEEP Autosleep turnoff time Active mode to autosleep mode delay 0.7 1 1.3 ms fVCP Charge pump switching frequency 6000 kHz POWER SUPPLIES, RTE (VM, VCC) IVMQ VM sleep mode current IN1 = IN2 = 0 V, after waiting tAUTOSLEEP, VVM = 5 V, VVCC = 3.3 V, TJ = 27°C 10 20 nA IVM VM active mode current IN1 = 3.3 V, IN2 = 0 V, VVM = 5 V, VVCC = 3.3 V 0.83 1 mA IVCCQ VCC sleep mode current IN1 = IN2 = 0 V, after waiting tAUTOSLEEP, VVM = 5 V, VVCC = 3.3 V, TJ = 27°C 6 12 nA IVCC VCC active mode current IN1 = 3.3 V, IN2 = 0 V, VVM = 5 V, VVCC = 3.3 V 0.46 0.6 mA tWAKE Turnon time Sleep mode to active mode delay 250 μs tAUTOSLEEP Autosleep turnoff time Active mode to autosleep mode delay 0.75 0.9 1.05 ms LOGIC-LEVEL INPUTS (IN1, IN2) VIL Input logic low voltage 0 0.4 V VIH Input logic high voltage 1.45 5.5 V VHYS Input hysteresis 40 mV IIL Input logic low current VI = 0 V -1 1 µA IIH Input logic high current VINx = 5 V 15 35 µA VnSTALL = VCC 40 nA RPD Input pulldown resistance, INx 200 kΩ tDEGLITCH Input logic deglitch, INx 50 ns TRI-LEVEL INPUTS (IMODE, SMODE) VTHYS Tri-level input logic low voltage 0 0.4 V ITIL Tri-level input Hi-Z voltage 0.75 1.05 V ITIZ Tri-level input logic high voltage 1.45 5.5 V RTPD Tri-level pulldown resistance to GND 83 kΩ ITPU Tri-level pullup current to VCC 10.5 µA OPEN-DRAIN OUTPUTS (nFAULT, nSTALL) VOL Output logic low voltage IOD = 5 mA 0.4 V IOZ Output logic high current VOD = VCC -1 1 µA DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A 120 280 mΩ RDS(ON)_LS Low-side MOSFET on resistance, 350mA to 2A GAINSEL = Low 120 260 mΩ RDS(ON)_LS Low-side MOSFET on resistance, 60mA to 350mA GAINSEL = High-Z 460 900 mΩ RDS(ON)_LS Low-side MOSFET on resistance, 10mA to 60mA GAINSEL = High 2100 4000 mΩ VSD Body diode forward voltage IOUTx = -1 A 0.9 V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 70 ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 40 ns tPDR Input high to output high propagation delay Input to OUTx 450 ns tPDF Input low to output low propagation delay Input to OUTx 450 ns tDEAD Output dead time 500 ns CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage SMODE = Open for RTE package and for DSG package 470 510 550 mV AIPROPI_H Current scaling factor GAINSEL = Low 205 µA/A AIPROPI_M Current scaling factor GAINSEL = High-Z 1050 µA/A AIPROPI_L Current scaling factor GAINSEL = High 4900 µA/A AERR_H Current mirror total error, 350 mA to 2 A GAINSEL = Low, VIPROPI ≤ min(VM-1.25 V, 3.3 V), 3.3 V ≤ VVM ≤ 11 V -6 6 % AERR_H Current mirror total error, 350 mA to 2 A GAINSEL = Low, VIPROPI ≤ min(VM-1.25 V, 3.3 V), 1.65 V ≤ VVM ≤ 3.3 V -6 6 % AERR_M Current mirror total error, 60 mA to 350 mA GAINSEL = High-Z, VIPROPI ≤ min(VM-1.25 V, 3.3 V), 3.3 V ≤ VVM ≤ 11 V -6 6 % GAINSEL = High-Z, VIPROPI ≤ min(VM-1.25 V, 3.3 V), 1.65 V ≤ VVM ≤ 3.3 V -6 6 % AERR_L Current mirror total error, 10 mA to 60 mA GAINSEL = High, VIPROPI ≤ min(VM-1.25 V, 3.3 V), 3.3 V ≤ VVM ≤ 11 V -6 6 % GAINSEL = High, VIPROPI ≤ min(VM-1.25 V, 3.3 V), 1.65 V ≤ VVM ≤ 3.3 V -6 6 % tOFF Current regulation off time 20 µs tBLANK Current regulation blanking time 1.8 µs tDELAY Current sense delay time 1.5 µs tDEG Current regulation and stall detection deglitch time 2 µs HARDWARE STALL DETECTION (TINRUSH) VTINRUSH_trip Threshold voltage for setting tINRUSH timing 0.97 1 1.03 V ITINRUSH Current sourced out of the TINRUSH pin Inputs transition to a state other than IN1=IN2=0, VTINRUSH <  VTINRUSH_trip 8 10 12 µA tdischarge TINRUSH capacitor discharge time 0.8 nF ≤ CTINRUSH ≤ 0.8 µF 100 µs tSTALL_RETRY IN1/IN2 = 0/0 duration to recover from Stall (retry type) 350 900 µs PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO), DSG Supply rising 1.65 V Supply falling 1.30 V VUVLO_VCC VCC supply undervoltage lockout (UVLO), RTE Supply rising 1.65 V Supply falling 1.30 V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 150 mV tUVLO Supply undervoltage deglitch time VVM falling (DSG) or VVCC falling (RTE) to OUTx disabled 10 µs IOCP Overcurrent protection trip point, 350mA to 2A 4 A IOCP Overcurrent protection trip point, 60mA to 350mA 0.8 A IOCP Overcurrent protection trip point, 10mA to 60mA 0.16 A tOCP Overcurrent protection deglitch time 4.2 µs tRETRY Fault retry time 1.5 ms TTSD Thermal shutdown temperature 165 175 185 °C THYS Thermal shutdown hysteresis 17 °C DSG: 1.65 V ≤ VVM ≤ 11 V, RTE: 0 V ≤ VVM ≤ 11 V and 1.65 V ≤ VVCC ≤ 5.5 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted).Typical values are at TJ = 27°C, VVM = 5 V, VVCC = 3.3 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES, DSG (VM) IVMQ VM sleep mode current IN1 = IN2 = 0 V, after waiting tAUTOSLEEP, VVM = 5 V, TJ = 27°C 20 60 nA IVM VM active mode current IN1 = 3.3 V, IN2 = 0 V 1.2 1.9 mA tWAKE Turnon time Sleep mode to active mode delay 250 μs tAUTOSLEEP Autosleep turnoff time Active mode to autosleep mode delay 0.7 1 1.3 ms fVCP Charge pump switching frequency 6000 kHz POWER SUPPLIES, RTE (VM, VCC) IVMQ VM sleep mode current IN1 = IN2 = 0 V, after waiting tAUTOSLEEP, VVM = 5 V, VVCC = 3.3 V, TJ = 27°C 10 20 nA IVM VM active mode current IN1 = 3.3 V, IN2 = 0 V, VVM = 5 V, VVCC = 3.3 V 0.83 1 mA IVCCQ VCC sleep mode current IN1 = IN2 = 0 V, after waiting tAUTOSLEEP, VVM = 5 V, VVCC = 3.3 V, TJ = 27°C 6 12 nA IVCC VCC active mode current IN1 = 3.3 V, IN2 = 0 V, VVM = 5 V, VVCC = 3.3 V 0.46 0.6 mA tWAKE Turnon time Sleep mode to active mode delay 250 μs tAUTOSLEEP Autosleep turnoff time Active mode to autosleep mode delay 0.75 0.9 1.05 ms LOGIC-LEVEL INPUTS (IN1, IN2) VIL Input logic low voltage 0 0.4 V VIH Input logic high voltage 1.45 5.5 V VHYS Input hysteresis 40 mV IIL Input logic low current VI = 0 V -1 1 µA IIH Input logic high current VINx = 5 V 15 35 µA VnSTALL = VCC 40 nA RPD Input pulldown resistance, INx 200 kΩ tDEGLITCH Input logic deglitch, INx 50 ns TRI-LEVEL INPUTS (IMODE, SMODE) VTHYS Tri-level input logic low voltage 0 0.4 V ITIL Tri-level input Hi-Z voltage 0.75 1.05 V ITIZ Tri-level input logic high voltage 1.45 5.5 V RTPD Tri-level pulldown resistance to GND 83 kΩ ITPU Tri-level pullup current to VCC 10.5 µA OPEN-DRAIN OUTPUTS (nFAULT, nSTALL) VOL Output logic low voltage IOD = 5 mA 0.4 V IOZ Output logic high current VOD = VCC -1 1 µA DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A 120 280 mΩ RDS(ON)_LS Low-side MOSFET on resistance, 350mA to 2A GAINSEL = Low 120 260 mΩ RDS(ON)_LS Low-side MOSFET on resistance, 60mA to 350mA GAINSEL = High-Z 460 900 mΩ RDS(ON)_LS Low-side MOSFET on resistance, 10mA to 60mA GAINSEL = High 2100 4000 mΩ VSD Body diode forward voltage IOUTx = -1 A 0.9 V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 70 ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 40 ns tPDR Input high to output high propagation delay Input to OUTx 450 ns tPDF Input low to output low propagation delay Input to OUTx 450 ns tDEAD Output dead time 500 ns CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage SMODE = Open for RTE package and for DSG package 470 510 550 mV AIPROPI_H Current scaling factor GAINSEL = Low 205 µA/A AIPROPI_M Current scaling factor GAINSEL = High-Z 1050 µA/A AIPROPI_L Current scaling factor GAINSEL = High 4900 µA/A AERR_H Current mirror total error, 350 mA to 2 A GAINSEL = Low, VIPROPI ≤ min(VM-1.25 V, 3.3 V), 3.3 V ≤ VVM ≤ 11 V -6 6 % AERR_H Current mirror total error, 350 mA to 2 A GAINSEL = Low, VIPROPI ≤ min(VM-1.25 V, 3.3 V), 1.65 V ≤ VVM ≤ 3.3 V -6 6 % AERR_M Current mirror total error, 60 mA to 350 mA GAINSEL = High-Z, VIPROPI ≤ min(VM-1.25 V, 3.3 V), 3.3 V ≤ VVM ≤ 11 V -6 6 % GAINSEL = High-Z, VIPROPI ≤ min(VM-1.25 V, 3.3 V), 1.65 V ≤ VVM ≤ 3.3 V -6 6 % AERR_L Current mirror total error, 10 mA to 60 mA GAINSEL = High, VIPROPI ≤ min(VM-1.25 V, 3.3 V), 3.3 V ≤ VVM ≤ 11 V -6 6 % GAINSEL = High, VIPROPI ≤ min(VM-1.25 V, 3.3 V), 1.65 V ≤ VVM ≤ 3.3 V -6 6 % tOFF Current regulation off time 20 µs tBLANK Current regulation blanking time 1.8 µs tDELAY Current sense delay time 1.5 µs tDEG Current regulation and stall detection deglitch time 2 µs HARDWARE STALL DETECTION (TINRUSH) VTINRUSH_trip Threshold voltage for setting tINRUSH timing 0.97 1 1.03 V ITINRUSH Current sourced out of the TINRUSH pin Inputs transition to a state other than IN1=IN2=0, VTINRUSH <  VTINRUSH_trip 8 10 12 µA tdischarge TINRUSH capacitor discharge time 0.8 nF ≤ CTINRUSH ≤ 0.8 µF 100 µs tSTALL_RETRY IN1/IN2 = 0/0 duration to recover from Stall (retry type) 350 900 µs PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO), DSG Supply rising 1.65 V Supply falling 1.30 V VUVLO_VCC VCC supply undervoltage lockout (UVLO), RTE Supply rising 1.65 V Supply falling 1.30 V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 150 mV tUVLO Supply undervoltage deglitch time VVM falling (DSG) or VVCC falling (RTE) to OUTx disabled 10 µs IOCP Overcurrent protection trip point, 350mA to 2A 4 A IOCP Overcurrent protection trip point, 60mA to 350mA 0.8 A IOCP Overcurrent protection trip point, 10mA to 60mA 0.16 A tOCP Overcurrent protection deglitch time 4.2 µs tRETRY Fault retry time 1.5 ms TTSD Thermal shutdown temperature 165 175 185 °C THYS Thermal shutdown hysteresis 17 °C DSG: 1.65 V ≤ VVM ≤ 11 V, RTE: 0 V ≤ VVM ≤ 11 V and 1.65 V ≤ VVCC ≤ 5.5 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted).Typical values are at TJ = 27°C, VVM = 5 V, VVCC = 3.3 V.VMVMVCCJJVMVCC PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES, DSG (VM) IVMQ VM sleep mode current IN1 = IN2 = 0 V, after waiting tAUTOSLEEP, VVM = 5 V, TJ = 27°C 20 60 nA IVM VM active mode current IN1 = 3.3 V, IN2 = 0 V 1.2 1.9 mA tWAKE Turnon time Sleep mode to active mode delay 250 μs tAUTOSLEEP Autosleep turnoff time Active mode to autosleep mode delay 0.7 1 1.3 ms fVCP Charge pump switching frequency 6000 kHz POWER SUPPLIES, RTE (VM, VCC) IVMQ VM sleep mode current IN1 = IN2 = 0 V, after waiting tAUTOSLEEP, VVM = 5 V, VVCC = 3.3 V, TJ = 27°C 10 20 nA IVM VM active mode current IN1 = 3.3 V, IN2 = 0 V, VVM = 5 V, VVCC = 3.3 V 0.83 1 mA IVCCQ VCC sleep mode current IN1 = IN2 = 0 V, after waiting tAUTOSLEEP, VVM = 5 V, VVCC = 3.3 V, TJ = 27°C 6 12 nA IVCC VCC active mode current IN1 = 3.3 V, IN2 = 0 V, VVM = 5 V, VVCC = 3.3 V 0.46 0.6 mA tWAKE Turnon time Sleep mode to active mode delay 250 μs tAUTOSLEEP Autosleep turnoff time Active mode to autosleep mode delay 0.75 0.9 1.05 ms LOGIC-LEVEL INPUTS (IN1, IN2) VIL Input logic low voltage 0 0.4 V VIH Input logic high voltage 1.45 5.5 V VHYS Input hysteresis 40 mV IIL Input logic low current VI = 0 V -1 1 µA IIH Input logic high current VINx = 5 V 15 35 µA VnSTALL = VCC 40 nA RPD Input pulldown resistance, INx 200 kΩ tDEGLITCH Input logic deglitch, INx 50 ns TRI-LEVEL INPUTS (IMODE, SMODE) VTHYS Tri-level input logic low voltage 0 0.4 V ITIL Tri-level input Hi-Z voltage 0.75 1.05 V ITIZ Tri-level input logic high voltage 1.45 5.5 V RTPD Tri-level pulldown resistance to GND 83 kΩ ITPU Tri-level pullup current to VCC 10.5 µA OPEN-DRAIN OUTPUTS (nFAULT, nSTALL) VOL Output logic low voltage IOD = 5 mA 0.4 V IOZ Output logic high current VOD = VCC -1 1 µA DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A 120 280 mΩ RDS(ON)_LS Low-side MOSFET on resistance, 350mA to 2A GAINSEL = Low 120 260 mΩ RDS(ON)_LS Low-side MOSFET on resistance, 60mA to 350mA GAINSEL = High-Z 460 900 mΩ RDS(ON)_LS Low-side MOSFET on resistance, 10mA to 60mA GAINSEL = High 2100 4000 mΩ VSD Body diode forward voltage IOUTx = -1 A 0.9 V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 70 ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 40 ns tPDR Input high to output high propagation delay Input to OUTx 450 ns tPDF Input low to output low propagation delay Input to OUTx 450 ns tDEAD Output dead time 500 ns CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage SMODE = Open for RTE package and for DSG package 470 510 550 mV AIPROPI_H Current scaling factor GAINSEL = Low 205 µA/A AIPROPI_M Current scaling factor GAINSEL = High-Z 1050 µA/A AIPROPI_L Current scaling factor GAINSEL = High 4900 µA/A AERR_H Current mirror total error, 350 mA to 2 A GAINSEL = Low, VIPROPI ≤ min(VM-1.25 V, 3.3 V), 3.3 V ≤ VVM ≤ 11 V -6 6 % AERR_H Current mirror total error, 350 mA to 2 A GAINSEL = Low, VIPROPI ≤ min(VM-1.25 V, 3.3 V), 1.65 V ≤ VVM ≤ 3.3 V -6 6 % AERR_M Current mirror total error, 60 mA to 350 mA GAINSEL = High-Z, VIPROPI ≤ min(VM-1.25 V, 3.3 V), 3.3 V ≤ VVM ≤ 11 V -6 6 % GAINSEL = High-Z, VIPROPI ≤ min(VM-1.25 V, 3.3 V), 1.65 V ≤ VVM ≤ 3.3 V -6 6 % AERR_L Current mirror total error, 10 mA to 60 mA GAINSEL = High, VIPROPI ≤ min(VM-1.25 V, 3.3 V), 3.3 V ≤ VVM ≤ 11 V -6 6 % GAINSEL = High, VIPROPI ≤ min(VM-1.25 V, 3.3 V), 1.65 V ≤ VVM ≤ 3.3 V -6 6 % tOFF Current regulation off time 20 µs tBLANK Current regulation blanking time 1.8 µs tDELAY Current sense delay time 1.5 µs tDEG Current regulation and stall detection deglitch time 2 µs HARDWARE STALL DETECTION (TINRUSH) VTINRUSH_trip Threshold voltage for setting tINRUSH timing 0.97 1 1.03 V ITINRUSH Current sourced out of the TINRUSH pin Inputs transition to a state other than IN1=IN2=0, VTINRUSH <  VTINRUSH_trip 8 10 12 µA tdischarge TINRUSH capacitor discharge time 0.8 nF ≤ CTINRUSH ≤ 0.8 µF 100 µs tSTALL_RETRY IN1/IN2 = 0/0 duration to recover from Stall (retry type) 350 900 µs PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO), DSG Supply rising 1.65 V Supply falling 1.30 V VUVLO_VCC VCC supply undervoltage lockout (UVLO), RTE Supply rising 1.65 V Supply falling 1.30 V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 150 mV tUVLO Supply undervoltage deglitch time VVM falling (DSG) or VVCC falling (RTE) to OUTx disabled 10 µs IOCP Overcurrent protection trip point, 350mA to 2A 4 A IOCP Overcurrent protection trip point, 60mA to 350mA 0.8 A IOCP Overcurrent protection trip point, 10mA to 60mA 0.16 A tOCP Overcurrent protection deglitch time 4.2 µs tRETRY Fault retry time 1.5 ms TTSD Thermal shutdown temperature 165 175 185 °C THYS Thermal shutdown hysteresis 17 °C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETERTEST CONDITIONSMINTYPMAXUNIT POWER SUPPLIES, DSG (VM) IVMQ VM sleep mode current IN1 = IN2 = 0 V, after waiting tAUTOSLEEP, VVM = 5 V, TJ = 27°C 20 60 nA IVM VM active mode current IN1 = 3.3 V, IN2 = 0 V 1.2 1.9 mA tWAKE Turnon time Sleep mode to active mode delay 250 μs tAUTOSLEEP Autosleep turnoff time Active mode to autosleep mode delay 0.7 1 1.3 ms fVCP Charge pump switching frequency 6000 kHz POWER SUPPLIES, RTE (VM, VCC) IVMQ VM sleep mode current IN1 = IN2 = 0 V, after waiting tAUTOSLEEP, VVM = 5 V, VVCC = 3.3 V, TJ = 27°C 10 20 nA IVM VM active mode current IN1 = 3.3 V, IN2 = 0 V, VVM = 5 V, VVCC = 3.3 V 0.83 1 mA IVCCQ VCC sleep mode current IN1 = IN2 = 0 V, after waiting tAUTOSLEEP, VVM = 5 V, VVCC = 3.3 V, TJ = 27°C 6 12 nA IVCC VCC active mode current IN1 = 3.3 V, IN2 = 0 V, VVM = 5 V, VVCC = 3.3 V 0.46 0.6 mA tWAKE Turnon time Sleep mode to active mode delay 250 μs tAUTOSLEEP Autosleep turnoff time Active mode to autosleep mode delay 0.75 0.9 1.05 ms LOGIC-LEVEL INPUTS (IN1, IN2) VIL Input logic low voltage 0 0.4 V VIH Input logic high voltage 1.45 5.5 V VHYS Input hysteresis 40 mV IIL Input logic low current VI = 0 V -1 1 µA IIH Input logic high current VINx = 5 V 15 35 µA VnSTALL = VCC 40 nA RPD Input pulldown resistance, INx 200 kΩ tDEGLITCH Input logic deglitch, INx 50 ns TRI-LEVEL INPUTS (IMODE, SMODE) VTHYS Tri-level input logic low voltage 0 0.4 V ITIL Tri-level input Hi-Z voltage 0.75 1.05 V ITIZ Tri-level input logic high voltage 1.45 5.5 V RTPD Tri-level pulldown resistance to GND 83 kΩ ITPU Tri-level pullup current to VCC 10.5 µA OPEN-DRAIN OUTPUTS (nFAULT, nSTALL) VOL Output logic low voltage IOD = 5 mA 0.4 V IOZ Output logic high current VOD = VCC -1 1 µA DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A 120 280 mΩ RDS(ON)_LS Low-side MOSFET on resistance, 350mA to 2A GAINSEL = Low 120 260 mΩ RDS(ON)_LS Low-side MOSFET on resistance, 60mA to 350mA GAINSEL = High-Z 460 900 mΩ RDS(ON)_LS Low-side MOSFET on resistance, 10mA to 60mA GAINSEL = High 2100 4000 mΩ VSD Body diode forward voltage IOUTx = -1 A 0.9 V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 70 ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 40 ns tPDR Input high to output high propagation delay Input to OUTx 450 ns tPDF Input low to output low propagation delay Input to OUTx 450 ns tDEAD Output dead time 500 ns CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage SMODE = Open for RTE package and for DSG package 470 510 550 mV AIPROPI_H Current scaling factor GAINSEL = Low 205 µA/A AIPROPI_M Current scaling factor GAINSEL = High-Z 1050 µA/A AIPROPI_L Current scaling factor GAINSEL = High 4900 µA/A AERR_H Current mirror total error, 350 mA to 2 A GAINSEL = Low, VIPROPI ≤ min(VM-1.25 V, 3.3 V), 3.3 V ≤ VVM ≤ 11 V -6 6 % AERR_H Current mirror total error, 350 mA to 2 A GAINSEL = Low, VIPROPI ≤ min(VM-1.25 V, 3.3 V), 1.65 V ≤ VVM ≤ 3.3 V -6 6 % AERR_M Current mirror total error, 60 mA to 350 mA GAINSEL = High-Z, VIPROPI ≤ min(VM-1.25 V, 3.3 V), 3.3 V ≤ VVM ≤ 11 V -6 6 % GAINSEL = High-Z, VIPROPI ≤ min(VM-1.25 V, 3.3 V), 1.65 V ≤ VVM ≤ 3.3 V -6 6 % AERR_L Current mirror total error, 10 mA to 60 mA GAINSEL = High, VIPROPI ≤ min(VM-1.25 V, 3.3 V), 3.3 V ≤ VVM ≤ 11 V -6 6 % GAINSEL = High, VIPROPI ≤ min(VM-1.25 V, 3.3 V), 1.65 V ≤ VVM ≤ 3.3 V -6 6 % tOFF Current regulation off time 20 µs tBLANK Current regulation blanking time 1.8 µs tDELAY Current sense delay time 1.5 µs tDEG Current regulation and stall detection deglitch time 2 µs HARDWARE STALL DETECTION (TINRUSH) VTINRUSH_trip Threshold voltage for setting tINRUSH timing 0.97 1 1.03 V ITINRUSH Current sourced out of the TINRUSH pin Inputs transition to a state other than IN1=IN2=0, VTINRUSH <  VTINRUSH_trip 8 10 12 µA tdischarge TINRUSH capacitor discharge time 0.8 nF ≤ CTINRUSH ≤ 0.8 µF 100 µs tSTALL_RETRY IN1/IN2 = 0/0 duration to recover from Stall (retry type) 350 900 µs PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO), DSG Supply rising 1.65 V Supply falling 1.30 V VUVLO_VCC VCC supply undervoltage lockout (UVLO), RTE Supply rising 1.65 V Supply falling 1.30 V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 150 mV tUVLO Supply undervoltage deglitch time VVM falling (DSG) or VVCC falling (RTE) to OUTx disabled 10 µs IOCP Overcurrent protection trip point, 350mA to 2A 4 A IOCP Overcurrent protection trip point, 60mA to 350mA 0.8 A IOCP Overcurrent protection trip point, 10mA to 60mA 0.16 A tOCP Overcurrent protection deglitch time 4.2 µs tRETRY Fault retry time 1.5 ms TTSD Thermal shutdown temperature 165 175 185 °C THYS Thermal shutdown hysteresis 17 °C POWER SUPPLIES, DSG (VM) POWER SUPPLIES, DSG (VM) IVMQ VM sleep mode current IN1 = IN2 = 0 V, after waiting tAUTOSLEEP, VVM = 5 V, TJ = 27°C 20 60 nA IVMQ VMQVM sleep mode currentIN1 = IN2 = 0 V, after waiting tAUTOSLEEP, VVM = 5 V, TJ = 27°CAUTOSLEEP, VMJ2060nA IVM VM active mode current IN1 = 3.3 V, IN2 = 0 V 1.2 1.9 mA IVM VMVM active mode currentIN1 = 3.3 V, IN2 = 0 V1.21.9mA tWAKE Turnon time Sleep mode to active mode delay 250 μs tWAKE WAKETurnon timeSleep mode to active mode delay250μs tAUTOSLEEP Autosleep turnoff time Active mode to autosleep mode delay 0.7 1 1.3 ms tAUTOSLEEP AUTOSLEEPAutosleep turnoff timeActive mode to autosleep mode delay0.711.3ms fVCP Charge pump switching frequency 6000 kHz fVCP VCPCharge pump switching frequency6000kHz POWER SUPPLIES, RTE (VM, VCC) POWER SUPPLIES, RTE (VM, VCC) IVMQ VM sleep mode current IN1 = IN2 = 0 V, after waiting tAUTOSLEEP, VVM = 5 V, VVCC = 3.3 V, TJ = 27°C 10 20 nA IVMQ VMQVM sleep mode currentIN1 = IN2 = 0 V, after waiting tAUTOSLEEP, VVM = 5 V, VVCC = 3.3 V, TJ = 27°CAUTOSLEEPVMVCCJ1020nA IVM VM active mode current IN1 = 3.3 V, IN2 = 0 V, VVM = 5 V, VVCC = 3.3 V 0.83 1 mA IVM VMVM active mode currentIN1 = 3.3 V, IN2 = 0 V, VVM = 5 V, VVCC = 3.3 VVMVCC0.831mA IVCCQ VCC sleep mode current IN1 = IN2 = 0 V, after waiting tAUTOSLEEP, VVM = 5 V, VVCC = 3.3 V, TJ = 27°C 6 12 nA IVCCQ VCCQVCC sleep mode currentIN1 = IN2 = 0 V, after waiting tAUTOSLEEP, VVM = 5 V, VVCC = 3.3 V, TJ = 27°CAUTOSLEEPVMVCCJ612nA IVCC VCC active mode current IN1 = 3.3 V, IN2 = 0 V, VVM = 5 V, VVCC = 3.3 V 0.46 0.6 mA IVCC VCCVCC active mode currentIN1 = 3.3 V, IN2 = 0 V, VVM = 5 V, VVCC = 3.3 VVMVCC0.460.6mA tWAKE Turnon time Sleep mode to active mode delay 250 μs tWAKE WAKETurnon timeSleep mode to active mode delay250μs tAUTOSLEEP Autosleep turnoff time Active mode to autosleep mode delay 0.75 0.9 1.05 ms tAUTOSLEEP AUTOSLEEPAutosleep turnoff timeActive mode to autosleep mode delay0.750.91.05ms LOGIC-LEVEL INPUTS (IN1, IN2) LOGIC-LEVEL INPUTS (IN1, IN2) VIL Input logic low voltage 0 0.4 V VIL ILInput logic low voltage00.4V VIH Input logic high voltage 1.45 5.5 V VIH IHInput logic high voltage1.455.5V VHYS Input hysteresis 40 mV VHYS HYSInput hysteresis40mV IIL Input logic low current VI = 0 V -1 1 µA IIL ILInput logic low currentVI = 0 VI-11µA IIH Input logic high current VINx = 5 V 15 35 µA IIH IHInput logic high currentVINx = 5 VINx1535µA VnSTALL = VCC 40 nA VnSTALL = VCCnSTALL40nA RPD Input pulldown resistance, INx 200 kΩ RPD PDInput pulldown resistance, INx200kΩ tDEGLITCH Input logic deglitch, INx 50 ns tDEGLITCH DEGLITCHInput logic deglitch, INx50ns TRI-LEVEL INPUTS (IMODE, SMODE) TRI-LEVEL INPUTS (IMODE, SMODE) VTHYS Tri-level input logic low voltage 0 0.4 V VTHYS THYSTri-level input logic low voltage00.4V ITIL Tri-level input Hi-Z voltage 0.75 1.05 V ITIL TILTri-level input Hi-Z voltage0.751.05V ITIZ Tri-level input logic high voltage 1.45 5.5 V ITIZ TIZTri-level input logic high voltage1.455.5V RTPD Tri-level pulldown resistance to GND 83 kΩ RTPD TPDTri-level pulldown resistanceto GND83kΩ ITPU Tri-level pullup current to VCC 10.5 µA ITPU TPUTri-level pullup currentto VCC10.5µA OPEN-DRAIN OUTPUTS (nFAULT, nSTALL) OPEN-DRAIN OUTPUTS (nFAULT, nSTALL) VOL Output logic low voltage IOD = 5 mA 0.4 V VOL OLOutput logic low voltageIOD = 5 mAOD0.4V IOZ Output logic high current VOD = VCC -1 1 µA IOZ OZOutput logic high currentVOD = VCCOD-11µA DRIVER OUTPUTS (OUTx) DRIVER OUTPUTS (OUTx) RDS(ON)_HS High-side MOSFET on resistance IOUTx = 1 A 120 280 mΩ RDS(ON)_HS DS(ON)_HSHigh-side MOSFET on resistanceIOUTx = 1 AOUTx120280mΩ RDS(ON)_LS Low-side MOSFET on resistance, 350mA to 2A GAINSEL = Low 120 260 mΩ RDS(ON)_LS DS(ON)_LSLow-side MOSFET on resistance, 350mA to 2AGAINSEL = Low120260mΩ RDS(ON)_LS Low-side MOSFET on resistance, 60mA to 350mA GAINSEL = High-Z 460 900 mΩ RDS(ON)_LS DS(ON)_LSLow-side MOSFET on resistance, 60mA to 350mAGAINSEL = High-Z460900mΩ RDS(ON)_LS Low-side MOSFET on resistance, 10mA to 60mA GAINSEL = High 2100 4000 mΩ RDS(ON)_LS DS(ON)_LSLow-side MOSFET on resistance, 10mA to 60mAGAINSEL = High21004000mΩ VSD Body diode forward voltage IOUTx = -1 A 0.9 V VSD SDBody diode forward voltageIOUTx = -1 AOUTx0.9V tRISE Output rise time VOUTx rising from 10% to 90% of VVM 70 ns tRISE RISEOutput rise timeVOUTx rising from 10% to 90% of VVM OUTxVM70ns tFALL Output fall time VOUTx falling from 90% to 10% of VVM 40 ns tFALL FALLOutput fall timeVOUTx falling from 90% to 10% of VVM OUTxVM40ns tPDR Input high to output high propagation delay Input to OUTx 450 ns tPDR PDRInput high to output high propagation delayInput to OUTx450ns tPDF Input low to output low propagation delay Input to OUTx 450 ns tPDF PDFInput low to output low propagation delayInput to OUTx450ns tDEAD Output dead time 500 ns tDEAD DEADOutput dead time500ns CURRENT SENSE AND REGULATION (IPROPI, VREF) CURRENT SENSE AND REGULATION (IPROPI, VREF) VREF_INT Internal reference voltage SMODE = Open for RTE package and for DSG package 470 510 550 mV VREF_INT REF_INTInternal reference voltageSMODE = Open for RTE package and for DSG package470510550mV AIPROPI_H Current scaling factor GAINSEL = Low 205 µA/A AIPROPI_H IPROPI_HCurrent scaling factorGAINSEL = Low205µA/A AIPROPI_M Current scaling factor GAINSEL = High-Z 1050 µA/A AIPROPI_M IPROPI_MCurrent scaling factorGAINSEL = High-Z1050µA/A AIPROPI_L Current scaling factor GAINSEL = High 4900 µA/A AIPROPI_L IPROPI_LCurrent scaling factorGAINSEL = High4900µA/A AERR_H Current mirror total error, 350 mA to 2 A GAINSEL = Low, VIPROPI ≤ min(VM-1.25 V, 3.3 V), 3.3 V ≤ VVM ≤ 11 V -6 6 % AERR_H ERR_HCurrent mirror total error, 350 mA to 2 AGAINSEL = Low, VIPROPI ≤ min(VM-1.25 V, 3.3 V), 3.3 V ≤ VVM ≤ 11 VIPROPIVM-66% AERR_H Current mirror total error, 350 mA to 2 A GAINSEL = Low, VIPROPI ≤ min(VM-1.25 V, 3.3 V), 1.65 V ≤ VVM ≤ 3.3 V -6 6 % AERR_H ERR_HCurrent mirror total error, 350 mA to 2 AGAINSEL = Low, VIPROPI ≤ min(VM-1.25 V, 3.3 V), 1.65 V ≤ VVM ≤ 3.3 VIPROPIVM-66% AERR_M Current mirror total error, 60 mA to 350 mA GAINSEL = High-Z, VIPROPI ≤ min(VM-1.25 V, 3.3 V), 3.3 V ≤ VVM ≤ 11 V -6 6 % AERR_M ERR_MCurrent mirror total error, 60 mA to 350 mAGAINSEL = High-Z, VIPROPI ≤ min(VM-1.25 V, 3.3 V), 3.3 V ≤ VVM ≤ 11 VIPROPIVM-66% GAINSEL = High-Z, VIPROPI ≤ min(VM-1.25 V, 3.3 V), 1.65 V ≤ VVM ≤ 3.3 V -6 6 % GAINSEL = High-Z, VIPROPI ≤ min(VM-1.25 V, 3.3 V), 1.65 V ≤ VVM ≤ 3.3 VIPROPIVM-66% AERR_L Current mirror total error, 10 mA to 60 mA GAINSEL = High, VIPROPI ≤ min(VM-1.25 V, 3.3 V), 3.3 V ≤ VVM ≤ 11 V -6 6 % AERR_L ERR_LCurrent mirror total error, 10 mA to 60 mAGAINSEL = High, VIPROPI ≤ min(VM-1.25 V, 3.3 V), 3.3 V ≤ VVM ≤ 11 VIPROPIVM-66% GAINSEL = High, VIPROPI ≤ min(VM-1.25 V, 3.3 V), 1.65 V ≤ VVM ≤ 3.3 V -6 6 % GAINSEL = High, VIPROPI ≤ min(VM-1.25 V, 3.3 V), 1.65 V ≤ VVM ≤ 3.3 VIPROPIVM-66% tOFF Current regulation off time 20 µs tOFF OFFCurrent regulation off time20µs tBLANK Current regulation blanking time 1.8 µs tBLANK BLANKCurrent regulation blanking time1.8µs tDELAY Current sense delay time 1.5 µs tDELAY DELAYCurrent sense delay time1.5µs tDEG Current regulation and stall detection deglitch time 2 µs tDEG DEGCurrent regulation and stall detection deglitch time2µs HARDWARE STALL DETECTION (TINRUSH) HARDWARE STALL DETECTION (TINRUSH) VTINRUSH_trip Threshold voltage for setting tINRUSH timing 0.97 1 1.03 V VTINRUSH_trip TINRUSH_tripThreshold voltage for setting tINRUSH timingINRUSH0.9711.03V ITINRUSH Current sourced out of the TINRUSH pin Inputs transition to a state other than IN1=IN2=0, VTINRUSH <  VTINRUSH_trip 8 10 12 µA ITINRUSH TINRUSHCurrent sourced out of the TINRUSH pinInputs transition to a state other than IN1=IN2=0, VTINRUSH <  VTINRUSH_trip TINRUSHTINRUSH_trip81012µA tdischarge TINRUSH capacitor discharge time 0.8 nF ≤ CTINRUSH ≤ 0.8 µF 100 µs tdischarge dischargeTINRUSH capacitor discharge time0.8 nF ≤ CTINRUSH ≤ 0.8 µFTINRUSH100µs tSTALL_RETRY IN1/IN2 = 0/0 duration to recover from Stall (retry type) 350 900 µs tSTALL_RETRY STALL_RETRYIN1/IN2 = 0/0 duration to recover from Stall (retry type)350900µs PROTECTION CIRCUITS PROTECTION CIRCUITS VUVLO_VM VM supply undervoltage lockout (UVLO), DSG Supply rising 1.65 V VUVLO_VM UVLO_VMVM supply undervoltage lockout (UVLO), DSGSupply rising1.65V Supply falling 1.30 V Supply falling1.30V VUVLO_VCC VCC supply undervoltage lockout (UVLO), RTE Supply rising 1.65 V VUVLO_VCC UVLO_VCCVCC supply undervoltage lockout (UVLO), RTESupply rising1.65V Supply falling 1.30 V Supply falling1.30V VUVLO_HYS Supply UVLO hysteresis Rising to falling threshold 150 mV VUVLO_HYS UVLO_HYSSupply UVLO hysteresisRising to falling threshold150mV tUVLO Supply undervoltage deglitch time VVM falling (DSG) or VVCC falling (RTE) to OUTx disabled 10 µs tUVLO UVLOSupply undervoltage deglitch timeVVM falling (DSG) or VVCC falling (RTE) to OUTx disabledVMVCC10µs IOCP Overcurrent protection trip point, 350mA to 2A 4 A IOCP OCPOvercurrent protection trip point, 350mA to 2A4A IOCP Overcurrent protection trip point, 60mA to 350mA 0.8 A IOCP OCPOvercurrent protection trip point, 60mA to 350mA0.8A IOCP Overcurrent protection trip point, 10mA to 60mA 0.16 A IOCP OCPOvercurrent protection trip point, 10mA to 60mA0.16A tOCP Overcurrent protection deglitch time 4.2 µs tOCP OCPOvercurrent protection deglitch time4.2µs tRETRY Fault retry time 1.5 ms tRETRY RETRYFault retry time1.5ms TTSD Thermal shutdown temperature 165 175 185 °C TTSD TSDThermal shutdown temperature165175185°C THYS Thermal shutdown hysteresis 17 °C THYS HYSThermal shutdown hysteresis17°C Timing Diagrams Input-to-Output Timing Timing Diagrams Input-to-Output Timing Input-to-Output Timing Input-to-Output Timing Input-to-Output Timing Typical Operating Characteristics High-Side MOSFET ON Resistance (DSG Package) Low-Side MOSFET ON Resistance with GAINSEL = Low (DSG Package) Low-Side MOSFET ON Resistance with GAINSEL = High-Z (DSG Package) Low-Side MOSFET ON Resistance with GAINSEL = High (DSG Package) High-Side MOSFET ON Resistance (RTE Package) Low-Side MOSFET ON Resistance with GAINSEL = Low (RTE Package) Low-Side MOSFET ON Resistance with GAINSEL = High-Z (RTE Package) Low-Side MOSFET ON Resistance with GAINSEL = High (RTE Package) Typical Operating Characteristics High-Side MOSFET ON Resistance (DSG Package) Low-Side MOSFET ON Resistance with GAINSEL = Low (DSG Package) Low-Side MOSFET ON Resistance with GAINSEL = High-Z (DSG Package) Low-Side MOSFET ON Resistance with GAINSEL = High (DSG Package) High-Side MOSFET ON Resistance (RTE Package) Low-Side MOSFET ON Resistance with GAINSEL = Low (RTE Package) Low-Side MOSFET ON Resistance with GAINSEL = High-Z (RTE Package) Low-Side MOSFET ON Resistance with GAINSEL = High (RTE Package) High-Side MOSFET ON Resistance (DSG Package) Low-Side MOSFET ON Resistance with GAINSEL = Low (DSG Package) Low-Side MOSFET ON Resistance with GAINSEL = High-Z (DSG Package) Low-Side MOSFET ON Resistance with GAINSEL = High (DSG Package) High-Side MOSFET ON Resistance (RTE Package) Low-Side MOSFET ON Resistance with GAINSEL = Low (RTE Package) Low-Side MOSFET ON Resistance with GAINSEL = High-Z (RTE Package) Low-Side MOSFET ON Resistance with GAINSEL = High (RTE Package) High-Side MOSFET ON Resistance (DSG Package) Low-Side MOSFET ON Resistance with GAINSEL = Low (DSG Package) Low-Side MOSFET ON Resistance with GAINSEL = High-Z (DSG Package) Low-Side MOSFET ON Resistance with GAINSEL = High (DSG Package) High-Side MOSFET ON Resistance (RTE Package) Low-Side MOSFET ON Resistance with GAINSEL = Low (RTE Package) Low-Side MOSFET ON Resistance with GAINSEL = High-Z (RTE Package) Low-Side MOSFET ON Resistance with GAINSEL = High (RTE Package) High-Side MOSFET ON Resistance (DSG Package) High-Side MOSFET ON Resistance (DSG Package) Low-Side MOSFET ON Resistance with GAINSEL = Low (DSG Package) Low-Side MOSFET ON Resistance with GAINSEL = Low (DSG Package) Low-Side MOSFET ON Resistance with GAINSEL = High-Z (DSG Package) Low-Side MOSFET ON Resistance with GAINSEL = High-Z (DSG Package) Low-Side MOSFET ON Resistance with GAINSEL = High (DSG Package) Low-Side MOSFET ON Resistance with GAINSEL = High (DSG Package) High-Side MOSFET ON Resistance (RTE Package) High-Side MOSFET ON Resistance (RTE Package) Low-Side MOSFET ON Resistance with GAINSEL = Low (RTE Package) Low-Side MOSFET ON Resistance with GAINSEL = Low (RTE Package) Low-Side MOSFET ON Resistance with GAINSEL = High-Z (RTE Package) Low-Side MOSFET ON Resistance with GAINSEL = High-Z (RTE Package) Low-Side MOSFET ON Resistance with GAINSEL = High (RTE Package) Low-Side MOSFET ON Resistance with GAINSEL = High (RTE Package) Detailed Description Overview DRV8213 is a full-bridge driver with integrated current sense, current regulation, and current sense output. To reduce area and external components on a printed circuit board, the device integrates a charge pump regulator and capacitors. In the WQFN (RTE) package, the separate full-bridge (VM) and logic (VCC) supplies allow the full-bridge supply voltage to drop to 0 V without significant impact to RDS(ON) and without triggering UVLO as long as the VCC supply is stable. In the WSON (DSG) package, a single power input (VM) serves as both device power and the full-bridge supply for small design size. An auto-sleep mode reduces microcontroller GPIO connections by eliminating a disable/sleep pin and automatically putting the device into a low-power sleep mode when the PWM inputs remain low for tAUTOSLEEP. The DRV8213 uses a standard 2-pin (IN1/IN2) PWM interface. The IN1/IN2 pins control the full bridge, which consists of four N-channel MOSFETs that have a typical RDS(ON) of 240 mΩ (including one high-side and one low-side FET). Motor speed can be controlled with pulse-width modulation (PWM), at frequencies between 0 to 100 kHz. The integrated current regulation feature limits motor current to a predefined maximum based on the VREF and IPROPI settings. The IPROPI signal can provide current feedback to a microcontroller during both the drive and brake/slow-decay states of the H-bridge. The gain select (GAINSEL) feature allows high accuracy current sensing down to 10 mA average motor current. The RDS(ON) of the low-side MOSFET and the overcurrent protection limit changes according to the GAINSEL setting, thereby leading to optimized answers for different applications and different values of motor current. In the WQFN package (RTE), the DRV8213 has additional pins to configure a hardware stall detection feature based on the IPROPI current sensing signal. The integrated protection features protect the device in the case of a system fault. These include undervoltage lockout (UVLO), overcurrent protection (OCP), and overtemperature shutdown (TSD). Functional Block Diagram DRV8213 in WSON (DSG) package with single supply pin DRV8213 in WQFN (RTE) package with stall detection and dual supply pins External Components #GUID-F7C448F7-4163-40D3-8C04-5B781B2293EA/T5859359-9 lists the recommended external components for the device. Recommended external components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated CVM2 VM GND , VM-rated CVCC VCC GND 0.1-µF, low ESR ceramic capacitor, VM-rated RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level CINRUSH TINRUSH GND Sets the inrush current blanking time RnFAULT VCC nFAULT 10 kΩ RnSTALL VCC nSTALL 10 kΩ Feature Description Bridge Control The DRV8213 output consists of four N-channel MOSFETs designed to drive high current. These outputs are controlled by the two PWM inputs IN1 and IN2 as listed in . H-Bridge Control IN1 IN2 OUT1 OUT2 DESCRIPTION 0 0 High-Z High-Z Coast; H-bridge disabled to High-Z (sleep entered after tAUTOSLEEP) 0 1 L H Reverse (Current OUT2 → OUT1) 1 0 H L Forward (Current OUT1 → OUT2) 1 1 L L Brake; low-side slow decay The inputs can be set to static voltages for 100% duty cycle drive, or they can be pulse-width modulated (PWM) for variable motor speed. When using PWM, switching between driving and braking typically works best. For example, to drive a motor forward with 50% of the maximum RPM, IN1 = 1 and IN2 = 0 during the driving period, and IN1 = 1 and IN2 = 1 during the other period. Alternatively, the coast mode (IN1 = 0, IN2 = 0) for fast current decay is also available. shows how the motor current flows through the H-bridge. The input pins can be powered before VM or VCC are applied. H-Bridge Current Paths When an output changes from driving high to driving low, or driving low to driving high, dead time is automatically inserted to prevent shoot-through. The tDEAD time is the time in the middle when the output is High-Z. If the output pin is measured during tDEAD, the voltage depends on the direction of current. If the current is leaving the pin, the voltage is a diode drop below ground. If the current is entering the pin, the voltage is a diode drop above VM. This diode is the body diode of the high-side or low-side FET. The propagation delay time (tPD) is measured as the time between an input edge to output change. This time accounts for input deglitch time and other internal logic propagation delays. The input deglitch time prevents noise on the input pins from affecting the output state. Additional output slew delay timing accounts for FET turn on or turn off times (tRISE and tFALL). Current Sense and Regulation (IPROPI) The DRV8213 device integrates current sensing, regulation, and current sense feedback. The internal current mirror allows the device to sense the output current without an external sense resistor or sense circuitry, thereby reducing system size, cost, and complexity. The current regulation feature allows for the device to limit the output current in the case of motor stall or high torque events and give detailed feedback to the controller about the load current using the IPROPI output. shows the IPROPI timings specified in the Electrical Characteristics table. Detailed IPROPI Timing Diagram Current Sensing and Current Mirror Gain Selection The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by . The ILSx in is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs. IPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A) The AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. AERR indicates the combined effect of offset error added to the IOUT current and gain error. Depending on the application, high accuracy current sense output is required down to 10 mA current. The GAINSEL feature allows optimizing the design for different end applications by reducing OCP limit and increasing current mirror gain at lower motor currents. The current mirror gain AIPROPI depends on the GAINSEL pin setting, as shown in . GAINSEL Setting GAINSEL AIPROPI Recommended Current Range Low-side FET RDS(ON) Minimum OCP Limit Low 205 μA/A 350 mA to 2 A 120 mΩ 4 A High-Z 1050 μA/A 60 mA to 350 mA 460 mΩ 800 mA High 4900 μA/A 10 mA to 60 mA 2100 mΩ 160 mA The motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown in . The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because the current flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing The IPROPI pin is connected to an external resistor (RIPROPI) to ground to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8213 device implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. For the DSG package, VVREF is set at 510 mV internally. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This maintains good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI has good accuracy up to 2.05 V. The corresponding IPROPI voltage to the output current can be calculated by . VIPROPI (V) = IPROPI (A) x RIPROPI (Ω) The IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready. If the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the logic tables in ), the IPROPI output disables with the input logic signal. Although the low-side MOSFETs still conduct current as the MOSFETs disable according to the device slew rate (noted in the Electrical Characteristics table by tRISE time), IPROPI does not represent the current in the low-side MOSFETs during this turnoff time. Current Regulation The DRV8213 device integrates current regulation using a fixed off-time current chopping scheme, as shown in . This allows the device to limit the output current in case of motor stall, high torque, or other high current load events without involvement from the external controller. Off-Time Current-Regulation The current chopping threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator. ITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω) For example, if VVREF = 3.3 V, RIPROPI = 8.06 kΩ, and AIPROPI = 205 μA/A, then ITRIP will be approximately 2 A. VVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. As mentioned before, for DSG package, VVREF is internally fixed at 510 mV. For RTE package as well, if SMODE is left OPEN, VVREF is internally fixed at 510 mV. The fixed off-time current chopping scheme supports up to 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the INx pins to reset the outputs. When the motor current exceeds the ITRIP threshold, the outputs will enter a current chopping mode with a fixed off time (tOFF). During tOFF, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF, the outputs re-enable according to the control inputs if IOUT is less than ITRIP. If IOUT is still greater than ITRIP, the H-bridge enters another period of brake/low-side slow decay for tOFF after a drive time of tBLANK.. If the state of the INx control pins changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The ITRIP comparator has both a blanking time (tBLK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from effecting the current regulation. These transients may be caused by a capacitor inside the motor or on the connections to the motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, will help filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be adjusted as needed, however large capacitor values may slow down the response time of the current regulation circuitry. The IMODE pin determines the behavior of current regulation in the motor driver. When IMODE is logic low (IMODE = 0), current regulation is disabled. When IMODE is floating (IMODE =Z), the device only performs current regulation during the tINRUSH time when stall detection is enabled. This functionality relates to the hardware stall detection feature described in . When IMODE is logic high (IMODE = 1), current regulation is enabled at all times. summarizes the IMODE pin settings. IMODE configuration IMODE nSTALL Description Low X No current regulation at any time High-Z Low Current regulation at all times High-Z High Current regulation during tINRUSH only High X Current regulation at all times Hardware Stall Detection The DRV8213 integrates a hardware stall detection feature available in the RTE package variant. The principle of the stall detection scheme relies on the fact that motor current increases during stall conditions. The DRV8213 compares the voltage on the IPROPI pin to the voltage on the VREF pin (or 510 mV as applicable) to determine whether a stall condition has occurred. The following paragraphs describe how to configure the device pins for the desired stall detection response. For information on implementing stall detection in the DSG package variant, see . The nSTALL output is pulled low when stall is detected. The nSTALL pin status is latched at power-up. It requires a pull-up resistor to VCC and pulls low when a stall condition occurs. This pin can be connected to the nFAULT pin so both pins share the same pullup resistor. Combining nFAULT and nSTALL signals reduces board area needed by external components and number of input pins on the controller to detect fault and stall conditions. By having separate pullup resistors for the nSTALL and nFAULT, the microcontroller can detect a device fault separate from a stall condtition using two input pins. Connecting nSTALL directly to GND disables stall detection. #GUID-498CF4C7-B671-4200-A4EA-B8124E5CC899/TABLE_X5D_QH1_JTB summarizes the nSTALL pin settings. nSTALL configuration nSTALL Description 0 V Stall detection disabled. Float TINRUSH. If IMODE = High-Z, current regulation will occur at all times when VIPROPI ≥ VVREF. Pull-up resistor to VCC Stall detection enabled. Pin pulls low to indicate a stall. The IPROPI pin provides the current sense signal for the hardware stall detection feature. The VREF pin sets the ITRIP current level at which a stall condition is detected. For DSG package, or RTE package and SMODE = High-Z, VVREF is internally fixed at 510 mV. When VIPROPI ≥ VVREF, then IOUT ≥ ITRIP, and the device will detect a stall condition if the tINRUSH time has passed. The IPROPI and VREF pins are also responsible for current regulation, as described in . The TINRUSH pin sets the amount of time that the stall detection scheme will ignore the inrush current during motor startup (tINRUSH). When the input pins transition from the state IN1 = IN2 = logic low to any other logic combination, the TINRUSH pin sources 10 μA of current into the capacitor (CINRUSH) connected from TINRUSH pin to ground. Once the voltage of the TINRUSH pin exceeds 1 V, the device discharges the capacitor in less than 100 μs. The capacitor charging time is internally multiplied by 65 to determine the tINRUSH time. After tINRUSH time expires, the DRV8213 indicates a stall condition the next time VIPROPI is greater than or equal to VVREF. The following conditions cause the stall detection scheme to ignore the inrush current for tINRUSH time - Power-up of the DRV8213 Recovering from faults After device exits from sleep mode After recovering from stall, as explained in #GUID-498CF4C7-B671-4200-A4EA-B8124E5CC899/TABLE_W1X_JJ1_JTB Use the following formula to select the CINRUSH capacitor - tINRUSH = 6.5 x 106 x CINRUSH The SMODE pin sets the device's response to a stall condition. The device decides that a stall condtion has occurred when VIPROPI is greater than or equal to VVREF and the tINRUSH time has elapsed. When SMODE = logic low, the outputs disable, and the nSTALL pin latches low. When SMODE = logic high, the nSTALL pin still latches low, but the outputs continue to drive current into the motor. When SMODE = Hi-z, the device uses internal VVREF (510 mV) for stall detection, the nSTALL pin still latches low, but the outputs continue to drive current into the motor. #GUID-498CF4C7-B671-4200-A4EA-B8124E5CC899/TABLE_W1X_JJ1_JTB summarizes the SMODE pin settings. SMODE configuration SMODE Description Recovery from Stall Condition 0 Latched disable with indication: the OUTx pins disable and the nSTALL pin pulls low. To recover from this condition, device needs to enter sleep mode. nSTALL will go high after IN1 and IN2 are both low for tSLEEP. After waking up from sleep mode, the stall detection scheme ignores the inrush current for tINRUSH time. 1 Indication only: the OUTx pins remain active and the nSTALL pin pulls low. nSTALL goes high if stall condition is not observed and if IN1 and IN2 are both low for stall retry time (tSTALL_RETRY). After tINRUSH time, if motor current is still higher than ITRIP, nSTALL pin is pulled low again. Hi-z Indication only: the OUTx pins remain active and the nSTALL pin pulls low. Device uses internal VVREF (510 mV) for stall detection. The stall retry time (tSTALL_RETRY) is implemented such that it is always lower than the autosleep turnoff time (tAUTOSLEEP). The IMODE pin determines the behavior of current regulation in the motor driver. When IMODE is floating (IMODE = High-Z), the device only performs current regulation during the tINRUSH time. summarizes the IMODE pin settings. For more details on current regulation, see . The following diagrams show example timing diagrams for different configurations of the hardware stall detection feature. Stall Detection with Latched Disable Stall Detection with nSTALL indication only Stall regulation with current regulation during inrush Stall detection with current regulation Protection Circuits The DRV8213 device is fully protected against supply undervoltage, overcurrent, and overtemperature events. Overcurrent Protection (OCP) An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable and nFAULT is pulled low. The driver re-enables after the fault retry period (tRETRY) has passed. If the fault condition is still present, the cycle repeats as shown in . OCP Operation Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. Thermal Shutdown (TSD) If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled and nFAULT is pulled low. The driver re-enables after the fault retry period (tRETRY) has passed. If the fault condition is still present, the cycle repeats. VM Undervoltage Lockout (UVLO) Whenever the supply voltage falls below the UVLO falling threshold voltage, VUVLO, all circuitry in the device is disabled, the output FETS are disabled, all internal logic is reset and nFAULT is pulled low. When powered by split supplies (RTE package only), the UVLO triggers when the VCC pin voltage drops below VUVLO_VCC falling threshold. This allows the VM supply to dip all the way to 0 V. When operating from a single supply (DSG package only), the UVLO triggers when the VM pin voltage drops below VUVLO_VM falling threshold. Normal operation resumes when the supply voltage rises above the VUVLO rising threshold as shown in . summarizes the conditions when the device enters UVLO. UVLO Operation UVLO response conditions Package variant VVM VVCC Device Response IPROPI RTE 0 V to VVM_MAX <1.65 V UVLO Not available 0 V to VVM_MAX >1.65 V Normal Operation Available for VVM > 1.65 V DSG <1.65 V N/A UVLO Not available 1.65 V to VVM_MAX N/A Normal Operation Available Device Functional Modes #GUID-B5992EA7-5239-428D-948F-848E19BB954C/SLVSCP92157 summarizes the DRV8213 functional modes described in this section. Modes of Operation MODE CONDITION H-BRIDGE INTERNAL CIRCUITS Active Mode IN1 or IN2 = logic high Operating Operating Low-Power Sleep Mode IN1 = IN2 = logic low Disabled Disabled Fault Mode Any fault condition met Disabled See Active Mode After the supply voltage on the VM pin (DSG package) or VCC pin (RTE package) has crossed the rising undervoltage threshold VUVLO, the INx pins are in a state other than IN1 = 0 & IN2 = 0, and tWAKE has elapsed, the device enters active mode. In this mode, the full-bridge, charge pump, and internal logic are active and the device is ready to receive inputs. In the RTE package, when VVCC < VVM, the DRV8213 draws active current from the VM pin rather than the VCC pin (IVM). During this operating condition, IVCC is typically less than 500 nA. When VVCC > VVM, the device draws active current from the VCC pin, and the VM pin will only draw current required by the load. When VVCC = VVM, the active current may be drawn from either supply pin. The active current is typically less than 1.9 mA. Low-Power Sleep Mode When the IN1 and IN2 pins are both low for time tSLEEP, the DRV8213 device enters a low-power sleep mode. In sleep mode, the outputs remain High-Z and the device draws minimal current from the supply pin (IVMQ or IVCCQ). After any of the input pins are set high for longer than the duration of tWAKE, the device becomes fully operational. shows an example timing diagram for entering and leaving sleep mode. Sleep Mode Entry and Wakeup Timing Diagram Fault Mode The DRV8213 device enters fault mode when it encounters a fault condition. This protects the device and the load on the outputs. #GUID-90C13FD3-9C45-47A3-BAD8-32CCD4E329AF/SLVSAR19411 describes the device behavior in the fault mode which depends on the fault condition. The device will leave the fault mode and re-enter the active mode when the system meets the recovery condition. Fault Conditions Summary FAULT FAULT CONDITION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (UVLO), DSG VVM < VUVLO_VM Falling nFAULT Disabled Disabled VVM > VUVLO_VM Rising VCC undervoltage (UVLO), RTE VVCC < VUVLO_VCC Falling nFAULT Disabled Disabled VVCC > VUVLO_VCC Rising Overcurrent (OCP) IOUT > IOCP nFAULT Disabled Operating IOUT < IOCP Thermal Shutdown (TSD) TJ > TTSD nFAULT Disabled Operating TJ < TTSD – THYS Pin Diagrams Logic-Level Inputs shows the input structure for the logic-level input pins IN1 and IN2. Logic-level input Tri-Level Input shows the input structure for the tri-level input pins, GAINSEL, IMODE and SMODE. Tri-level input Detailed Description Overview DRV8213 is a full-bridge driver with integrated current sense, current regulation, and current sense output. To reduce area and external components on a printed circuit board, the device integrates a charge pump regulator and capacitors. In the WQFN (RTE) package, the separate full-bridge (VM) and logic (VCC) supplies allow the full-bridge supply voltage to drop to 0 V without significant impact to RDS(ON) and without triggering UVLO as long as the VCC supply is stable. In the WSON (DSG) package, a single power input (VM) serves as both device power and the full-bridge supply for small design size. An auto-sleep mode reduces microcontroller GPIO connections by eliminating a disable/sleep pin and automatically putting the device into a low-power sleep mode when the PWM inputs remain low for tAUTOSLEEP. The DRV8213 uses a standard 2-pin (IN1/IN2) PWM interface. The IN1/IN2 pins control the full bridge, which consists of four N-channel MOSFETs that have a typical RDS(ON) of 240 mΩ (including one high-side and one low-side FET). Motor speed can be controlled with pulse-width modulation (PWM), at frequencies between 0 to 100 kHz. The integrated current regulation feature limits motor current to a predefined maximum based on the VREF and IPROPI settings. The IPROPI signal can provide current feedback to a microcontroller during both the drive and brake/slow-decay states of the H-bridge. The gain select (GAINSEL) feature allows high accuracy current sensing down to 10 mA average motor current. The RDS(ON) of the low-side MOSFET and the overcurrent protection limit changes according to the GAINSEL setting, thereby leading to optimized answers for different applications and different values of motor current. In the WQFN package (RTE), the DRV8213 has additional pins to configure a hardware stall detection feature based on the IPROPI current sensing signal. The integrated protection features protect the device in the case of a system fault. These include undervoltage lockout (UVLO), overcurrent protection (OCP), and overtemperature shutdown (TSD). Overview DRV8213 is a full-bridge driver with integrated current sense, current regulation, and current sense output. To reduce area and external components on a printed circuit board, the device integrates a charge pump regulator and capacitors. In the WQFN (RTE) package, the separate full-bridge (VM) and logic (VCC) supplies allow the full-bridge supply voltage to drop to 0 V without significant impact to RDS(ON) and without triggering UVLO as long as the VCC supply is stable. In the WSON (DSG) package, a single power input (VM) serves as both device power and the full-bridge supply for small design size. An auto-sleep mode reduces microcontroller GPIO connections by eliminating a disable/sleep pin and automatically putting the device into a low-power sleep mode when the PWM inputs remain low for tAUTOSLEEP. The DRV8213 uses a standard 2-pin (IN1/IN2) PWM interface. The IN1/IN2 pins control the full bridge, which consists of four N-channel MOSFETs that have a typical RDS(ON) of 240 mΩ (including one high-side and one low-side FET). Motor speed can be controlled with pulse-width modulation (PWM), at frequencies between 0 to 100 kHz. The integrated current regulation feature limits motor current to a predefined maximum based on the VREF and IPROPI settings. The IPROPI signal can provide current feedback to a microcontroller during both the drive and brake/slow-decay states of the H-bridge. The gain select (GAINSEL) feature allows high accuracy current sensing down to 10 mA average motor current. The RDS(ON) of the low-side MOSFET and the overcurrent protection limit changes according to the GAINSEL setting, thereby leading to optimized answers for different applications and different values of motor current. In the WQFN package (RTE), the DRV8213 has additional pins to configure a hardware stall detection feature based on the IPROPI current sensing signal. The integrated protection features protect the device in the case of a system fault. These include undervoltage lockout (UVLO), overcurrent protection (OCP), and overtemperature shutdown (TSD). DRV8213 is a full-bridge driver with integrated current sense, current regulation, and current sense output. To reduce area and external components on a printed circuit board, the device integrates a charge pump regulator and capacitors. In the WQFN (RTE) package, the separate full-bridge (VM) and logic (VCC) supplies allow the full-bridge supply voltage to drop to 0 V without significant impact to RDS(ON) and without triggering UVLO as long as the VCC supply is stable. In the WSON (DSG) package, a single power input (VM) serves as both device power and the full-bridge supply for small design size. An auto-sleep mode reduces microcontroller GPIO connections by eliminating a disable/sleep pin and automatically putting the device into a low-power sleep mode when the PWM inputs remain low for tAUTOSLEEP. The DRV8213 uses a standard 2-pin (IN1/IN2) PWM interface. The IN1/IN2 pins control the full bridge, which consists of four N-channel MOSFETs that have a typical RDS(ON) of 240 mΩ (including one high-side and one low-side FET). Motor speed can be controlled with pulse-width modulation (PWM), at frequencies between 0 to 100 kHz. The integrated current regulation feature limits motor current to a predefined maximum based on the VREF and IPROPI settings. The IPROPI signal can provide current feedback to a microcontroller during both the drive and brake/slow-decay states of the H-bridge. The gain select (GAINSEL) feature allows high accuracy current sensing down to 10 mA average motor current. The RDS(ON) of the low-side MOSFET and the overcurrent protection limit changes according to the GAINSEL setting, thereby leading to optimized answers for different applications and different values of motor current. In the WQFN package (RTE), the DRV8213 has additional pins to configure a hardware stall detection feature based on the IPROPI current sensing signal. The integrated protection features protect the device in the case of a system fault. These include undervoltage lockout (UVLO), overcurrent protection (OCP), and overtemperature shutdown (TSD). DRV8213 is a full-bridge driver with integrated current sense, current regulation, and current sense output. To reduce area and external components on a printed circuit board, the device integrates a charge pump regulator and capacitors. In the WQFN (RTE) package, the separate full-bridge (VM) and logic (VCC) supplies allow the full-bridge supply voltage to drop to 0 V without significant impact to RDS(ON) and without triggering UVLO as long as the VCC supply is stable. In the WSON (DSG) package, a single power input (VM) serves as both device power and the full-bridge supply for small design size. An auto-sleep mode reduces microcontroller GPIO connections by eliminating a disable/sleep pin and automatically putting the device into a low-power sleep mode when the PWM inputs remain low for tAUTOSLEEP.DRV8213DS(ON)AUTOSLEEPThe DRV8213 uses a standard 2-pin (IN1/IN2) PWM interface. The IN1/IN2 pins control the full bridge, which consists of four N-channel MOSFETs that have a typical RDS(ON) of 240 mΩ (including one high-side and one low-side FET). Motor speed can be controlled with pulse-width modulation (PWM), at frequencies between 0 to 100 kHz.DRV8213DS(ON)The integrated current regulation feature limits motor current to a predefined maximum based on the VREF and IPROPI settings. The IPROPI signal can provide current feedback to a microcontroller during both the drive and brake/slow-decay states of the H-bridge.The gain select (GAINSEL) feature allows high accuracy current sensing down to 10 mA average motor current. The RDS(ON) of the low-side MOSFET and the overcurrent protection limit changes according to the GAINSEL setting, thereby leading to optimized answers for different applications and different values of motor current.DS(ON)In the WQFN package (RTE), the DRV8213 has additional pins to configure a hardware stall detection feature based on the IPROPI current sensing signal.DRV8213The integrated protection features protect the device in the case of a system fault. These include undervoltage lockout (UVLO), overcurrent protection (OCP), and overtemperature shutdown (TSD). Functional Block Diagram DRV8213 in WSON (DSG) package with single supply pin DRV8213 in WQFN (RTE) package with stall detection and dual supply pins Functional Block Diagram DRV8213 in WSON (DSG) package with single supply pin DRV8213 in WQFN (RTE) package with stall detection and dual supply pins DRV8213 in WSON (DSG) package with single supply pin DRV8213 in WQFN (RTE) package with stall detection and dual supply pins DRV8213 in WSON (DSG) package with single supply pin DRV8213 in WSON (DSG) package with single supply pinDRV8213 DRV8213 in WQFN (RTE) package with stall detection and dual supply pins DRV8213 in WQFN (RTE) package with stall detection and dual supply pinsDRV8213 External Components #GUID-F7C448F7-4163-40D3-8C04-5B781B2293EA/T5859359-9 lists the recommended external components for the device. Recommended external components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated CVM2 VM GND , VM-rated CVCC VCC GND 0.1-µF, low ESR ceramic capacitor, VM-rated RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level CINRUSH TINRUSH GND Sets the inrush current blanking time RnFAULT VCC nFAULT 10 kΩ RnSTALL VCC nSTALL 10 kΩ External Components #GUID-F7C448F7-4163-40D3-8C04-5B781B2293EA/T5859359-9 lists the recommended external components for the device. Recommended external components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated CVM2 VM GND , VM-rated CVCC VCC GND 0.1-µF, low ESR ceramic capacitor, VM-rated RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level CINRUSH TINRUSH GND Sets the inrush current blanking time RnFAULT VCC nFAULT 10 kΩ RnSTALL VCC nSTALL 10 kΩ #GUID-F7C448F7-4163-40D3-8C04-5B781B2293EA/T5859359-9 lists the recommended external components for the device. Recommended external components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated CVM2 VM GND , VM-rated CVCC VCC GND 0.1-µF, low ESR ceramic capacitor, VM-rated RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level CINRUSH TINRUSH GND Sets the inrush current blanking time RnFAULT VCC nFAULT 10 kΩ RnSTALL VCC nSTALL 10 kΩ #GUID-F7C448F7-4163-40D3-8C04-5B781B2293EA/T5859359-9 Recommended external components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated CVM2 VM GND , VM-rated CVCC VCC GND 0.1-µF, low ESR ceramic capacitor, VM-rated RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level CINRUSH TINRUSH GND Sets the inrush current blanking time RnFAULT VCC nFAULT 10 kΩ RnSTALL VCC nSTALL 10 kΩ Recommended external components COMPONENT PIN 1 PIN 2 RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated CVM2 VM GND , VM-rated CVCC VCC GND 0.1-µF, low ESR ceramic capacitor, VM-rated RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level CINRUSH TINRUSH GND Sets the inrush current blanking time RnFAULT VCC nFAULT 10 kΩ RnSTALL VCC nSTALL 10 kΩ COMPONENT PIN 1 PIN 2 RECOMMENDED COMPONENT PIN 1 PIN 2 RECOMMENDED COMPONENTPIN 1PIN 2RECOMMENDED CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated CVM2 VM GND , VM-rated CVCC VCC GND 0.1-µF, low ESR ceramic capacitor, VM-rated RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level CINRUSH TINRUSH GND Sets the inrush current blanking time RnFAULT VCC nFAULT 10 kΩ RnSTALL VCC nSTALL 10 kΩ CVM1 VM GND 0.1-µF, low ESR ceramic capacitor, VM-rated CVM1 VM1VMGND0.1-µF, low ESR ceramic capacitor, VM-rated CVM2 VM GND , VM-rated CVM2 VM2VMGND , VM-rated CVCC VCC GND 0.1-µF, low ESR ceramic capacitor, VM-rated CVCC CVCC VCC VCC VCC GND GND0.1-µF, low ESR ceramic capacitor, VM-rated RIPROPI IPROPI GND Resistor from IPROPI pin to GND, sets the current regulation level RIPROPI RIPROPI IPROPI IPROPI IPROPI GND GND Resistor from IPROPI pin to GND, sets the current regulation level Resistor from IPROPI pin to GND, sets the current regulation level CINRUSH TINRUSH GND Sets the inrush current blanking time CINRUSH CINRUSH INRUSH TINRUSH TINRUSH GND GND Sets the inrush current blanking time Sets the inrush current blanking time RnFAULT VCC nFAULT 10 kΩ RnFAULT RnFAULT nFAULT VCC VCC nFAULT nFAULT10 kΩ RnSTALL VCC nSTALL 10 kΩ RnSTALL RnSTALL nSTALL VCC VCC nSTALL nSTALL10 kΩ Feature Description Bridge Control The DRV8213 output consists of four N-channel MOSFETs designed to drive high current. These outputs are controlled by the two PWM inputs IN1 and IN2 as listed in . H-Bridge Control IN1 IN2 OUT1 OUT2 DESCRIPTION 0 0 High-Z High-Z Coast; H-bridge disabled to High-Z (sleep entered after tAUTOSLEEP) 0 1 L H Reverse (Current OUT2 → OUT1) 1 0 H L Forward (Current OUT1 → OUT2) 1 1 L L Brake; low-side slow decay The inputs can be set to static voltages for 100% duty cycle drive, or they can be pulse-width modulated (PWM) for variable motor speed. When using PWM, switching between driving and braking typically works best. For example, to drive a motor forward with 50% of the maximum RPM, IN1 = 1 and IN2 = 0 during the driving period, and IN1 = 1 and IN2 = 1 during the other period. Alternatively, the coast mode (IN1 = 0, IN2 = 0) for fast current decay is also available. shows how the motor current flows through the H-bridge. The input pins can be powered before VM or VCC are applied. H-Bridge Current Paths When an output changes from driving high to driving low, or driving low to driving high, dead time is automatically inserted to prevent shoot-through. The tDEAD time is the time in the middle when the output is High-Z. If the output pin is measured during tDEAD, the voltage depends on the direction of current. If the current is leaving the pin, the voltage is a diode drop below ground. If the current is entering the pin, the voltage is a diode drop above VM. This diode is the body diode of the high-side or low-side FET. The propagation delay time (tPD) is measured as the time between an input edge to output change. This time accounts for input deglitch time and other internal logic propagation delays. The input deglitch time prevents noise on the input pins from affecting the output state. Additional output slew delay timing accounts for FET turn on or turn off times (tRISE and tFALL). Current Sense and Regulation (IPROPI) The DRV8213 device integrates current sensing, regulation, and current sense feedback. The internal current mirror allows the device to sense the output current without an external sense resistor or sense circuitry, thereby reducing system size, cost, and complexity. The current regulation feature allows for the device to limit the output current in the case of motor stall or high torque events and give detailed feedback to the controller about the load current using the IPROPI output. shows the IPROPI timings specified in the Electrical Characteristics table. Detailed IPROPI Timing Diagram Current Sensing and Current Mirror Gain Selection The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by . The ILSx in is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs. IPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A) The AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. AERR indicates the combined effect of offset error added to the IOUT current and gain error. Depending on the application, high accuracy current sense output is required down to 10 mA current. The GAINSEL feature allows optimizing the design for different end applications by reducing OCP limit and increasing current mirror gain at lower motor currents. The current mirror gain AIPROPI depends on the GAINSEL pin setting, as shown in . GAINSEL Setting GAINSEL AIPROPI Recommended Current Range Low-side FET RDS(ON) Minimum OCP Limit Low 205 μA/A 350 mA to 2 A 120 mΩ 4 A High-Z 1050 μA/A 60 mA to 350 mA 460 mΩ 800 mA High 4900 μA/A 10 mA to 60 mA 2100 mΩ 160 mA The motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown in . The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because the current flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing The IPROPI pin is connected to an external resistor (RIPROPI) to ground to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8213 device implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. For the DSG package, VVREF is set at 510 mV internally. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This maintains good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI has good accuracy up to 2.05 V. The corresponding IPROPI voltage to the output current can be calculated by . VIPROPI (V) = IPROPI (A) x RIPROPI (Ω) The IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready. If the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the logic tables in ), the IPROPI output disables with the input logic signal. Although the low-side MOSFETs still conduct current as the MOSFETs disable according to the device slew rate (noted in the Electrical Characteristics table by tRISE time), IPROPI does not represent the current in the low-side MOSFETs during this turnoff time. Current Regulation The DRV8213 device integrates current regulation using a fixed off-time current chopping scheme, as shown in . This allows the device to limit the output current in case of motor stall, high torque, or other high current load events without involvement from the external controller. Off-Time Current-Regulation The current chopping threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator. ITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω) For example, if VVREF = 3.3 V, RIPROPI = 8.06 kΩ, and AIPROPI = 205 μA/A, then ITRIP will be approximately 2 A. VVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. As mentioned before, for DSG package, VVREF is internally fixed at 510 mV. For RTE package as well, if SMODE is left OPEN, VVREF is internally fixed at 510 mV. The fixed off-time current chopping scheme supports up to 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the INx pins to reset the outputs. When the motor current exceeds the ITRIP threshold, the outputs will enter a current chopping mode with a fixed off time (tOFF). During tOFF, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF, the outputs re-enable according to the control inputs if IOUT is less than ITRIP. If IOUT is still greater than ITRIP, the H-bridge enters another period of brake/low-side slow decay for tOFF after a drive time of tBLANK.. If the state of the INx control pins changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The ITRIP comparator has both a blanking time (tBLK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from effecting the current regulation. These transients may be caused by a capacitor inside the motor or on the connections to the motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, will help filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be adjusted as needed, however large capacitor values may slow down the response time of the current regulation circuitry. The IMODE pin determines the behavior of current regulation in the motor driver. When IMODE is logic low (IMODE = 0), current regulation is disabled. When IMODE is floating (IMODE =Z), the device only performs current regulation during the tINRUSH time when stall detection is enabled. This functionality relates to the hardware stall detection feature described in . When IMODE is logic high (IMODE = 1), current regulation is enabled at all times. summarizes the IMODE pin settings. IMODE configuration IMODE nSTALL Description Low X No current regulation at any time High-Z Low Current regulation at all times High-Z High Current regulation during tINRUSH only High X Current regulation at all times Hardware Stall Detection The DRV8213 integrates a hardware stall detection feature available in the RTE package variant. The principle of the stall detection scheme relies on the fact that motor current increases during stall conditions. The DRV8213 compares the voltage on the IPROPI pin to the voltage on the VREF pin (or 510 mV as applicable) to determine whether a stall condition has occurred. The following paragraphs describe how to configure the device pins for the desired stall detection response. For information on implementing stall detection in the DSG package variant, see . The nSTALL output is pulled low when stall is detected. The nSTALL pin status is latched at power-up. It requires a pull-up resistor to VCC and pulls low when a stall condition occurs. This pin can be connected to the nFAULT pin so both pins share the same pullup resistor. Combining nFAULT and nSTALL signals reduces board area needed by external components and number of input pins on the controller to detect fault and stall conditions. By having separate pullup resistors for the nSTALL and nFAULT, the microcontroller can detect a device fault separate from a stall condtition using two input pins. Connecting nSTALL directly to GND disables stall detection. #GUID-498CF4C7-B671-4200-A4EA-B8124E5CC899/TABLE_X5D_QH1_JTB summarizes the nSTALL pin settings. nSTALL configuration nSTALL Description 0 V Stall detection disabled. Float TINRUSH. If IMODE = High-Z, current regulation will occur at all times when VIPROPI ≥ VVREF. Pull-up resistor to VCC Stall detection enabled. Pin pulls low to indicate a stall. The IPROPI pin provides the current sense signal for the hardware stall detection feature. The VREF pin sets the ITRIP current level at which a stall condition is detected. For DSG package, or RTE package and SMODE = High-Z, VVREF is internally fixed at 510 mV. When VIPROPI ≥ VVREF, then IOUT ≥ ITRIP, and the device will detect a stall condition if the tINRUSH time has passed. The IPROPI and VREF pins are also responsible for current regulation, as described in . The TINRUSH pin sets the amount of time that the stall detection scheme will ignore the inrush current during motor startup (tINRUSH). When the input pins transition from the state IN1 = IN2 = logic low to any other logic combination, the TINRUSH pin sources 10 μA of current into the capacitor (CINRUSH) connected from TINRUSH pin to ground. Once the voltage of the TINRUSH pin exceeds 1 V, the device discharges the capacitor in less than 100 μs. The capacitor charging time is internally multiplied by 65 to determine the tINRUSH time. After tINRUSH time expires, the DRV8213 indicates a stall condition the next time VIPROPI is greater than or equal to VVREF. The following conditions cause the stall detection scheme to ignore the inrush current for tINRUSH time - Power-up of the DRV8213 Recovering from faults After device exits from sleep mode After recovering from stall, as explained in #GUID-498CF4C7-B671-4200-A4EA-B8124E5CC899/TABLE_W1X_JJ1_JTB Use the following formula to select the CINRUSH capacitor - tINRUSH = 6.5 x 106 x CINRUSH The SMODE pin sets the device's response to a stall condition. The device decides that a stall condtion has occurred when VIPROPI is greater than or equal to VVREF and the tINRUSH time has elapsed. When SMODE = logic low, the outputs disable, and the nSTALL pin latches low. When SMODE = logic high, the nSTALL pin still latches low, but the outputs continue to drive current into the motor. When SMODE = Hi-z, the device uses internal VVREF (510 mV) for stall detection, the nSTALL pin still latches low, but the outputs continue to drive current into the motor. #GUID-498CF4C7-B671-4200-A4EA-B8124E5CC899/TABLE_W1X_JJ1_JTB summarizes the SMODE pin settings. SMODE configuration SMODE Description Recovery from Stall Condition 0 Latched disable with indication: the OUTx pins disable and the nSTALL pin pulls low. To recover from this condition, device needs to enter sleep mode. nSTALL will go high after IN1 and IN2 are both low for tSLEEP. After waking up from sleep mode, the stall detection scheme ignores the inrush current for tINRUSH time. 1 Indication only: the OUTx pins remain active and the nSTALL pin pulls low. nSTALL goes high if stall condition is not observed and if IN1 and IN2 are both low for stall retry time (tSTALL_RETRY). After tINRUSH time, if motor current is still higher than ITRIP, nSTALL pin is pulled low again. Hi-z Indication only: the OUTx pins remain active and the nSTALL pin pulls low. Device uses internal VVREF (510 mV) for stall detection. The stall retry time (tSTALL_RETRY) is implemented such that it is always lower than the autosleep turnoff time (tAUTOSLEEP). The IMODE pin determines the behavior of current regulation in the motor driver. When IMODE is floating (IMODE = High-Z), the device only performs current regulation during the tINRUSH time. summarizes the IMODE pin settings. For more details on current regulation, see . The following diagrams show example timing diagrams for different configurations of the hardware stall detection feature. Stall Detection with Latched Disable Stall Detection with nSTALL indication only Stall regulation with current regulation during inrush Stall detection with current regulation Protection Circuits The DRV8213 device is fully protected against supply undervoltage, overcurrent, and overtemperature events. Overcurrent Protection (OCP) An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable and nFAULT is pulled low. The driver re-enables after the fault retry period (tRETRY) has passed. If the fault condition is still present, the cycle repeats as shown in . OCP Operation Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. Thermal Shutdown (TSD) If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled and nFAULT is pulled low. The driver re-enables after the fault retry period (tRETRY) has passed. If the fault condition is still present, the cycle repeats. VM Undervoltage Lockout (UVLO) Whenever the supply voltage falls below the UVLO falling threshold voltage, VUVLO, all circuitry in the device is disabled, the output FETS are disabled, all internal logic is reset and nFAULT is pulled low. When powered by split supplies (RTE package only), the UVLO triggers when the VCC pin voltage drops below VUVLO_VCC falling threshold. This allows the VM supply to dip all the way to 0 V. When operating from a single supply (DSG package only), the UVLO triggers when the VM pin voltage drops below VUVLO_VM falling threshold. Normal operation resumes when the supply voltage rises above the VUVLO rising threshold as shown in . summarizes the conditions when the device enters UVLO. UVLO Operation UVLO response conditions Package variant VVM VVCC Device Response IPROPI RTE 0 V to VVM_MAX <1.65 V UVLO Not available 0 V to VVM_MAX >1.65 V Normal Operation Available for VVM > 1.65 V DSG <1.65 V N/A UVLO Not available 1.65 V to VVM_MAX N/A Normal Operation Available Feature Description Bridge Control The DRV8213 output consists of four N-channel MOSFETs designed to drive high current. These outputs are controlled by the two PWM inputs IN1 and IN2 as listed in . H-Bridge Control IN1 IN2 OUT1 OUT2 DESCRIPTION 0 0 High-Z High-Z Coast; H-bridge disabled to High-Z (sleep entered after tAUTOSLEEP) 0 1 L H Reverse (Current OUT2 → OUT1) 1 0 H L Forward (Current OUT1 → OUT2) 1 1 L L Brake; low-side slow decay The inputs can be set to static voltages for 100% duty cycle drive, or they can be pulse-width modulated (PWM) for variable motor speed. When using PWM, switching between driving and braking typically works best. For example, to drive a motor forward with 50% of the maximum RPM, IN1 = 1 and IN2 = 0 during the driving period, and IN1 = 1 and IN2 = 1 during the other period. Alternatively, the coast mode (IN1 = 0, IN2 = 0) for fast current decay is also available. shows how the motor current flows through the H-bridge. The input pins can be powered before VM or VCC are applied. H-Bridge Current Paths When an output changes from driving high to driving low, or driving low to driving high, dead time is automatically inserted to prevent shoot-through. The tDEAD time is the time in the middle when the output is High-Z. If the output pin is measured during tDEAD, the voltage depends on the direction of current. If the current is leaving the pin, the voltage is a diode drop below ground. If the current is entering the pin, the voltage is a diode drop above VM. This diode is the body diode of the high-side or low-side FET. The propagation delay time (tPD) is measured as the time between an input edge to output change. This time accounts for input deglitch time and other internal logic propagation delays. The input deglitch time prevents noise on the input pins from affecting the output state. Additional output slew delay timing accounts for FET turn on or turn off times (tRISE and tFALL). Bridge Control The DRV8213 output consists of four N-channel MOSFETs designed to drive high current. These outputs are controlled by the two PWM inputs IN1 and IN2 as listed in . H-Bridge Control IN1 IN2 OUT1 OUT2 DESCRIPTION 0 0 High-Z High-Z Coast; H-bridge disabled to High-Z (sleep entered after tAUTOSLEEP) 0 1 L H Reverse (Current OUT2 → OUT1) 1 0 H L Forward (Current OUT1 → OUT2) 1 1 L L Brake; low-side slow decay The inputs can be set to static voltages for 100% duty cycle drive, or they can be pulse-width modulated (PWM) for variable motor speed. When using PWM, switching between driving and braking typically works best. For example, to drive a motor forward with 50% of the maximum RPM, IN1 = 1 and IN2 = 0 during the driving period, and IN1 = 1 and IN2 = 1 during the other period. Alternatively, the coast mode (IN1 = 0, IN2 = 0) for fast current decay is also available. shows how the motor current flows through the H-bridge. The input pins can be powered before VM or VCC are applied. H-Bridge Current Paths When an output changes from driving high to driving low, or driving low to driving high, dead time is automatically inserted to prevent shoot-through. The tDEAD time is the time in the middle when the output is High-Z. If the output pin is measured during tDEAD, the voltage depends on the direction of current. If the current is leaving the pin, the voltage is a diode drop below ground. If the current is entering the pin, the voltage is a diode drop above VM. This diode is the body diode of the high-side or low-side FET. The propagation delay time (tPD) is measured as the time between an input edge to output change. This time accounts for input deglitch time and other internal logic propagation delays. The input deglitch time prevents noise on the input pins from affecting the output state. Additional output slew delay timing accounts for FET turn on or turn off times (tRISE and tFALL). The DRV8213 output consists of four N-channel MOSFETs designed to drive high current. These outputs are controlled by the two PWM inputs IN1 and IN2 as listed in . H-Bridge Control IN1 IN2 OUT1 OUT2 DESCRIPTION 0 0 High-Z High-Z Coast; H-bridge disabled to High-Z (sleep entered after tAUTOSLEEP) 0 1 L H Reverse (Current OUT2 → OUT1) 1 0 H L Forward (Current OUT1 → OUT2) 1 1 L L Brake; low-side slow decay The inputs can be set to static voltages for 100% duty cycle drive, or they can be pulse-width modulated (PWM) for variable motor speed. When using PWM, switching between driving and braking typically works best. For example, to drive a motor forward with 50% of the maximum RPM, IN1 = 1 and IN2 = 0 during the driving period, and IN1 = 1 and IN2 = 1 during the other period. Alternatively, the coast mode (IN1 = 0, IN2 = 0) for fast current decay is also available. shows how the motor current flows through the H-bridge. The input pins can be powered before VM or VCC are applied. H-Bridge Current Paths When an output changes from driving high to driving low, or driving low to driving high, dead time is automatically inserted to prevent shoot-through. The tDEAD time is the time in the middle when the output is High-Z. If the output pin is measured during tDEAD, the voltage depends on the direction of current. If the current is leaving the pin, the voltage is a diode drop below ground. If the current is entering the pin, the voltage is a diode drop above VM. This diode is the body diode of the high-side or low-side FET. The propagation delay time (tPD) is measured as the time between an input edge to output change. This time accounts for input deglitch time and other internal logic propagation delays. The input deglitch time prevents noise on the input pins from affecting the output state. Additional output slew delay timing accounts for FET turn on or turn off times (tRISE and tFALL). The DRV8213 output consists of four N-channel MOSFETs designed to drive high current. These outputs are controlled by the two PWM inputs IN1 and IN2 as listed in .DRV8213 H-Bridge Control IN1 IN2 OUT1 OUT2 DESCRIPTION 0 0 High-Z High-Z Coast; H-bridge disabled to High-Z (sleep entered after tAUTOSLEEP) 0 1 L H Reverse (Current OUT2 → OUT1) 1 0 H L Forward (Current OUT1 → OUT2) 1 1 L L Brake; low-side slow decay H-Bridge Control IN1 IN2 OUT1 OUT2 DESCRIPTION 0 0 High-Z High-Z Coast; H-bridge disabled to High-Z (sleep entered after tAUTOSLEEP) 0 1 L H Reverse (Current OUT2 → OUT1) 1 0 H L Forward (Current OUT1 → OUT2) 1 1 L L Brake; low-side slow decay IN1 IN2 OUT1 OUT2 DESCRIPTION IN1 IN2 OUT1 OUT2 DESCRIPTION IN1IN2OUT1OUT2DESCRIPTION 0 0 High-Z High-Z Coast; H-bridge disabled to High-Z (sleep entered after tAUTOSLEEP) 0 1 L H Reverse (Current OUT2 → OUT1) 1 0 H L Forward (Current OUT1 → OUT2) 1 1 L L Brake; low-side slow decay 0 0 High-Z High-Z Coast; H-bridge disabled to High-Z (sleep entered after tAUTOSLEEP) 00High-ZHigh-ZCoast; H-bridge disabled to High-Z (sleep entered after tAUTOSLEEP)AUTOSLEEP 0 1 L H Reverse (Current OUT2 → OUT1) 01LHReverse (Current OUT2 → OUT1) 1 0 H L Forward (Current OUT1 → OUT2) 10HLForward (Current OUT1 → OUT2) 1 1 L L Brake; low-side slow decay 11LLBrake; low-side slow decayThe inputs can be set to static voltages for 100% duty cycle drive, or they can be pulse-width modulated (PWM) for variable motor speed. When using PWM, switching between driving and braking typically works best. For example, to drive a motor forward with 50% of the maximum RPM, IN1 = 1 and IN2 = 0 during the driving period, and IN1 = 1 and IN2 = 1 during the other period. Alternatively, the coast mode (IN1 = 0, IN2 = 0) for fast current decay is also available. shows how the motor current flows through the H-bridge. The input pins can be powered before VM or VCC are applied.fast current decay H-Bridge Current Paths H-Bridge Current PathsWhen an output changes from driving high to driving low, or driving low to driving high, dead time is automatically inserted to prevent shoot-through. The tDEAD time is the time in the middle when the output is High-Z. If the output pin is measured during tDEAD, the voltage depends on the direction of current. If the current is leaving the pin, the voltage is a diode drop below ground. If the current is entering the pin, the voltage is a diode drop above VM. This diode is the body diode of the high-side or low-side FET.DEADDEADThe propagation delay time (tPD) is measured as the time between an input edge to output change. This time accounts for input deglitch time and other internal logic propagation delays. The input deglitch time prevents noise on the input pins from affecting the output state. Additional output slew delay timing accounts for FET turn on or turn off times (tRISE and tFALL).PDRISEFALL Current Sense and Regulation (IPROPI) The DRV8213 device integrates current sensing, regulation, and current sense feedback. The internal current mirror allows the device to sense the output current without an external sense resistor or sense circuitry, thereby reducing system size, cost, and complexity. The current regulation feature allows for the device to limit the output current in the case of motor stall or high torque events and give detailed feedback to the controller about the load current using the IPROPI output. shows the IPROPI timings specified in the Electrical Characteristics table. Detailed IPROPI Timing Diagram Current Sensing and Current Mirror Gain Selection The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by . The ILSx in is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs. IPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A) The AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. AERR indicates the combined effect of offset error added to the IOUT current and gain error. Depending on the application, high accuracy current sense output is required down to 10 mA current. The GAINSEL feature allows optimizing the design for different end applications by reducing OCP limit and increasing current mirror gain at lower motor currents. The current mirror gain AIPROPI depends on the GAINSEL pin setting, as shown in . GAINSEL Setting GAINSEL AIPROPI Recommended Current Range Low-side FET RDS(ON) Minimum OCP Limit Low 205 μA/A 350 mA to 2 A 120 mΩ 4 A High-Z 1050 μA/A 60 mA to 350 mA 460 mΩ 800 mA High 4900 μA/A 10 mA to 60 mA 2100 mΩ 160 mA The motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown in . The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because the current flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing The IPROPI pin is connected to an external resistor (RIPROPI) to ground to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8213 device implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. For the DSG package, VVREF is set at 510 mV internally. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This maintains good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI has good accuracy up to 2.05 V. The corresponding IPROPI voltage to the output current can be calculated by . VIPROPI (V) = IPROPI (A) x RIPROPI (Ω) The IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready. If the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the logic tables in ), the IPROPI output disables with the input logic signal. Although the low-side MOSFETs still conduct current as the MOSFETs disable according to the device slew rate (noted in the Electrical Characteristics table by tRISE time), IPROPI does not represent the current in the low-side MOSFETs during this turnoff time. Current Regulation The DRV8213 device integrates current regulation using a fixed off-time current chopping scheme, as shown in . This allows the device to limit the output current in case of motor stall, high torque, or other high current load events without involvement from the external controller. Off-Time Current-Regulation The current chopping threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator. ITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω) For example, if VVREF = 3.3 V, RIPROPI = 8.06 kΩ, and AIPROPI = 205 μA/A, then ITRIP will be approximately 2 A. VVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. As mentioned before, for DSG package, VVREF is internally fixed at 510 mV. For RTE package as well, if SMODE is left OPEN, VVREF is internally fixed at 510 mV. The fixed off-time current chopping scheme supports up to 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the INx pins to reset the outputs. When the motor current exceeds the ITRIP threshold, the outputs will enter a current chopping mode with a fixed off time (tOFF). During tOFF, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF, the outputs re-enable according to the control inputs if IOUT is less than ITRIP. If IOUT is still greater than ITRIP, the H-bridge enters another period of brake/low-side slow decay for tOFF after a drive time of tBLANK.. If the state of the INx control pins changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The ITRIP comparator has both a blanking time (tBLK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from effecting the current regulation. These transients may be caused by a capacitor inside the motor or on the connections to the motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, will help filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be adjusted as needed, however large capacitor values may slow down the response time of the current regulation circuitry. The IMODE pin determines the behavior of current regulation in the motor driver. When IMODE is logic low (IMODE = 0), current regulation is disabled. When IMODE is floating (IMODE =Z), the device only performs current regulation during the tINRUSH time when stall detection is enabled. This functionality relates to the hardware stall detection feature described in . When IMODE is logic high (IMODE = 1), current regulation is enabled at all times. summarizes the IMODE pin settings. IMODE configuration IMODE nSTALL Description Low X No current regulation at any time High-Z Low Current regulation at all times High-Z High Current regulation during tINRUSH only High X Current regulation at all times Current Sense and Regulation (IPROPI) The DRV8213 device integrates current sensing, regulation, and current sense feedback. The internal current mirror allows the device to sense the output current without an external sense resistor or sense circuitry, thereby reducing system size, cost, and complexity. The current regulation feature allows for the device to limit the output current in the case of motor stall or high torque events and give detailed feedback to the controller about the load current using the IPROPI output. shows the IPROPI timings specified in the Electrical Characteristics table. Detailed IPROPI Timing Diagram The DRV8213 device integrates current sensing, regulation, and current sense feedback. The internal current mirror allows the device to sense the output current without an external sense resistor or sense circuitry, thereby reducing system size, cost, and complexity. The current regulation feature allows for the device to limit the output current in the case of motor stall or high torque events and give detailed feedback to the controller about the load current using the IPROPI output. shows the IPROPI timings specified in the Electrical Characteristics table. Detailed IPROPI Timing Diagram The DRV8213 device integrates current sensing, regulation, and current sense feedback. The internal current mirror allows the device to sense the output current without an external sense resistor or sense circuitry, thereby reducing system size, cost, and complexity. The current regulation feature allows for the device to limit the output current in the case of motor stall or high torque events and give detailed feedback to the controller about the load current using the IPROPI output. shows the IPROPI timings specified in the Electrical Characteristics table.DRV8213Electrical Characteristics table Detailed IPROPI Timing Diagram Detailed IPROPI Timing Diagram Current Sensing and Current Mirror Gain Selection The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by . The ILSx in is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs. IPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A) The AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. AERR indicates the combined effect of offset error added to the IOUT current and gain error. Depending on the application, high accuracy current sense output is required down to 10 mA current. The GAINSEL feature allows optimizing the design for different end applications by reducing OCP limit and increasing current mirror gain at lower motor currents. The current mirror gain AIPROPI depends on the GAINSEL pin setting, as shown in . GAINSEL Setting GAINSEL AIPROPI Recommended Current Range Low-side FET RDS(ON) Minimum OCP Limit Low 205 μA/A 350 mA to 2 A 120 mΩ 4 A High-Z 1050 μA/A 60 mA to 350 mA 460 mΩ 800 mA High 4900 μA/A 10 mA to 60 mA 2100 mΩ 160 mA The motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown in . The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because the current flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing The IPROPI pin is connected to an external resistor (RIPROPI) to ground to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8213 device implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. For the DSG package, VVREF is set at 510 mV internally. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This maintains good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI has good accuracy up to 2.05 V. The corresponding IPROPI voltage to the output current can be calculated by . VIPROPI (V) = IPROPI (A) x RIPROPI (Ω) The IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready. If the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the logic tables in ), the IPROPI output disables with the input logic signal. Although the low-side MOSFETs still conduct current as the MOSFETs disable according to the device slew rate (noted in the Electrical Characteristics table by tRISE time), IPROPI does not represent the current in the low-side MOSFETs during this turnoff time. Current Sensing and Current Mirror Gain Selection The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by . The ILSx in is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs. IPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A) The AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. AERR indicates the combined effect of offset error added to the IOUT current and gain error. Depending on the application, high accuracy current sense output is required down to 10 mA current. The GAINSEL feature allows optimizing the design for different end applications by reducing OCP limit and increasing current mirror gain at lower motor currents. The current mirror gain AIPROPI depends on the GAINSEL pin setting, as shown in . GAINSEL Setting GAINSEL AIPROPI Recommended Current Range Low-side FET RDS(ON) Minimum OCP Limit Low 205 μA/A 350 mA to 2 A 120 mΩ 4 A High-Z 1050 μA/A 60 mA to 350 mA 460 mΩ 800 mA High 4900 μA/A 10 mA to 60 mA 2100 mΩ 160 mA The motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown in . The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because the current flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing The IPROPI pin is connected to an external resistor (RIPROPI) to ground to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8213 device implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. For the DSG package, VVREF is set at 510 mV internally. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This maintains good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI has good accuracy up to 2.05 V. The corresponding IPROPI voltage to the output current can be calculated by . VIPROPI (V) = IPROPI (A) x RIPROPI (Ω) The IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready. If the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the logic tables in ), the IPROPI output disables with the input logic signal. Although the low-side MOSFETs still conduct current as the MOSFETs disable according to the device slew rate (noted in the Electrical Characteristics table by tRISE time), IPROPI does not represent the current in the low-side MOSFETs during this turnoff time. The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by . The ILSx in is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs. IPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A) The AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. AERR indicates the combined effect of offset error added to the IOUT current and gain error. Depending on the application, high accuracy current sense output is required down to 10 mA current. The GAINSEL feature allows optimizing the design for different end applications by reducing OCP limit and increasing current mirror gain at lower motor currents. The current mirror gain AIPROPI depends on the GAINSEL pin setting, as shown in . GAINSEL Setting GAINSEL AIPROPI Recommended Current Range Low-side FET RDS(ON) Minimum OCP Limit Low 205 μA/A 350 mA to 2 A 120 mΩ 4 A High-Z 1050 μA/A 60 mA to 350 mA 460 mΩ 800 mA High 4900 μA/A 10 mA to 60 mA 2100 mΩ 160 mA The motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown in . The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because the current flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing The IPROPI pin is connected to an external resistor (RIPROPI) to ground to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV8213 device implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. For the DSG package, VVREF is set at 510 mV internally. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This maintains good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI has good accuracy up to 2.05 V. The corresponding IPROPI voltage to the output current can be calculated by . VIPROPI (V) = IPROPI (A) x RIPROPI (Ω) The IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready. If the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the logic tables in ), the IPROPI output disables with the input logic signal. Although the low-side MOSFETs still conduct current as the MOSFETs disable according to the device slew rate (noted in the Electrical Characteristics table by tRISE time), IPROPI does not represent the current in the low-side MOSFETs during this turnoff time. The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge and scaled by the current mirror gain (AIPROPI). The IPROPI output current can be calculated by . The ILSx in is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain or through the body diode, the value of ILSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs.IPROPILSxLSxIPROPI (μA) = (ILS1 + ILS2) (A) x AIPROPI (μA/A)PROPILS1LS2IPROPIThe AERR parameter in the Electrical Characteristics table is the error associated with the AIPROPI gain. AERR indicates the combined effect of offset error added to the IOUT current and gain error.ERRIPROPIERROUTDepending on the application, high accuracy current sense output is required down to 10 mA current. The GAINSEL feature allows optimizing the design for different end applications by reducing OCP limit and increasing current mirror gain at lower motor currents. The current mirror gain AIPROPI depends on the GAINSEL pin setting, as shown in .IPROPI GAINSEL Setting GAINSEL AIPROPI Recommended Current Range Low-side FET RDS(ON) Minimum OCP Limit Low 205 μA/A 350 mA to 2 A 120 mΩ 4 A High-Z 1050 μA/A 60 mA to 350 mA 460 mΩ 800 mA High 4900 μA/A 10 mA to 60 mA 2100 mΩ 160 mA GAINSEL Setting GAINSEL AIPROPI Recommended Current Range Low-side FET RDS(ON) Minimum OCP Limit Low 205 μA/A 350 mA to 2 A 120 mΩ 4 A High-Z 1050 μA/A 60 mA to 350 mA 460 mΩ 800 mA High 4900 μA/A 10 mA to 60 mA 2100 mΩ 160 mA GAINSEL AIPROPI Recommended Current Range Low-side FET RDS(ON) Minimum OCP Limit GAINSEL AIPROPI Recommended Current Range Low-side FET RDS(ON) Minimum OCP Limit GAINSEL GAINSEL AIPROPI AIPROPI IPROPI Recommended Current Range Recommended Current Range Low-side FET RDS(ON) Low-side FET RDS(ON) DS(ON) Minimum OCP Limit Minimum OCP Limit Low 205 μA/A 350 mA to 2 A 120 mΩ 4 A High-Z 1050 μA/A 60 mA to 350 mA 460 mΩ 800 mA High 4900 μA/A 10 mA to 60 mA 2100 mΩ 160 mA Low 205 μA/A 350 mA to 2 A 120 mΩ 4 A Low Low 205 μA/A 205 μA/A 350 mA to 2 A 350 mA to 2 A 120 mΩ 120 mΩ 4 A 4 A High-Z 1050 μA/A 60 mA to 350 mA 460 mΩ 800 mA High-Z High-Z 1050 μA/A 1050 μA/A 60 mA to 350 mA 60 mA to 350 mA 460 mΩ 460 mΩ 800 mA 800 mA High 4900 μA/A 10 mA to 60 mA 2100 mΩ 160 mA High High 4900 μA/A 4900 μA/A 10 mA to 60 mA 10 mA to 60 mA 2100 mΩ 2100 mΩ 160 mA 160 mAThe motor current is measured by an internal current mirror architecture on the low-side FETs which removes the need for an external power sense resistor as shown in . The current mirror architecture senses motor winding current in both the drive and brake low-side slow-decay periods, therefore allowing continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because the current flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. Integrated Current Sensing Integrated Current SensingThe IPROPI pin is connected to an external resistor (RIPROPI) to ground to generate a proportional voltage (VIPROPI) on the IPROPI pin with the IIPROPI analog current output. This allows for the load current to be measured as the voltage drop across the RIPROPI resistor with a standard analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized.IPROPIIPROPIIPROPIIPROPIIPROPIAdditionally, the DRV8213 device implements an internal IPROPI voltage clamp circuit to limit VIPROPI with respect to VVREF on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events. For the DSG package, VVREF is set at 510 mV internally. TI recommends designing for at least 1.25 V of headroom between VVM and the maximum VIPROPI voltage to be measured by the ADC, VIPROPI_MAX. This maintains good accuracy across the range of VIPROPI voltages measured by the ADC. For instance, if VVM is 4.55 V to 11 V, VIPROPI_MAX can be as high as 3.3 V. However, if VVM is 3.3 V, then VIPROPI has good accuracy up to 2.05 V.DRV8213IPROPIVREFVREFVMIPROPIIPROPI_MAXgood accuracyVMIPROPI_MAXVMIPROPIgood accuracyThe corresponding IPROPI voltage to the output current can be calculated by .VIPROPI (V) = IPROPI (A) x RIPROPI (Ω)IPROPIPROPIIPROPIThe IPROPI output bandwidth is limited by the sense delay time (tDELAY) of the internal current sensing circuit. This time is the delay from the low-side MOSFET enable command (from the INx pins) to the IPROPI output being ready.DELAYIf the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output. If a command on the INx pins disables the low-side MOSFETs (according to the logic tables in ), the IPROPI output disables with the input logic signal. Although the low-side MOSFETs still conduct current as the MOSFETs disable according to the device slew rate (noted in the Electrical Characteristics table by tRISE time), IPROPI does not represent the current in the low-side MOSFETs during this turnoff time.RISE Current Regulation The DRV8213 device integrates current regulation using a fixed off-time current chopping scheme, as shown in . This allows the device to limit the output current in case of motor stall, high torque, or other high current load events without involvement from the external controller. Off-Time Current-Regulation The current chopping threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator. ITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω) For example, if VVREF = 3.3 V, RIPROPI = 8.06 kΩ, and AIPROPI = 205 μA/A, then ITRIP will be approximately 2 A. VVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. As mentioned before, for DSG package, VVREF is internally fixed at 510 mV. For RTE package as well, if SMODE is left OPEN, VVREF is internally fixed at 510 mV. The fixed off-time current chopping scheme supports up to 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the INx pins to reset the outputs. When the motor current exceeds the ITRIP threshold, the outputs will enter a current chopping mode with a fixed off time (tOFF). During tOFF, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF, the outputs re-enable according to the control inputs if IOUT is less than ITRIP. If IOUT is still greater than ITRIP, the H-bridge enters another period of brake/low-side slow decay for tOFF after a drive time of tBLANK.. If the state of the INx control pins changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The ITRIP comparator has both a blanking time (tBLK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from effecting the current regulation. These transients may be caused by a capacitor inside the motor or on the connections to the motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, will help filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be adjusted as needed, however large capacitor values may slow down the response time of the current regulation circuitry. The IMODE pin determines the behavior of current regulation in the motor driver. When IMODE is logic low (IMODE = 0), current regulation is disabled. When IMODE is floating (IMODE =Z), the device only performs current regulation during the tINRUSH time when stall detection is enabled. This functionality relates to the hardware stall detection feature described in . When IMODE is logic high (IMODE = 1), current regulation is enabled at all times. summarizes the IMODE pin settings. IMODE configuration IMODE nSTALL Description Low X No current regulation at any time High-Z Low Current regulation at all times High-Z High Current regulation during tINRUSH only High X Current regulation at all times Current Regulation The DRV8213 device integrates current regulation using a fixed off-time current chopping scheme, as shown in . This allows the device to limit the output current in case of motor stall, high torque, or other high current load events without involvement from the external controller. Off-Time Current-Regulation The current chopping threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator. ITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω) For example, if VVREF = 3.3 V, RIPROPI = 8.06 kΩ, and AIPROPI = 205 μA/A, then ITRIP will be approximately 2 A. VVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. As mentioned before, for DSG package, VVREF is internally fixed at 510 mV. For RTE package as well, if SMODE is left OPEN, VVREF is internally fixed at 510 mV. The fixed off-time current chopping scheme supports up to 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the INx pins to reset the outputs. When the motor current exceeds the ITRIP threshold, the outputs will enter a current chopping mode with a fixed off time (tOFF). During tOFF, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF, the outputs re-enable according to the control inputs if IOUT is less than ITRIP. If IOUT is still greater than ITRIP, the H-bridge enters another period of brake/low-side slow decay for tOFF after a drive time of tBLANK.. If the state of the INx control pins changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The ITRIP comparator has both a blanking time (tBLK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from effecting the current regulation. These transients may be caused by a capacitor inside the motor or on the connections to the motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, will help filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be adjusted as needed, however large capacitor values may slow down the response time of the current regulation circuitry. The IMODE pin determines the behavior of current regulation in the motor driver. When IMODE is logic low (IMODE = 0), current regulation is disabled. When IMODE is floating (IMODE =Z), the device only performs current regulation during the tINRUSH time when stall detection is enabled. This functionality relates to the hardware stall detection feature described in . When IMODE is logic high (IMODE = 1), current regulation is enabled at all times. summarizes the IMODE pin settings. IMODE configuration IMODE nSTALL Description Low X No current regulation at any time High-Z Low Current regulation at all times High-Z High Current regulation during tINRUSH only High X Current regulation at all times The DRV8213 device integrates current regulation using a fixed off-time current chopping scheme, as shown in . This allows the device to limit the output current in case of motor stall, high torque, or other high current load events without involvement from the external controller. Off-Time Current-Regulation The current chopping threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator. ITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω) For example, if VVREF = 3.3 V, RIPROPI = 8.06 kΩ, and AIPROPI = 205 μA/A, then ITRIP will be approximately 2 A. VVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V. As mentioned before, for DSG package, VVREF is internally fixed at 510 mV. For RTE package as well, if SMODE is left OPEN, VVREF is internally fixed at 510 mV. The fixed off-time current chopping scheme supports up to 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the INx pins to reset the outputs. When the motor current exceeds the ITRIP threshold, the outputs will enter a current chopping mode with a fixed off time (tOFF). During tOFF, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF, the outputs re-enable according to the control inputs if IOUT is less than ITRIP. If IOUT is still greater than ITRIP, the H-bridge enters another period of brake/low-side slow decay for tOFF after a drive time of tBLANK.. If the state of the INx control pins changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs. The ITRIP comparator has both a blanking time (tBLK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from effecting the current regulation. These transients may be caused by a capacitor inside the motor or on the connections to the motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, will help filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be adjusted as needed, however large capacitor values may slow down the response time of the current regulation circuitry. The IMODE pin determines the behavior of current regulation in the motor driver. When IMODE is logic low (IMODE = 0), current regulation is disabled. When IMODE is floating (IMODE =Z), the device only performs current regulation during the tINRUSH time when stall detection is enabled. This functionality relates to the hardware stall detection feature described in . When IMODE is logic high (IMODE = 1), current regulation is enabled at all times. summarizes the IMODE pin settings. IMODE configuration IMODE nSTALL Description Low X No current regulation at any time High-Z Low Current regulation at all times High-Z High Current regulation during tINRUSH only High X Current regulation at all times The DRV8213 device integrates current regulation using a fixed off-time current chopping scheme, as shown in . This allows the device to limit the output current in case of motor stall, high torque, or other high current load events without involvement from the external controller.DRV8213 Off-Time Current-Regulation Off-Time Current-RegulationThe current chopping threshold (ITRIP) is set through a combination of the VREF voltage (VVREF) and IPROPI output resistor (RIPROPI). This is done by comparing the voltage drop across the external RIPROPI resistor to VVREF with an internal comparator.TRIPVREFIPROPIIPROPIVREFITRIP (A) x AIPROPI (μA/A) = VVREF (V) / RIPROPI (Ω)TRIPIPROPIVREFIPROPIFor example, if VVREF = 3.3 V, RIPROPI = 8.06 kΩ, and AIPROPI = 205 μA/A, then ITRIP will be approximately 2 A.VREFIPROPIIPROPITRIPVVREF must be lower than VVM by at least 1.25 V. The maximum recommended value of VVREF is 3.3 V.VREFVMVREFAs mentioned before, for DSG package, VVREF is internally fixed at 510 mV. For RTE package as well, if SMODE is left OPEN, VVREF is internally fixed at 510 mV.VREFVREFThe fixed off-time current chopping scheme supports up to 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the INx pins to reset the outputs. When the motor current exceeds the ITRIP threshold, the outputs will enter a current chopping mode with a fixed off time (tOFF). During tOFF, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for tOFF duration after IOUT exceeds ITRIP. After tOFF, the outputs re-enable according to the control inputs if IOUT is less than ITRIP. If IOUT is still greater than ITRIP, the H-bridge enters another period of brake/low-side slow decay for tOFF after a drive time of tBLANK.. If the state of the INx control pins changes during the tOFF time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs.OFFTRIPOFFOFFOFFOUTTRIPOFFOUTTRIPOUTTRIPOFFBLANK.OFFOFFThe ITRIP comparator has both a blanking time (tBLK) and a deglitch time (tDEG). The internal blanking time helps to prevent voltage and current transients during output switching from effecting the current regulation. These transients may be caused by a capacitor inside the motor or on the connections to the motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the device, will help filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be adjusted as needed, however large capacitor values may slow down the response time of the current regulation circuitry.TRIPBLKDEGThe IMODE pin determines the behavior of current regulation in the motor driver. When IMODE is logic low (IMODE = 0), current regulation is disabled. When IMODE is floating (IMODE =Z), the device only performs current regulation during the tINRUSH time when stall detection is enabled. This functionality relates to the hardware stall detection feature described in . When IMODE is logic high (IMODE = 1), current regulation is enabled at all times. summarizes the IMODE pin settings.INRUSH IMODE configuration IMODE nSTALL Description Low X No current regulation at any time High-Z Low Current regulation at all times High-Z High Current regulation during tINRUSH only High X Current regulation at all times IMODE configuration IMODE nSTALL Description Low X No current regulation at any time High-Z Low Current regulation at all times High-Z High Current regulation during tINRUSH only High X Current regulation at all times IMODE nSTALL Description IMODE nSTALL Description IMODEnSTALLDescription Low X No current regulation at any time High-Z Low Current regulation at all times High-Z High Current regulation during tINRUSH only High X Current regulation at all times Low X No current regulation at any time Low LowXNo current regulation at any time High-Z Low Current regulation at all times High-Z Low LowCurrent regulation at all times High-Z High Current regulation during tINRUSH only High-Z High HighCurrent regulation during tINRUSH onlyINRUSH High X Current regulation at all times High HighXCurrent regulation at all times Hardware Stall Detection The DRV8213 integrates a hardware stall detection feature available in the RTE package variant. The principle of the stall detection scheme relies on the fact that motor current increases during stall conditions. The DRV8213 compares the voltage on the IPROPI pin to the voltage on the VREF pin (or 510 mV as applicable) to determine whether a stall condition has occurred. The following paragraphs describe how to configure the device pins for the desired stall detection response. For information on implementing stall detection in the DSG package variant, see . The nSTALL output is pulled low when stall is detected. The nSTALL pin status is latched at power-up. It requires a pull-up resistor to VCC and pulls low when a stall condition occurs. This pin can be connected to the nFAULT pin so both pins share the same pullup resistor. Combining nFAULT and nSTALL signals reduces board area needed by external components and number of input pins on the controller to detect fault and stall conditions. By having separate pullup resistors for the nSTALL and nFAULT, the microcontroller can detect a device fault separate from a stall condtition using two input pins. Connecting nSTALL directly to GND disables stall detection. #GUID-498CF4C7-B671-4200-A4EA-B8124E5CC899/TABLE_X5D_QH1_JTB summarizes the nSTALL pin settings. nSTALL configuration nSTALL Description 0 V Stall detection disabled. Float TINRUSH. If IMODE = High-Z, current regulation will occur at all times when VIPROPI ≥ VVREF. Pull-up resistor to VCC Stall detection enabled. Pin pulls low to indicate a stall. The IPROPI pin provides the current sense signal for the hardware stall detection feature. The VREF pin sets the ITRIP current level at which a stall condition is detected. For DSG package, or RTE package and SMODE = High-Z, VVREF is internally fixed at 510 mV. When VIPROPI ≥ VVREF, then IOUT ≥ ITRIP, and the device will detect a stall condition if the tINRUSH time has passed. The IPROPI and VREF pins are also responsible for current regulation, as described in . The TINRUSH pin sets the amount of time that the stall detection scheme will ignore the inrush current during motor startup (tINRUSH). When the input pins transition from the state IN1 = IN2 = logic low to any other logic combination, the TINRUSH pin sources 10 μA of current into the capacitor (CINRUSH) connected from TINRUSH pin to ground. Once the voltage of the TINRUSH pin exceeds 1 V, the device discharges the capacitor in less than 100 μs. The capacitor charging time is internally multiplied by 65 to determine the tINRUSH time. After tINRUSH time expires, the DRV8213 indicates a stall condition the next time VIPROPI is greater than or equal to VVREF. The following conditions cause the stall detection scheme to ignore the inrush current for tINRUSH time - Power-up of the DRV8213 Recovering from faults After device exits from sleep mode After recovering from stall, as explained in #GUID-498CF4C7-B671-4200-A4EA-B8124E5CC899/TABLE_W1X_JJ1_JTB Use the following formula to select the CINRUSH capacitor - tINRUSH = 6.5 x 106 x CINRUSH The SMODE pin sets the device's response to a stall condition. The device decides that a stall condtion has occurred when VIPROPI is greater than or equal to VVREF and the tINRUSH time has elapsed. When SMODE = logic low, the outputs disable, and the nSTALL pin latches low. When SMODE = logic high, the nSTALL pin still latches low, but the outputs continue to drive current into the motor. When SMODE = Hi-z, the device uses internal VVREF (510 mV) for stall detection, the nSTALL pin still latches low, but the outputs continue to drive current into the motor. #GUID-498CF4C7-B671-4200-A4EA-B8124E5CC899/TABLE_W1X_JJ1_JTB summarizes the SMODE pin settings. SMODE configuration SMODE Description Recovery from Stall Condition 0 Latched disable with indication: the OUTx pins disable and the nSTALL pin pulls low. To recover from this condition, device needs to enter sleep mode. nSTALL will go high after IN1 and IN2 are both low for tSLEEP. After waking up from sleep mode, the stall detection scheme ignores the inrush current for tINRUSH time. 1 Indication only: the OUTx pins remain active and the nSTALL pin pulls low. nSTALL goes high if stall condition is not observed and if IN1 and IN2 are both low for stall retry time (tSTALL_RETRY). After tINRUSH time, if motor current is still higher than ITRIP, nSTALL pin is pulled low again. Hi-z Indication only: the OUTx pins remain active and the nSTALL pin pulls low. Device uses internal VVREF (510 mV) for stall detection. The stall retry time (tSTALL_RETRY) is implemented such that it is always lower than the autosleep turnoff time (tAUTOSLEEP). The IMODE pin determines the behavior of current regulation in the motor driver. When IMODE is floating (IMODE = High-Z), the device only performs current regulation during the tINRUSH time. summarizes the IMODE pin settings. For more details on current regulation, see . The following diagrams show example timing diagrams for different configurations of the hardware stall detection feature. Stall Detection with Latched Disable Stall Detection with nSTALL indication only Stall regulation with current regulation during inrush Stall detection with current regulation Hardware Stall Detection The DRV8213 integrates a hardware stall detection feature available in the RTE package variant. The principle of the stall detection scheme relies on the fact that motor current increases during stall conditions. The DRV8213 compares the voltage on the IPROPI pin to the voltage on the VREF pin (or 510 mV as applicable) to determine whether a stall condition has occurred. The following paragraphs describe how to configure the device pins for the desired stall detection response. For information on implementing stall detection in the DSG package variant, see . The nSTALL output is pulled low when stall is detected. The nSTALL pin status is latched at power-up. It requires a pull-up resistor to VCC and pulls low when a stall condition occurs. This pin can be connected to the nFAULT pin so both pins share the same pullup resistor. Combining nFAULT and nSTALL signals reduces board area needed by external components and number of input pins on the controller to detect fault and stall conditions. By having separate pullup resistors for the nSTALL and nFAULT, the microcontroller can detect a device fault separate from a stall condtition using two input pins. Connecting nSTALL directly to GND disables stall detection. #GUID-498CF4C7-B671-4200-A4EA-B8124E5CC899/TABLE_X5D_QH1_JTB summarizes the nSTALL pin settings. nSTALL configuration nSTALL Description 0 V Stall detection disabled. Float TINRUSH. If IMODE = High-Z, current regulation will occur at all times when VIPROPI ≥ VVREF. Pull-up resistor to VCC Stall detection enabled. Pin pulls low to indicate a stall. The IPROPI pin provides the current sense signal for the hardware stall detection feature. The VREF pin sets the ITRIP current level at which a stall condition is detected. For DSG package, or RTE package and SMODE = High-Z, VVREF is internally fixed at 510 mV. When VIPROPI ≥ VVREF, then IOUT ≥ ITRIP, and the device will detect a stall condition if the tINRUSH time has passed. The IPROPI and VREF pins are also responsible for current regulation, as described in . The TINRUSH pin sets the amount of time that the stall detection scheme will ignore the inrush current during motor startup (tINRUSH). When the input pins transition from the state IN1 = IN2 = logic low to any other logic combination, the TINRUSH pin sources 10 μA of current into the capacitor (CINRUSH) connected from TINRUSH pin to ground. Once the voltage of the TINRUSH pin exceeds 1 V, the device discharges the capacitor in less than 100 μs. The capacitor charging time is internally multiplied by 65 to determine the tINRUSH time. After tINRUSH time expires, the DRV8213 indicates a stall condition the next time VIPROPI is greater than or equal to VVREF. The following conditions cause the stall detection scheme to ignore the inrush current for tINRUSH time - Power-up of the DRV8213 Recovering from faults After device exits from sleep mode After recovering from stall, as explained in #GUID-498CF4C7-B671-4200-A4EA-B8124E5CC899/TABLE_W1X_JJ1_JTB Use the following formula to select the CINRUSH capacitor - tINRUSH = 6.5 x 106 x CINRUSH The SMODE pin sets the device's response to a stall condition. The device decides that a stall condtion has occurred when VIPROPI is greater than or equal to VVREF and the tINRUSH time has elapsed. When SMODE = logic low, the outputs disable, and the nSTALL pin latches low. When SMODE = logic high, the nSTALL pin still latches low, but the outputs continue to drive current into the motor. When SMODE = Hi-z, the device uses internal VVREF (510 mV) for stall detection, the nSTALL pin still latches low, but the outputs continue to drive current into the motor. #GUID-498CF4C7-B671-4200-A4EA-B8124E5CC899/TABLE_W1X_JJ1_JTB summarizes the SMODE pin settings. SMODE configuration SMODE Description Recovery from Stall Condition 0 Latched disable with indication: the OUTx pins disable and the nSTALL pin pulls low. To recover from this condition, device needs to enter sleep mode. nSTALL will go high after IN1 and IN2 are both low for tSLEEP. After waking up from sleep mode, the stall detection scheme ignores the inrush current for tINRUSH time. 1 Indication only: the OUTx pins remain active and the nSTALL pin pulls low. nSTALL goes high if stall condition is not observed and if IN1 and IN2 are both low for stall retry time (tSTALL_RETRY). After tINRUSH time, if motor current is still higher than ITRIP, nSTALL pin is pulled low again. Hi-z Indication only: the OUTx pins remain active and the nSTALL pin pulls low. Device uses internal VVREF (510 mV) for stall detection. The stall retry time (tSTALL_RETRY) is implemented such that it is always lower than the autosleep turnoff time (tAUTOSLEEP). The IMODE pin determines the behavior of current regulation in the motor driver. When IMODE is floating (IMODE = High-Z), the device only performs current regulation during the tINRUSH time. summarizes the IMODE pin settings. For more details on current regulation, see . The following diagrams show example timing diagrams for different configurations of the hardware stall detection feature. Stall Detection with Latched Disable Stall Detection with nSTALL indication only Stall regulation with current regulation during inrush Stall detection with current regulation The DRV8213 integrates a hardware stall detection feature available in the RTE package variant. The principle of the stall detection scheme relies on the fact that motor current increases during stall conditions. The DRV8213 compares the voltage on the IPROPI pin to the voltage on the VREF pin (or 510 mV as applicable) to determine whether a stall condition has occurred. The following paragraphs describe how to configure the device pins for the desired stall detection response. For information on implementing stall detection in the DSG package variant, see . The nSTALL output is pulled low when stall is detected. The nSTALL pin status is latched at power-up. It requires a pull-up resistor to VCC and pulls low when a stall condition occurs. This pin can be connected to the nFAULT pin so both pins share the same pullup resistor. Combining nFAULT and nSTALL signals reduces board area needed by external components and number of input pins on the controller to detect fault and stall conditions. By having separate pullup resistors for the nSTALL and nFAULT, the microcontroller can detect a device fault separate from a stall condtition using two input pins. Connecting nSTALL directly to GND disables stall detection. #GUID-498CF4C7-B671-4200-A4EA-B8124E5CC899/TABLE_X5D_QH1_JTB summarizes the nSTALL pin settings. nSTALL configuration nSTALL Description 0 V Stall detection disabled. Float TINRUSH. If IMODE = High-Z, current regulation will occur at all times when VIPROPI ≥ VVREF. Pull-up resistor to VCC Stall detection enabled. Pin pulls low to indicate a stall. The IPROPI pin provides the current sense signal for the hardware stall detection feature. The VREF pin sets the ITRIP current level at which a stall condition is detected. For DSG package, or RTE package and SMODE = High-Z, VVREF is internally fixed at 510 mV. When VIPROPI ≥ VVREF, then IOUT ≥ ITRIP, and the device will detect a stall condition if the tINRUSH time has passed. The IPROPI and VREF pins are also responsible for current regulation, as described in . The TINRUSH pin sets the amount of time that the stall detection scheme will ignore the inrush current during motor startup (tINRUSH). When the input pins transition from the state IN1 = IN2 = logic low to any other logic combination, the TINRUSH pin sources 10 μA of current into the capacitor (CINRUSH) connected from TINRUSH pin to ground. Once the voltage of the TINRUSH pin exceeds 1 V, the device discharges the capacitor in less than 100 μs. The capacitor charging time is internally multiplied by 65 to determine the tINRUSH time. After tINRUSH time expires, the DRV8213 indicates a stall condition the next time VIPROPI is greater than or equal to VVREF. The following conditions cause the stall detection scheme to ignore the inrush current for tINRUSH time - Power-up of the DRV8213 Recovering from faults After device exits from sleep mode After recovering from stall, as explained in #GUID-498CF4C7-B671-4200-A4EA-B8124E5CC899/TABLE_W1X_JJ1_JTB Use the following formula to select the CINRUSH capacitor - tINRUSH = 6.5 x 106 x CINRUSH The SMODE pin sets the device's response to a stall condition. The device decides that a stall condtion has occurred when VIPROPI is greater than or equal to VVREF and the tINRUSH time has elapsed. When SMODE = logic low, the outputs disable, and the nSTALL pin latches low. When SMODE = logic high, the nSTALL pin still latches low, but the outputs continue to drive current into the motor. When SMODE = Hi-z, the device uses internal VVREF (510 mV) for stall detection, the nSTALL pin still latches low, but the outputs continue to drive current into the motor. #GUID-498CF4C7-B671-4200-A4EA-B8124E5CC899/TABLE_W1X_JJ1_JTB summarizes the SMODE pin settings. SMODE configuration SMODE Description Recovery from Stall Condition 0 Latched disable with indication: the OUTx pins disable and the nSTALL pin pulls low. To recover from this condition, device needs to enter sleep mode. nSTALL will go high after IN1 and IN2 are both low for tSLEEP. After waking up from sleep mode, the stall detection scheme ignores the inrush current for tINRUSH time. 1 Indication only: the OUTx pins remain active and the nSTALL pin pulls low. nSTALL goes high if stall condition is not observed and if IN1 and IN2 are both low for stall retry time (tSTALL_RETRY). After tINRUSH time, if motor current is still higher than ITRIP, nSTALL pin is pulled low again. Hi-z Indication only: the OUTx pins remain active and the nSTALL pin pulls low. Device uses internal VVREF (510 mV) for stall detection. The stall retry time (tSTALL_RETRY) is implemented such that it is always lower than the autosleep turnoff time (tAUTOSLEEP). The IMODE pin determines the behavior of current regulation in the motor driver. When IMODE is floating (IMODE = High-Z), the device only performs current regulation during the tINRUSH time. summarizes the IMODE pin settings. For more details on current regulation, see . The following diagrams show example timing diagrams for different configurations of the hardware stall detection feature. Stall Detection with Latched Disable Stall Detection with nSTALL indication only Stall regulation with current regulation during inrush Stall detection with current regulation The DRV8213 integrates a hardware stall detection feature available in the RTE package variant. The principle of the stall detection scheme relies on the fact that motor current increases during stall conditions. The DRV8213 compares the voltage on the IPROPI pin to the voltage on the VREF pin (or 510 mV as applicable) to determine whether a stall condition has occurred. The following paragraphs describe how to configure the device pins for the desired stall detection response. For information on implementing stall detection in the DSG package variant, see .The nSTALL output is pulled low when stall is detected. The nSTALL pin status is latched at power-up. It requires a pull-up resistor to VCC and pulls low when a stall condition occurs. This pin can be connected to the nFAULT pin so both pins share the same pullup resistor. Combining nFAULT and nSTALL signals reduces board area needed by external components and number of input pins on the controller to detect fault and stall conditions. By having separate pullup resistors for the nSTALL and nFAULT, the microcontroller can detect a device fault separate from a stall condtition using two input pins. Connecting nSTALL directly to GND disables stall detection. #GUID-498CF4C7-B671-4200-A4EA-B8124E5CC899/TABLE_X5D_QH1_JTB summarizes the nSTALL pin settings.#GUID-498CF4C7-B671-4200-A4EA-B8124E5CC899/TABLE_X5D_QH1_JTB nSTALL configuration nSTALL Description 0 V Stall detection disabled. Float TINRUSH. If IMODE = High-Z, current regulation will occur at all times when VIPROPI ≥ VVREF. Pull-up resistor to VCC Stall detection enabled. Pin pulls low to indicate a stall. nSTALL configuration nSTALL Description 0 V Stall detection disabled. Float TINRUSH. If IMODE = High-Z, current regulation will occur at all times when VIPROPI ≥ VVREF. Pull-up resistor to VCC Stall detection enabled. Pin pulls low to indicate a stall. nSTALL Description nSTALL Description nSTALLDescription 0 V Stall detection disabled. Float TINRUSH. If IMODE = High-Z, current regulation will occur at all times when VIPROPI ≥ VVREF. Pull-up resistor to VCC Stall detection enabled. Pin pulls low to indicate a stall. 0 V Stall detection disabled. Float TINRUSH. If IMODE = High-Z, current regulation will occur at all times when VIPROPI ≥ VVREF. 0 VStall detection disabled. Float TINRUSH. If IMODE = High-Z, current regulation will occur at all times when VIPROPI ≥ VVREF.IPROPIVREF Pull-up resistor to VCC Stall detection enabled. Pin pulls low to indicate a stall. Pull-up resistor to VCCStall detection enabled. Pin pulls low to indicate a stall.The IPROPI pin provides the current sense signal for the hardware stall detection feature. The VREF pin sets the ITRIP current level at which a stall condition is detected. For DSG package, or RTE package and SMODE = High-Z, VVREF is internally fixed at 510 mV. When VIPROPI ≥ VVREF, then IOUT ≥ ITRIP, and the device will detect a stall condition if the tINRUSH time has passed. The IPROPI and VREF pins are also responsible for current regulation, as described in .IPROPIVREFTRIPVREFIPROPIVREFOUTTRIPINRUSHThe TINRUSH pin sets the amount of time that the stall detection scheme will ignore the inrush current during motor startup (tINRUSH). When the input pins transition from the state IN1 = IN2 = logic low to any other logic combination, the TINRUSH pin sources 10 μA of current into the capacitor (CINRUSH) connected from TINRUSH pin to ground. Once the voltage of the TINRUSH pin exceeds 1 V, the device discharges the capacitor in less than 100 μs. The capacitor charging time is internally multiplied by 65 to determine the tINRUSH time. After tINRUSH time expires, the DRV8213 indicates a stall condition the next time VIPROPI is greater than or equal to VVREF.TINRUSHINRUSHINRUSHINRUSHINRUSHIPROPIVREFThe following conditions cause the stall detection scheme to ignore the inrush current for tINRUSH time -INRUSH Power-up of the DRV8213 Recovering from faults After device exits from sleep mode After recovering from stall, as explained in #GUID-498CF4C7-B671-4200-A4EA-B8124E5CC899/TABLE_W1X_JJ1_JTB Power-up of the DRV8213 Power-up of the DRV8213 Recovering from faults Recovering from faults After device exits from sleep mode After device exits from sleep mode After recovering from stall, as explained in #GUID-498CF4C7-B671-4200-A4EA-B8124E5CC899/TABLE_W1X_JJ1_JTB After recovering from stall, as explained in #GUID-498CF4C7-B671-4200-A4EA-B8124E5CC899/TABLE_W1X_JJ1_JTB #GUID-498CF4C7-B671-4200-A4EA-B8124E5CC899/TABLE_W1X_JJ1_JTBUse the following formula to select the CINRUSH capacitor -INRUSHtINRUSH = 6.5 x 106 x CINRUSH INRUSH6INRUSHThe SMODE pin sets the device's response to a stall condition. The device decides that a stall condtion has occurred when VIPROPI is greater than or equal to VVREF and the tINRUSH time has elapsed. When SMODE = logic low, the outputs disable, and the nSTALL pin latches low. When SMODE = logic high, the nSTALL pin still latches low, but the outputs continue to drive current into the motor. When SMODE = Hi-z, the device uses internal VVREF (510 mV) for stall detection, the nSTALL pin still latches low, but the outputs continue to drive current into the motor. #GUID-498CF4C7-B671-4200-A4EA-B8124E5CC899/TABLE_W1X_JJ1_JTB summarizes the SMODE pin settings.SMODEIPROPIVREFINRUSHVREF#GUID-498CF4C7-B671-4200-A4EA-B8124E5CC899/TABLE_W1X_JJ1_JTB SMODE configuration SMODE Description Recovery from Stall Condition 0 Latched disable with indication: the OUTx pins disable and the nSTALL pin pulls low. To recover from this condition, device needs to enter sleep mode. nSTALL will go high after IN1 and IN2 are both low for tSLEEP. After waking up from sleep mode, the stall detection scheme ignores the inrush current for tINRUSH time. 1 Indication only: the OUTx pins remain active and the nSTALL pin pulls low. nSTALL goes high if stall condition is not observed and if IN1 and IN2 are both low for stall retry time (tSTALL_RETRY). After tINRUSH time, if motor current is still higher than ITRIP, nSTALL pin is pulled low again. Hi-z Indication only: the OUTx pins remain active and the nSTALL pin pulls low. Device uses internal VVREF (510 mV) for stall detection. SMODE configuration SMODE Description Recovery from Stall Condition 0 Latched disable with indication: the OUTx pins disable and the nSTALL pin pulls low. To recover from this condition, device needs to enter sleep mode. nSTALL will go high after IN1 and IN2 are both low for tSLEEP. After waking up from sleep mode, the stall detection scheme ignores the inrush current for tINRUSH time. 1 Indication only: the OUTx pins remain active and the nSTALL pin pulls low. nSTALL goes high if stall condition is not observed and if IN1 and IN2 are both low for stall retry time (tSTALL_RETRY). After tINRUSH time, if motor current is still higher than ITRIP, nSTALL pin is pulled low again. Hi-z Indication only: the OUTx pins remain active and the nSTALL pin pulls low. Device uses internal VVREF (510 mV) for stall detection. SMODE Description Recovery from Stall Condition SMODE Description Recovery from Stall Condition SMODEDescription Recovery from Stall Condition Recovery from Stall Condition 0 Latched disable with indication: the OUTx pins disable and the nSTALL pin pulls low. To recover from this condition, device needs to enter sleep mode. nSTALL will go high after IN1 and IN2 are both low for tSLEEP. After waking up from sleep mode, the stall detection scheme ignores the inrush current for tINRUSH time. 1 Indication only: the OUTx pins remain active and the nSTALL pin pulls low. nSTALL goes high if stall condition is not observed and if IN1 and IN2 are both low for stall retry time (tSTALL_RETRY). After tINRUSH time, if motor current is still higher than ITRIP, nSTALL pin is pulled low again. Hi-z Indication only: the OUTx pins remain active and the nSTALL pin pulls low. Device uses internal VVREF (510 mV) for stall detection. 0 Latched disable with indication: the OUTx pins disable and the nSTALL pin pulls low. To recover from this condition, device needs to enter sleep mode. nSTALL will go high after IN1 and IN2 are both low for tSLEEP. After waking up from sleep mode, the stall detection scheme ignores the inrush current for tINRUSH time. 0Latched disable with indication: the OUTx pins disable and the nSTALL pin pulls low.To recover from this condition, device needs to enter sleep mode. nSTALL will go high after IN1 and IN2 are both low for tSLEEP. After waking up from sleep mode, the stall detection scheme ignores the inrush current for tINRUSH time. SLEEPINRUSH 1 Indication only: the OUTx pins remain active and the nSTALL pin pulls low. nSTALL goes high if stall condition is not observed and if IN1 and IN2 are both low for stall retry time (tSTALL_RETRY). After tINRUSH time, if motor current is still higher than ITRIP, nSTALL pin is pulled low again. 1Indication only: the OUTx pins remain active and the nSTALL pin pulls low. nSTALL goes high if stall condition is not observed and if IN1 and IN2 are both low for stall retry time (tSTALL_RETRY). After tINRUSH time, if motor current is still higher than ITRIP, nSTALL pin is pulled low again. nSTALL goes high if stall condition is not observed and if IN1 and IN2 are both low for stall retry time (tSTALL_RETRY). After tINRUSH time, if motor current is still higher than ITRIP, nSTALL pin is pulled low again.STALL_RETRYINRUSHTRIP Hi-z Indication only: the OUTx pins remain active and the nSTALL pin pulls low. Device uses internal VVREF (510 mV) for stall detection. Hi-z Hi-z Indication only: the OUTx pins remain active and the nSTALL pin pulls low. Device uses internal VVREF (510 mV) for stall detection. Indication only: the OUTx pins remain active and the nSTALL pin pulls low. Device uses internal VVREF (510 mV) for stall detection.VREFThe stall retry time (tSTALL_RETRY) is implemented such that it is always lower than the autosleep turnoff time (tAUTOSLEEP).STALL_RETRYAUTOSLEEPThe IMODE pin determines the behavior of current regulation in the motor driver. When IMODE is floating (IMODE = High-Z), the device only performs current regulation during the tINRUSH time. summarizes the IMODE pin settings. For more details on current regulation, see .IMODEINRUSHThe following diagrams show example timing diagrams for different configurations of the hardware stall detection feature. Stall Detection with Latched Disable Stall Detection with nSTALL indication only Stall regulation with current regulation during inrush Stall detection with current regulation Stall Detection with Latched Disable Stall Detection with Latched Disable Stall Detection with nSTALL indication only Stall Detection with nSTALL indication only Stall regulation with current regulation during inrush Stall regulation with current regulation during inrush Stall detection with current regulation Stall detection with current regulation Protection Circuits The DRV8213 device is fully protected against supply undervoltage, overcurrent, and overtemperature events. Overcurrent Protection (OCP) An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable and nFAULT is pulled low. The driver re-enables after the fault retry period (tRETRY) has passed. If the fault condition is still present, the cycle repeats as shown in . OCP Operation Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. Thermal Shutdown (TSD) If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled and nFAULT is pulled low. The driver re-enables after the fault retry period (tRETRY) has passed. If the fault condition is still present, the cycle repeats. VM Undervoltage Lockout (UVLO) Whenever the supply voltage falls below the UVLO falling threshold voltage, VUVLO, all circuitry in the device is disabled, the output FETS are disabled, all internal logic is reset and nFAULT is pulled low. When powered by split supplies (RTE package only), the UVLO triggers when the VCC pin voltage drops below VUVLO_VCC falling threshold. This allows the VM supply to dip all the way to 0 V. When operating from a single supply (DSG package only), the UVLO triggers when the VM pin voltage drops below VUVLO_VM falling threshold. Normal operation resumes when the supply voltage rises above the VUVLO rising threshold as shown in . summarizes the conditions when the device enters UVLO. UVLO Operation UVLO response conditions Package variant VVM VVCC Device Response IPROPI RTE 0 V to VVM_MAX <1.65 V UVLO Not available 0 V to VVM_MAX >1.65 V Normal Operation Available for VVM > 1.65 V DSG <1.65 V N/A UVLO Not available 1.65 V to VVM_MAX N/A Normal Operation Available Protection Circuits The DRV8213 device is fully protected against supply undervoltage, overcurrent, and overtemperature events. The DRV8213 device is fully protected against supply undervoltage, overcurrent, and overtemperature events. The DRV8213 device is fully protected against supply undervoltage, overcurrent, and overtemperature events.DRV8213 Overcurrent Protection (OCP) An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable and nFAULT is pulled low. The driver re-enables after the fault retry period (tRETRY) has passed. If the fault condition is still present, the cycle repeats as shown in . OCP Operation Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. Overcurrent Protection (OCP) An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable and nFAULT is pulled low. The driver re-enables after the fault retry period (tRETRY) has passed. If the fault condition is still present, the cycle repeats as shown in . OCP Operation Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable and nFAULT is pulled low. The driver re-enables after the fault retry period (tRETRY) has passed. If the fault condition is still present, the cycle repeats as shown in . OCP Operation Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable and nFAULT is pulled low. The driver re-enables after the fault retry period (tRETRY) has passed. If the fault condition is still present, the cycle repeats as shown in .OCPRETRY OCP Operation OCP OperationOvercurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings. Thermal Shutdown (TSD) If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled and nFAULT is pulled low. The driver re-enables after the fault retry period (tRETRY) has passed. If the fault condition is still present, the cycle repeats. Thermal Shutdown (TSD) If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled and nFAULT is pulled low. The driver re-enables after the fault retry period (tRETRY) has passed. If the fault condition is still present, the cycle repeats. If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled and nFAULT is pulled low. The driver re-enables after the fault retry period (tRETRY) has passed. If the fault condition is still present, the cycle repeats. If the die temperature exceeds the thermal shutdown temperature threshold (TTSD), all FETs in the H-bridge are disabled and nFAULT is pulled low. The driver re-enables after the fault retry period (tRETRY) has passed. If the fault condition is still present, the cycle repeats.TSDRETRY VM Undervoltage Lockout (UVLO) Whenever the supply voltage falls below the UVLO falling threshold voltage, VUVLO, all circuitry in the device is disabled, the output FETS are disabled, all internal logic is reset and nFAULT is pulled low. When powered by split supplies (RTE package only), the UVLO triggers when the VCC pin voltage drops below VUVLO_VCC falling threshold. This allows the VM supply to dip all the way to 0 V. When operating from a single supply (DSG package only), the UVLO triggers when the VM pin voltage drops below VUVLO_VM falling threshold. Normal operation resumes when the supply voltage rises above the VUVLO rising threshold as shown in . summarizes the conditions when the device enters UVLO. UVLO Operation UVLO response conditions Package variant VVM VVCC Device Response IPROPI RTE 0 V to VVM_MAX <1.65 V UVLO Not available 0 V to VVM_MAX >1.65 V Normal Operation Available for VVM > 1.65 V DSG <1.65 V N/A UVLO Not available 1.65 V to VVM_MAX N/A Normal Operation Available VM Undervoltage Lockout (UVLO) Whenever the supply voltage falls below the UVLO falling threshold voltage, VUVLO, all circuitry in the device is disabled, the output FETS are disabled, all internal logic is reset and nFAULT is pulled low. When powered by split supplies (RTE package only), the UVLO triggers when the VCC pin voltage drops below VUVLO_VCC falling threshold. This allows the VM supply to dip all the way to 0 V. When operating from a single supply (DSG package only), the UVLO triggers when the VM pin voltage drops below VUVLO_VM falling threshold. Normal operation resumes when the supply voltage rises above the VUVLO rising threshold as shown in . summarizes the conditions when the device enters UVLO. UVLO Operation UVLO response conditions Package variant VVM VVCC Device Response IPROPI RTE 0 V to VVM_MAX <1.65 V UVLO Not available 0 V to VVM_MAX >1.65 V Normal Operation Available for VVM > 1.65 V DSG <1.65 V N/A UVLO Not available 1.65 V to VVM_MAX N/A Normal Operation Available Whenever the supply voltage falls below the UVLO falling threshold voltage, VUVLO, all circuitry in the device is disabled, the output FETS are disabled, all internal logic is reset and nFAULT is pulled low. When powered by split supplies (RTE package only), the UVLO triggers when the VCC pin voltage drops below VUVLO_VCC falling threshold. This allows the VM supply to dip all the way to 0 V. When operating from a single supply (DSG package only), the UVLO triggers when the VM pin voltage drops below VUVLO_VM falling threshold. Normal operation resumes when the supply voltage rises above the VUVLO rising threshold as shown in . summarizes the conditions when the device enters UVLO. UVLO Operation UVLO response conditions Package variant VVM VVCC Device Response IPROPI RTE 0 V to VVM_MAX <1.65 V UVLO Not available 0 V to VVM_MAX >1.65 V Normal Operation Available for VVM > 1.65 V DSG <1.65 V N/A UVLO Not available 1.65 V to VVM_MAX N/A Normal Operation Available Whenever the supply voltage falls below the UVLO falling threshold voltage, VUVLO, all circuitry in the device is disabled, the output FETS are disabled, all internal logic is reset and nFAULT is pulled low. When powered by split supplies (RTE package only), the UVLO triggers when the VCC pin voltage drops below VUVLO_VCC falling threshold. This allows the VM supply to dip all the way to 0 V. When operating from a single supply (DSG package only), the UVLO triggers when the VM pin voltage drops below VUVLO_VM falling threshold. Normal operation resumes when the supply voltage rises above the VUVLO rising threshold as shown in . summarizes the conditions when the device enters UVLO.UVLOUVLO_VCCUVLO_VMUVLO UVLO Operation UVLO Operation UVLO response conditions Package variant VVM VVCC Device Response IPROPI RTE 0 V to VVM_MAX <1.65 V UVLO Not available 0 V to VVM_MAX >1.65 V Normal Operation Available for VVM > 1.65 V DSG <1.65 V N/A UVLO Not available 1.65 V to VVM_MAX N/A Normal Operation Available UVLO response conditions Package variant VVM VVCC Device Response IPROPI RTE 0 V to VVM_MAX <1.65 V UVLO Not available 0 V to VVM_MAX >1.65 V Normal Operation Available for VVM > 1.65 V DSG <1.65 V N/A UVLO Not available 1.65 V to VVM_MAX N/A Normal Operation Available Package variant VVM VVCC Device Response IPROPI Package variant VVM VVCC Device Response IPROPI Package variantVVM VMVVCC VCCDevice Response IPROPI IPROPI RTE 0 V to VVM_MAX <1.65 V UVLO Not available 0 V to VVM_MAX >1.65 V Normal Operation Available for VVM > 1.65 V DSG <1.65 V N/A UVLO Not available 1.65 V to VVM_MAX N/A Normal Operation Available RTE 0 V to VVM_MAX <1.65 V UVLO Not available RTE0 V to VVM_MAX VM_MAX<1.65 VUVLO Not available Not available 0 V to VVM_MAX >1.65 V Normal Operation Available for VVM > 1.65 V 0 V to VVM_MAX VM_MAX>1.65 VNormal Operation Available for VVM > 1.65 V Available for VVM > 1.65 VVM DSG <1.65 V N/A UVLO Not available DSG<1.65 VN/AUVLO Not available Not available 1.65 V to VVM_MAX N/A Normal Operation Available 1.65 V to VVM_MAX VM_MAXN/ANormal Operation Available Available Device Functional Modes #GUID-B5992EA7-5239-428D-948F-848E19BB954C/SLVSCP92157 summarizes the DRV8213 functional modes described in this section. Modes of Operation MODE CONDITION H-BRIDGE INTERNAL CIRCUITS Active Mode IN1 or IN2 = logic high Operating Operating Low-Power Sleep Mode IN1 = IN2 = logic low Disabled Disabled Fault Mode Any fault condition met Disabled See Active Mode After the supply voltage on the VM pin (DSG package) or VCC pin (RTE package) has crossed the rising undervoltage threshold VUVLO, the INx pins are in a state other than IN1 = 0 & IN2 = 0, and tWAKE has elapsed, the device enters active mode. In this mode, the full-bridge, charge pump, and internal logic are active and the device is ready to receive inputs. In the RTE package, when VVCC < VVM, the DRV8213 draws active current from the VM pin rather than the VCC pin (IVM). During this operating condition, IVCC is typically less than 500 nA. When VVCC > VVM, the device draws active current from the VCC pin, and the VM pin will only draw current required by the load. When VVCC = VVM, the active current may be drawn from either supply pin. The active current is typically less than 1.9 mA. Low-Power Sleep Mode When the IN1 and IN2 pins are both low for time tSLEEP, the DRV8213 device enters a low-power sleep mode. In sleep mode, the outputs remain High-Z and the device draws minimal current from the supply pin (IVMQ or IVCCQ). After any of the input pins are set high for longer than the duration of tWAKE, the device becomes fully operational. shows an example timing diagram for entering and leaving sleep mode. Sleep Mode Entry and Wakeup Timing Diagram Fault Mode The DRV8213 device enters fault mode when it encounters a fault condition. This protects the device and the load on the outputs. #GUID-90C13FD3-9C45-47A3-BAD8-32CCD4E329AF/SLVSAR19411 describes the device behavior in the fault mode which depends on the fault condition. The device will leave the fault mode and re-enter the active mode when the system meets the recovery condition. Fault Conditions Summary FAULT FAULT CONDITION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (UVLO), DSG VVM < VUVLO_VM Falling nFAULT Disabled Disabled VVM > VUVLO_VM Rising VCC undervoltage (UVLO), RTE VVCC < VUVLO_VCC Falling nFAULT Disabled Disabled VVCC > VUVLO_VCC Rising Overcurrent (OCP) IOUT > IOCP nFAULT Disabled Operating IOUT < IOCP Thermal Shutdown (TSD) TJ > TTSD nFAULT Disabled Operating TJ < TTSD – THYS Device Functional Modes #GUID-B5992EA7-5239-428D-948F-848E19BB954C/SLVSCP92157 summarizes the DRV8213 functional modes described in this section. Modes of Operation MODE CONDITION H-BRIDGE INTERNAL CIRCUITS Active Mode IN1 or IN2 = logic high Operating Operating Low-Power Sleep Mode IN1 = IN2 = logic low Disabled Disabled Fault Mode Any fault condition met Disabled See #GUID-B5992EA7-5239-428D-948F-848E19BB954C/SLVSCP92157 summarizes the DRV8213 functional modes described in this section. Modes of Operation MODE CONDITION H-BRIDGE INTERNAL CIRCUITS Active Mode IN1 or IN2 = logic high Operating Operating Low-Power Sleep Mode IN1 = IN2 = logic low Disabled Disabled Fault Mode Any fault condition met Disabled See #GUID-B5992EA7-5239-428D-948F-848E19BB954C/SLVSCP92157 summarizes the DRV8213 functional modes described in this section.#GUID-B5992EA7-5239-428D-948F-848E19BB954C/SLVSCP92157DRV8213 Modes of Operation MODE CONDITION H-BRIDGE INTERNAL CIRCUITS Active Mode IN1 or IN2 = logic high Operating Operating Low-Power Sleep Mode IN1 = IN2 = logic low Disabled Disabled Fault Mode Any fault condition met Disabled See Modes of Operation MODE CONDITION H-BRIDGE INTERNAL CIRCUITS Active Mode IN1 or IN2 = logic high Operating Operating Low-Power Sleep Mode IN1 = IN2 = logic low Disabled Disabled Fault Mode Any fault condition met Disabled See MODE CONDITION H-BRIDGE INTERNAL CIRCUITS MODE CONDITION H-BRIDGE INTERNAL CIRCUITS MODECONDITIONH-BRIDGEINTERNAL CIRCUITS Active Mode IN1 or IN2 = logic high Operating Operating Low-Power Sleep Mode IN1 = IN2 = logic low Disabled Disabled Fault Mode Any fault condition met Disabled See Active Mode IN1 or IN2 = logic high Operating Operating Active ModeIN1 or IN2 = logic highOperatingOperating Low-Power Sleep Mode IN1 = IN2 = logic low Disabled Disabled Low-Power Sleep ModeIN1 = IN2 = logic lowDisabledDisabled Fault Mode Any fault condition met Disabled See Fault ModeAny fault condition metDisabledSee Active Mode After the supply voltage on the VM pin (DSG package) or VCC pin (RTE package) has crossed the rising undervoltage threshold VUVLO, the INx pins are in a state other than IN1 = 0 & IN2 = 0, and tWAKE has elapsed, the device enters active mode. In this mode, the full-bridge, charge pump, and internal logic are active and the device is ready to receive inputs. In the RTE package, when VVCC < VVM, the DRV8213 draws active current from the VM pin rather than the VCC pin (IVM). During this operating condition, IVCC is typically less than 500 nA. When VVCC > VVM, the device draws active current from the VCC pin, and the VM pin will only draw current required by the load. When VVCC = VVM, the active current may be drawn from either supply pin. The active current is typically less than 1.9 mA. Active Mode After the supply voltage on the VM pin (DSG package) or VCC pin (RTE package) has crossed the rising undervoltage threshold VUVLO, the INx pins are in a state other than IN1 = 0 & IN2 = 0, and tWAKE has elapsed, the device enters active mode. In this mode, the full-bridge, charge pump, and internal logic are active and the device is ready to receive inputs. In the RTE package, when VVCC < VVM, the DRV8213 draws active current from the VM pin rather than the VCC pin (IVM). During this operating condition, IVCC is typically less than 500 nA. When VVCC > VVM, the device draws active current from the VCC pin, and the VM pin will only draw current required by the load. When VVCC = VVM, the active current may be drawn from either supply pin. The active current is typically less than 1.9 mA. After the supply voltage on the VM pin (DSG package) or VCC pin (RTE package) has crossed the rising undervoltage threshold VUVLO, the INx pins are in a state other than IN1 = 0 & IN2 = 0, and tWAKE has elapsed, the device enters active mode. In this mode, the full-bridge, charge pump, and internal logic are active and the device is ready to receive inputs. In the RTE package, when VVCC < VVM, the DRV8213 draws active current from the VM pin rather than the VCC pin (IVM). During this operating condition, IVCC is typically less than 500 nA. When VVCC > VVM, the device draws active current from the VCC pin, and the VM pin will only draw current required by the load. When VVCC = VVM, the active current may be drawn from either supply pin. The active current is typically less than 1.9 mA. After the supply voltage on the VM pin (DSG package) or VCC pin (RTE package) has crossed the rising undervoltage threshold VUVLO, the INx pins are in a state other than IN1 = 0 & IN2 = 0, and tWAKE has elapsed, the device enters active mode. In this mode, the full-bridge, charge pump, and internal logic are active and the device is ready to receive inputs.UVLOWAKE In the RTE package, when VVCC < VVM, the DRV8213 draws active current from the VM pin rather than the VCC pin (IVM). During this operating condition, IVCC is typically less than 500 nA. When VVCC > VVM, the device draws active current from the VCC pin, and the VM pin will only draw current required by the load. When VVCC = VVM, the active current may be drawn from either supply pin. The active current is typically less than 1.9 mA. In the RTE package, when VVCC < VVM, the DRV8213 draws active current from the VM pin rather than the VCC pin (IVM). During this operating condition, IVCC is typically less than 500 nA. When VVCC > VVM, the device draws active current from the VCC pin, and the VM pin will only draw current required by the load. When VVCC = VVM, the active current may be drawn from either supply pin. The active current is typically less than 1.9 mA.VCCVMDRV8213VMVCCVCCVMVCCVM Low-Power Sleep Mode When the IN1 and IN2 pins are both low for time tSLEEP, the DRV8213 device enters a low-power sleep mode. In sleep mode, the outputs remain High-Z and the device draws minimal current from the supply pin (IVMQ or IVCCQ). After any of the input pins are set high for longer than the duration of tWAKE, the device becomes fully operational. shows an example timing diagram for entering and leaving sleep mode. Sleep Mode Entry and Wakeup Timing Diagram Low-Power Sleep Mode When the IN1 and IN2 pins are both low for time tSLEEP, the DRV8213 device enters a low-power sleep mode. In sleep mode, the outputs remain High-Z and the device draws minimal current from the supply pin (IVMQ or IVCCQ). After any of the input pins are set high for longer than the duration of tWAKE, the device becomes fully operational. shows an example timing diagram for entering and leaving sleep mode. Sleep Mode Entry and Wakeup Timing Diagram When the IN1 and IN2 pins are both low for time tSLEEP, the DRV8213 device enters a low-power sleep mode. In sleep mode, the outputs remain High-Z and the device draws minimal current from the supply pin (IVMQ or IVCCQ). After any of the input pins are set high for longer than the duration of tWAKE, the device becomes fully operational. shows an example timing diagram for entering and leaving sleep mode. Sleep Mode Entry and Wakeup Timing Diagram When the IN1 and IN2 pins are both low for time tSLEEP, the DRV8213 device enters a low-power sleep mode. In sleep mode, the outputs remain High-Z and the device draws minimal current from the supply pin (IVMQ or IVCCQ). After any of the input pins are set high for longer than the duration of tWAKE, the device becomes fully operational. shows an example timing diagram for entering and leaving sleep mode.SLEEPDRV8213VMQVCCQWAKE Sleep Mode Entry and Wakeup Timing Diagram Sleep Mode Entry and Wakeup Timing Diagram Fault Mode The DRV8213 device enters fault mode when it encounters a fault condition. This protects the device and the load on the outputs. #GUID-90C13FD3-9C45-47A3-BAD8-32CCD4E329AF/SLVSAR19411 describes the device behavior in the fault mode which depends on the fault condition. The device will leave the fault mode and re-enter the active mode when the system meets the recovery condition. Fault Conditions Summary FAULT FAULT CONDITION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (UVLO), DSG VVM < VUVLO_VM Falling nFAULT Disabled Disabled VVM > VUVLO_VM Rising VCC undervoltage (UVLO), RTE VVCC < VUVLO_VCC Falling nFAULT Disabled Disabled VVCC > VUVLO_VCC Rising Overcurrent (OCP) IOUT > IOCP nFAULT Disabled Operating IOUT < IOCP Thermal Shutdown (TSD) TJ > TTSD nFAULT Disabled Operating TJ < TTSD – THYS Fault Mode The DRV8213 device enters fault mode when it encounters a fault condition. This protects the device and the load on the outputs. #GUID-90C13FD3-9C45-47A3-BAD8-32CCD4E329AF/SLVSAR19411 describes the device behavior in the fault mode which depends on the fault condition. The device will leave the fault mode and re-enter the active mode when the system meets the recovery condition. Fault Conditions Summary FAULT FAULT CONDITION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (UVLO), DSG VVM < VUVLO_VM Falling nFAULT Disabled Disabled VVM > VUVLO_VM Rising VCC undervoltage (UVLO), RTE VVCC < VUVLO_VCC Falling nFAULT Disabled Disabled VVCC > VUVLO_VCC Rising Overcurrent (OCP) IOUT > IOCP nFAULT Disabled Operating IOUT < IOCP Thermal Shutdown (TSD) TJ > TTSD nFAULT Disabled Operating TJ < TTSD – THYS The DRV8213 device enters fault mode when it encounters a fault condition. This protects the device and the load on the outputs. #GUID-90C13FD3-9C45-47A3-BAD8-32CCD4E329AF/SLVSAR19411 describes the device behavior in the fault mode which depends on the fault condition. The device will leave the fault mode and re-enter the active mode when the system meets the recovery condition. Fault Conditions Summary FAULT FAULT CONDITION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (UVLO), DSG VVM < VUVLO_VM Falling nFAULT Disabled Disabled VVM > VUVLO_VM Rising VCC undervoltage (UVLO), RTE VVCC < VUVLO_VCC Falling nFAULT Disabled Disabled VVCC > VUVLO_VCC Rising Overcurrent (OCP) IOUT > IOCP nFAULT Disabled Operating IOUT < IOCP Thermal Shutdown (TSD) TJ > TTSD nFAULT Disabled Operating TJ < TTSD – THYS The DRV8213 device enters fault mode when it encounters a fault condition. This protects the device and the load on the outputs. #GUID-90C13FD3-9C45-47A3-BAD8-32CCD4E329AF/SLVSAR19411 describes the device behavior in the fault mode which depends on the fault condition. The device will leave the fault mode and re-enter the active mode when the system meets the recovery condition.DRV8213#GUID-90C13FD3-9C45-47A3-BAD8-32CCD4E329AF/SLVSAR19411 Fault Conditions Summary FAULT FAULT CONDITION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (UVLO), DSG VVM < VUVLO_VM Falling nFAULT Disabled Disabled VVM > VUVLO_VM Rising VCC undervoltage (UVLO), RTE VVCC < VUVLO_VCC Falling nFAULT Disabled Disabled VVCC > VUVLO_VCC Rising Overcurrent (OCP) IOUT > IOCP nFAULT Disabled Operating IOUT < IOCP Thermal Shutdown (TSD) TJ > TTSD nFAULT Disabled Operating TJ < TTSD – THYS Fault Conditions Summary FAULT FAULT CONDITION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION VM undervoltage (UVLO), DSG VVM < VUVLO_VM Falling nFAULT Disabled Disabled VVM > VUVLO_VM Rising VCC undervoltage (UVLO), RTE VVCC < VUVLO_VCC Falling nFAULT Disabled Disabled VVCC > VUVLO_VCC Rising Overcurrent (OCP) IOUT > IOCP nFAULT Disabled Operating IOUT < IOCP Thermal Shutdown (TSD) TJ > TTSD nFAULT Disabled Operating TJ < TTSD – THYS FAULT FAULT CONDITION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION FAULT FAULT CONDITION ERROR REPORT FULL-BRIDGE INTERNAL CIRCUITS RECOVERY CONDITION FAULTFAULT CONDITION ERROR REPORT ERROR REPORTFULL-BRIDGEINTERNAL CIRCUITSRECOVERY CONDITION VM undervoltage (UVLO), DSG VVM < VUVLO_VM Falling nFAULT Disabled Disabled VVM > VUVLO_VM Rising VCC undervoltage (UVLO), RTE VVCC < VUVLO_VCC Falling nFAULT Disabled Disabled VVCC > VUVLO_VCC Rising Overcurrent (OCP) IOUT > IOCP nFAULT Disabled Operating IOUT < IOCP Thermal Shutdown (TSD) TJ > TTSD nFAULT Disabled Operating TJ < TTSD – THYS VM undervoltage (UVLO), DSG VVM < VUVLO_VM Falling nFAULT Disabled Disabled VVM > VUVLO_VM Rising VM undervoltage (UVLO), DSGVVM < VUVLO_VM FallingVMUVLO_VM nFAULT nFAULTDisabledDisabledVVM > VUVLO_VM RisingVMUVLO_VM VCC undervoltage (UVLO), RTE VVCC < VUVLO_VCC Falling nFAULT Disabled Disabled VVCC > VUVLO_VCC Rising VCC undervoltage (UVLO), RTEVVCC < VUVLO_VCC FallingVCCUVLO_VCC nFAULT nFAULTDisabledDisabledVVCC > VUVLO_VCC RisingVCCUVLO_VCC Overcurrent (OCP) IOUT > IOCP nFAULT Disabled Operating IOUT < IOCP Overcurrent (OCP)IOUT > IOCP OUTOCP nFAULT nFAULTDisabledOperatingIOUT < IOCP OUTOCP Thermal Shutdown (TSD) TJ > TTSD nFAULT Disabled Operating TJ < TTSD – THYS Thermal Shutdown (TSD)TJ > TTSD JTSD nFAULT nFAULTDisabledOperatingTJ < TTSD – THYS JTSDHYS Pin Diagrams Logic-Level Inputs shows the input structure for the logic-level input pins IN1 and IN2. Logic-level input Tri-Level Input shows the input structure for the tri-level input pins, GAINSEL, IMODE and SMODE. Tri-level input Pin Diagrams Logic-Level Inputs shows the input structure for the logic-level input pins IN1 and IN2. Logic-level input Logic-Level Inputs shows the input structure for the logic-level input pins IN1 and IN2. Logic-level input shows the input structure for the logic-level input pins IN1 and IN2. Logic-level input shows the input structure for the logic-level input pins IN1 and IN2. Logic-level input Logic-level input Tri-Level Input shows the input structure for the tri-level input pins, GAINSEL, IMODE and SMODE. Tri-level input Tri-Level Input shows the input structure for the tri-level input pins, GAINSEL, IMODE and SMODE. Tri-level input shows the input structure for the tri-level input pins, GAINSEL, IMODE and SMODE. Tri-level input shows the input structure for the tri-level input pins, GAINSEL, IMODE and SMODE. Tri-level input Tri-level input Application and Implementation Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. Application Information The DRV8213 is intended to drive one brushed DC motor. Typical Application Brushed DC Motor A typical application for the DRV8213 is to drive a brushed DC motor using the full-bridge outputs. shows an example schematic using the DSG package for driving a motor and controlling the driver from a microcontroller (MCU). shows a schematic example using the RTE package with stall detection disabled. The resistor on the IPROPI pin can provide a voltage signal to the microcontroller analog-to-digital converter (ADC). Typical Connections for DSG variant Typical Connections for RTE variant with stall detection disabled Design Requirements #GUID-1DFAB0A4-875D-4F8B-A58B-4A48AAE30D80/TABLE_TLV_MKS_SNB lists example design parameters. Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2.1 A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Detailed Design Procedure Motor Voltage The motor voltage to use depends on the ratings of the motor selected and the desired RPM. A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive motor windings. Motor Current Motors experience large currents at low speed, initial startup, and stalled rotor conditions. The large current at motor startup is sometimes called inrush current. The current regulation feature in the DRV8213 can help to limit these large currents. Alternatively, the microcontroller may limit the inrush current by ramping the PWM duty cycle during the startup time. Stall Detection Some applications require stall detection to notify the microcontroller of a locked-rotor/stall condition. A stall could be caused by one of two things: unintended mechanical blockage or the load reaching an end-stop in a constrained travel path. The DRV8213 supports two methods for determing a stall conditions: hardware stall detection and software stall detection. The RTE package supports hardware stall detection by providing additional pins to configure the response of the device to a stall condition as shown in . Both DSG and RTE packages support software stall detection by providing the IPROPI analog current sense feedback to the ADC of a microcontroller as shown in and . Typical Connections for RTE variant with stall detection enabled Detailed Design Procedure Hardware Stall Detection Application Description The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8213 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The capacitor on the TINRUSH pin sets the timing, tINRUSH, so the DRV8213 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8213 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nSTALL pulls low to indicate the stall event to the microcontroller. provides full details for configuring the stall detection feature. Example timing diagram for hardware stall detection summarizes stall detection configuration. Summary table for hardware stall detection pin configuration nSTALL TINRUSH SMODE Description GND Z X Stall detection disabled. Float TINRUSH. If IMODE = Z, current regulation occurs at all times when VIPROPI ≥ VVREF. Pull-up resistor to VCC GND X TI does not recommend this configuration. tINRUSH corresponds to approximately 6.7s. Device continuously sources 10 uA out of TINRUSH pin into GND. If IMODE = Z, current regulation occurs when VIPROPI ≥ VVREF. Capacitor to GND 0 Latched disable with indication: the OUTx pins disable and the nSTALL pin pulls low after tINRUSH when VIPROPI ≥ VVREF. 1/ Z Indication only: the OUTx pins remain active and the nSTALL pin pulls low after tINRUSH when VIPROPI ≥ VVREF. Z X TI does not recommend this configuration. Floating TINRUSH pin effectively sets tINRUSH = 0 seconds.The device responds according to the settings of SMODE and IMODE at all times when VIPROPI ≥ VVREF. VCC X TI does not recommend this configuration. Tying TINRUSH to a voltage higher than 1 V effectively sets tINRUSH = 0 seconds. The device draws excessive current from the voltage source due to the TINRUSH discharge path being on. Hardware Stall Detection Timing Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8213 integrates a timing circuit in the RTE package variant to ignore the inrush current during the startup time, tINRUSH. The timing circuit is configured using a capactior, CINRUSH, on the TINRUSH pin. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8213 and the system overall. #GUID-4A192769-F52B-4F35-9C38-238F0D2A0D89/EQUATION-BLOCK_F1X_S14_JTB defines the minimum tINRUSH time, tINRUSH_min. The timing tINRUSH_motor should be determined experimentally because it depends on motor parameters, supply voltage, temperature, and mechanical load response times. The ϵTINRUSH term accounts for tolerances in the TINRUSH timing circuit and the CINRUSH capacitor. t I N R U S H _ m i n = t I N R U S H _ m o t o r × 1 + ϵ T I N R U S H #GUID-4A192769-F52B-4F35-9C38-238F0D2A0D89/EQUATION-BLOCK_I54_HB4_JTB shows the expression for finding ϵTINRUSH. The tolerance of the 1-V reference on the TINRUSH pin is ϵVTINRUSH_trip. This tolerance is 3%, as defined by the minimum and maximum specifications for VTINRUSH_trip in the Electrical Characteristics table. The tolerance of the 10-µA current source on the TINRUSH pin is ϵITINRUSH. This tolerance is 20%, as defined by the minimum and maximum specifications for ITINRUSH in the Electrical Characteristics table. The tolerance of the CINRUSH capacitor is ϵCINRUSH. This is a percentage defined by the tolerance of the selected CINRUSH capacitor. ϵ T I N R U S H = ϵ V T I N R U S H _ t r i p 2 + ϵ I T I N R U S H 2 + ϵ C I N R U S H 2 For example, assume tINRUSH_motor = 100 ms and a capacitor with 1% tolerance will be used for CINRUSH. In this case, it can be calculated that the CINRUSH capacitor should be larger than 18.5 nF, so a 22 nF capacitor will be sufficient in this application. Hardware Stall Threshold Selection The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. and provide more details for configuring the voltage on the VREF pin. Software Stall Detection Application Description The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . To implement stall detection, the microcontroller reads the voltage on the IPROPI pin using an ADC and compares it to a stall threshold set in firmware. Alternatively, a comparator peripheral may be used to set this threshold. Motor Current Profile with STALL Signal Software Stall Detection Timing The microcontroller needs to decide whether or not the IPROPI signal indicates a motor stall. Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. Do not mistake the inrush current for a stall condition. One way to do this is for the microcontroller to ignore the IPROPI signal above the firmware stall threshold for the duration of the inrush current, tINRUSH, at startup. The tINRUSH timing is determined experimentally using the motor parameters, supply voltage, and mechanical load response times. When a stall condition occurs, the motor current increases from the average running current level because the back EMF is now 0 V. In some cases, it may be desirable to drive at the stall curent for some time in case the motor can clear the blockage on its own. This might be useful for an unintended stall or high-torque condition on the motor. In this case, the system designer can choose a long stall detection time, tSTALL, before the microcontroller decides to take action. In other cases, like end-stop detection, a faster response might be desired to reduce power or minimize strong motor torque on the gears or end-stop. This corresponds to setting a shorter tSTALL time in the microcontroller. illustrates the tINRUSH and tSTALL timings and how they relate to the motor current waveform. Software Stall Threshold Selection The stall detection threshold in firmware should be chosen at a current level between the maximum stall current and the average running current of the motor as shown in . Application Curves PWM Operation at VM = 1.65 V Traces from top to bottom: IN1 (6 V/div), OUT2 (5 V/div), VIPROPI (600 mV/div), Motor Current (100 mA/div) PWM Operation at VM = 5 V Traces from top to bottom: OUT1 (10 V/div), OUT2 (10 V/div), Motor Current (1 A/div), VIPROPI (50 mV/div) PWM Operation at VM = 11 V Traces from top to bottom: IN1 (7 V/div), OUT2 (6 V/div), Motor Current (200 mA/div), VIPROPI (2 V/div) Stall Detection with IMODE = Hi-Z, SMODE = 1 Traces from top to bottom: nSTALL (4 V/div), TINRUSH (1 V/div), OUT2 (5 V/div), Motor Current (600 mA/div) Thermal Performance The datasheet-specified junction-to-ambient thermal resistance, RθJA, is primarily useful for comparing various drivers or approximating thermal performance. However, the actual system performance may be better or worse than this value depending on PCB stackup, routing, number of vias, and copper area around the thermal pad. The length of time the driver drives a particular current will also impact power dissipation and thermal performance. This section considers how to design for steady-state and transient thermal conditions. The data in this section was simulated using the following criteria: WSON (DSG package) 2-layer PCB (size 114.3 x 76.2 x 1.6 mm), standard FR4, 1-oz (35 mm copper thickness) or 2-oz copper thickness. Thermal vias are only present under the thermal pad (2 vias, 1.2mm spacing, 0.3 mm diameter, 0.025 mm Cu plating). Top layer: DRV8213 WSON package footprint and copper plane heatsink. Top layer copper area is varied in simulation. Bottom layer: ground plane thermally connected through vias under the thermal pad for DRV8213. Bottom layer copper area varies with top copper area. 4-layer PCB (size 114.3 x 76.2 x 1.6 mm), standard FR4. Outer planes are 1-oz (35 mm copper thickness) or 2-oz copper thickness. Inner planes are kept at 1-oz. Thermal vias are only present under the thermal pad (2 vias, 1.2mm spacing, 0.3 mm diameter, 0.025 mm Cu plating). Top layer: DRV8213 WSON package footprint and copper plane heatsink. Top layer copper area is varied in simulation. Mid layer 1: GND plane thermally connected to DRV8213 thermal pad through vias. The area of the ground plane is 74.2 mm x 74.2 mm. Mid layer 2: power plane, no thermal connection. The area of the power plane is 74.2 mm x 74.2 mm. Bottom layer: ground plane thermally connected through via stitching from the TOP and internal GND planes. Bottom layer copper area varies with top copper area. shows an example of the simulated board for the DSG package. shows the dimensions of the board that were varied for each simulation. WSON PCB model top layer Dimension A for 8-pin DSG package Cu area (mm2) Dimension A (mm) 2 15.11 4 20.98 8 29.27 16 40.99 WQFN (RTE package) 2-layer PCB (size 114.3 x 76.2 x 1.6 mm), standard FR4, 1-oz (35 mm copper thickness) or 2-oz copper thickness. Thermal vias are only present under the package footprint (5 vias, 1 mm pitch, 0.2 mm diameter, 0.025 mm Cu plating). Top layer: WQFN package footprint and traces. Bottom layer: ground plane thermally connected through vias under the package footprint. Bottom layer copper area is varied in simulation. 4-layer PCB (size 114.3 x 76.2 x 1.6 mm), standard FR4. Outer planes are 1-oz (35 mm copper thickness) or 2-oz copper thickness. Inner planes are kept at 1-oz. Thermal vias are only present under the package footprint (5 vias, 1 mm pitch, 0.2 mm diameter, 0.025 mm Cu plating). Top layer: WQFN package footprint and traces. Mid layer 1: GND plane thermally connected under package footprint through vias. The area of the ground plane is 74.2 mm x 74.2 mm. Mid layer 2: power plane, no thermal connection. The area of the power plane is 74.2 mm x 74.2 mm. Bottom layer: signal layer with small copper pad underneath the driver and thermally connected through via stitching from the TOP and internal GND plane. Bottom layer thermal pad is the same size as the package (3 mm x 3 mm). Bottom pad size remains constant. shows an example of the simulated board for the WQFN package. shows the dimensions of the board that were varied for each simulation. WQFN PCB model top layer Dimension A for 16-pin RTE package Cu area (cm2) Dimension A (mm) 2 14.14 4 20.00 8 28.28 16 40.00 Steady-State Thermal Performance "Steady-state" conditions assume that the motor driver operates with a constant RMS current over a long period of time. The figures in this section show how RθJA and ΨJB (junction-to-board characterization parameter) change depending on copper area, copper thickness, and number of layers of the PCB. More copper area, more layers, and thicker copper planes decrease RθJA and ΨJB, which indicate better thermal performance from the PCB layout. WSON, PCB junction-to-ambient thermal resistance vs copper area WSON, junction-to-board characterization parameter vs copper area WQFN, PCB junction-to-ambient thermal resistance vs copper area WQFN, junction-to-board characterization parameter vs copper area Transient Thermal Performance The motor driver may experience different transient driving conditions that cause large currents to flow for a short duration of time. These may include - Motor start-up when the rotor is initially stationary. Fault conditions when there is a supply or ground short to one of the motor outputs, and the overcurrent protection triggers. Briefly energizing a motor or solenoid for a limited time, then de-energizing. For these transient cases, the duration of drive time is another factor that impacts thermal performance in addition to copper area and thickness. In transient cases, the thermal impedance parameter ZθJA denotes the junction-to-ambient thermal performance. The figures in this section show the simulated thermal impedances for 1-oz and 2-oz copper layouts for the WSON and WQFN packages. These graphs indicate better thermal performance with short current pulses. For short periods of drive time, the device die size and package dominates the thermal performance. For longer drive pulses, board layout has a more significant impact on thermal performance. Both graphs show the curves for thermal impedance split due to number of layers and copper area as the duration of the drive pulse duration increases. Long pulses can be considered steady-state performance. WSON package junction-to-ambient thermal impedance for 1-oz copper layouts WSON package junction-to-ambient thermal impedance for 2-oz copper layouts WQFN package junction-to-ambient thermal impedance for 1-oz copper layouts WQFN package junction-to-ambient thermal impedance for 2-oz copper layouts Application and Implementation Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. Application Information The DRV8213 is intended to drive one brushed DC motor. Application Information The DRV8213 is intended to drive one brushed DC motor. The DRV8213 is intended to drive one brushed DC motor. The DRV8213 is intended to drive one brushed DC motor.DRV8213 Typical Application Brushed DC Motor A typical application for the DRV8213 is to drive a brushed DC motor using the full-bridge outputs. shows an example schematic using the DSG package for driving a motor and controlling the driver from a microcontroller (MCU). shows a schematic example using the RTE package with stall detection disabled. The resistor on the IPROPI pin can provide a voltage signal to the microcontroller analog-to-digital converter (ADC). Typical Connections for DSG variant Typical Connections for RTE variant with stall detection disabled Design Requirements #GUID-1DFAB0A4-875D-4F8B-A58B-4A48AAE30D80/TABLE_TLV_MKS_SNB lists example design parameters. Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2.1 A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Detailed Design Procedure Motor Voltage The motor voltage to use depends on the ratings of the motor selected and the desired RPM. A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive motor windings. Motor Current Motors experience large currents at low speed, initial startup, and stalled rotor conditions. The large current at motor startup is sometimes called inrush current. The current regulation feature in the DRV8213 can help to limit these large currents. Alternatively, the microcontroller may limit the inrush current by ramping the PWM duty cycle during the startup time. Stall Detection Some applications require stall detection to notify the microcontroller of a locked-rotor/stall condition. A stall could be caused by one of two things: unintended mechanical blockage or the load reaching an end-stop in a constrained travel path. The DRV8213 supports two methods for determing a stall conditions: hardware stall detection and software stall detection. The RTE package supports hardware stall detection by providing additional pins to configure the response of the device to a stall condition as shown in . Both DSG and RTE packages support software stall detection by providing the IPROPI analog current sense feedback to the ADC of a microcontroller as shown in and . Typical Connections for RTE variant with stall detection enabled Detailed Design Procedure Hardware Stall Detection Application Description The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8213 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The capacitor on the TINRUSH pin sets the timing, tINRUSH, so the DRV8213 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8213 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nSTALL pulls low to indicate the stall event to the microcontroller. provides full details for configuring the stall detection feature. Example timing diagram for hardware stall detection summarizes stall detection configuration. Summary table for hardware stall detection pin configuration nSTALL TINRUSH SMODE Description GND Z X Stall detection disabled. Float TINRUSH. If IMODE = Z, current regulation occurs at all times when VIPROPI ≥ VVREF. Pull-up resistor to VCC GND X TI does not recommend this configuration. tINRUSH corresponds to approximately 6.7s. Device continuously sources 10 uA out of TINRUSH pin into GND. If IMODE = Z, current regulation occurs when VIPROPI ≥ VVREF. Capacitor to GND 0 Latched disable with indication: the OUTx pins disable and the nSTALL pin pulls low after tINRUSH when VIPROPI ≥ VVREF. 1/ Z Indication only: the OUTx pins remain active and the nSTALL pin pulls low after tINRUSH when VIPROPI ≥ VVREF. Z X TI does not recommend this configuration. Floating TINRUSH pin effectively sets tINRUSH = 0 seconds.The device responds according to the settings of SMODE and IMODE at all times when VIPROPI ≥ VVREF. VCC X TI does not recommend this configuration. Tying TINRUSH to a voltage higher than 1 V effectively sets tINRUSH = 0 seconds. The device draws excessive current from the voltage source due to the TINRUSH discharge path being on. Hardware Stall Detection Timing Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8213 integrates a timing circuit in the RTE package variant to ignore the inrush current during the startup time, tINRUSH. The timing circuit is configured using a capactior, CINRUSH, on the TINRUSH pin. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8213 and the system overall. #GUID-4A192769-F52B-4F35-9C38-238F0D2A0D89/EQUATION-BLOCK_F1X_S14_JTB defines the minimum tINRUSH time, tINRUSH_min. The timing tINRUSH_motor should be determined experimentally because it depends on motor parameters, supply voltage, temperature, and mechanical load response times. The ϵTINRUSH term accounts for tolerances in the TINRUSH timing circuit and the CINRUSH capacitor. t I N R U S H _ m i n = t I N R U S H _ m o t o r × 1 + ϵ T I N R U S H #GUID-4A192769-F52B-4F35-9C38-238F0D2A0D89/EQUATION-BLOCK_I54_HB4_JTB shows the expression for finding ϵTINRUSH. The tolerance of the 1-V reference on the TINRUSH pin is ϵVTINRUSH_trip. This tolerance is 3%, as defined by the minimum and maximum specifications for VTINRUSH_trip in the Electrical Characteristics table. The tolerance of the 10-µA current source on the TINRUSH pin is ϵITINRUSH. This tolerance is 20%, as defined by the minimum and maximum specifications for ITINRUSH in the Electrical Characteristics table. The tolerance of the CINRUSH capacitor is ϵCINRUSH. This is a percentage defined by the tolerance of the selected CINRUSH capacitor. ϵ T I N R U S H = ϵ V T I N R U S H _ t r i p 2 + ϵ I T I N R U S H 2 + ϵ C I N R U S H 2 For example, assume tINRUSH_motor = 100 ms and a capacitor with 1% tolerance will be used for CINRUSH. In this case, it can be calculated that the CINRUSH capacitor should be larger than 18.5 nF, so a 22 nF capacitor will be sufficient in this application. Hardware Stall Threshold Selection The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. and provide more details for configuring the voltage on the VREF pin. Software Stall Detection Application Description The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . To implement stall detection, the microcontroller reads the voltage on the IPROPI pin using an ADC and compares it to a stall threshold set in firmware. Alternatively, a comparator peripheral may be used to set this threshold. Motor Current Profile with STALL Signal Software Stall Detection Timing The microcontroller needs to decide whether or not the IPROPI signal indicates a motor stall. Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. Do not mistake the inrush current for a stall condition. One way to do this is for the microcontroller to ignore the IPROPI signal above the firmware stall threshold for the duration of the inrush current, tINRUSH, at startup. The tINRUSH timing is determined experimentally using the motor parameters, supply voltage, and mechanical load response times. When a stall condition occurs, the motor current increases from the average running current level because the back EMF is now 0 V. In some cases, it may be desirable to drive at the stall curent for some time in case the motor can clear the blockage on its own. This might be useful for an unintended stall or high-torque condition on the motor. In this case, the system designer can choose a long stall detection time, tSTALL, before the microcontroller decides to take action. In other cases, like end-stop detection, a faster response might be desired to reduce power or minimize strong motor torque on the gears or end-stop. This corresponds to setting a shorter tSTALL time in the microcontroller. illustrates the tINRUSH and tSTALL timings and how they relate to the motor current waveform. Software Stall Threshold Selection The stall detection threshold in firmware should be chosen at a current level between the maximum stall current and the average running current of the motor as shown in . Application Curves PWM Operation at VM = 1.65 V Traces from top to bottom: IN1 (6 V/div), OUT2 (5 V/div), VIPROPI (600 mV/div), Motor Current (100 mA/div) PWM Operation at VM = 5 V Traces from top to bottom: OUT1 (10 V/div), OUT2 (10 V/div), Motor Current (1 A/div), VIPROPI (50 mV/div) PWM Operation at VM = 11 V Traces from top to bottom: IN1 (7 V/div), OUT2 (6 V/div), Motor Current (200 mA/div), VIPROPI (2 V/div) Stall Detection with IMODE = Hi-Z, SMODE = 1 Traces from top to bottom: nSTALL (4 V/div), TINRUSH (1 V/div), OUT2 (5 V/div), Motor Current (600 mA/div) Thermal Performance The datasheet-specified junction-to-ambient thermal resistance, RθJA, is primarily useful for comparing various drivers or approximating thermal performance. However, the actual system performance may be better or worse than this value depending on PCB stackup, routing, number of vias, and copper area around the thermal pad. The length of time the driver drives a particular current will also impact power dissipation and thermal performance. This section considers how to design for steady-state and transient thermal conditions. The data in this section was simulated using the following criteria: WSON (DSG package) 2-layer PCB (size 114.3 x 76.2 x 1.6 mm), standard FR4, 1-oz (35 mm copper thickness) or 2-oz copper thickness. Thermal vias are only present under the thermal pad (2 vias, 1.2mm spacing, 0.3 mm diameter, 0.025 mm Cu plating). Top layer: DRV8213 WSON package footprint and copper plane heatsink. Top layer copper area is varied in simulation. Bottom layer: ground plane thermally connected through vias under the thermal pad for DRV8213. Bottom layer copper area varies with top copper area. 4-layer PCB (size 114.3 x 76.2 x 1.6 mm), standard FR4. Outer planes are 1-oz (35 mm copper thickness) or 2-oz copper thickness. Inner planes are kept at 1-oz. Thermal vias are only present under the thermal pad (2 vias, 1.2mm spacing, 0.3 mm diameter, 0.025 mm Cu plating). Top layer: DRV8213 WSON package footprint and copper plane heatsink. Top layer copper area is varied in simulation. Mid layer 1: GND plane thermally connected to DRV8213 thermal pad through vias. The area of the ground plane is 74.2 mm x 74.2 mm. Mid layer 2: power plane, no thermal connection. The area of the power plane is 74.2 mm x 74.2 mm. Bottom layer: ground plane thermally connected through via stitching from the TOP and internal GND planes. Bottom layer copper area varies with top copper area. shows an example of the simulated board for the DSG package. shows the dimensions of the board that were varied for each simulation. WSON PCB model top layer Dimension A for 8-pin DSG package Cu area (mm2) Dimension A (mm) 2 15.11 4 20.98 8 29.27 16 40.99 WQFN (RTE package) 2-layer PCB (size 114.3 x 76.2 x 1.6 mm), standard FR4, 1-oz (35 mm copper thickness) or 2-oz copper thickness. Thermal vias are only present under the package footprint (5 vias, 1 mm pitch, 0.2 mm diameter, 0.025 mm Cu plating). Top layer: WQFN package footprint and traces. Bottom layer: ground plane thermally connected through vias under the package footprint. Bottom layer copper area is varied in simulation. 4-layer PCB (size 114.3 x 76.2 x 1.6 mm), standard FR4. Outer planes are 1-oz (35 mm copper thickness) or 2-oz copper thickness. Inner planes are kept at 1-oz. Thermal vias are only present under the package footprint (5 vias, 1 mm pitch, 0.2 mm diameter, 0.025 mm Cu plating). Top layer: WQFN package footprint and traces. Mid layer 1: GND plane thermally connected under package footprint through vias. The area of the ground plane is 74.2 mm x 74.2 mm. Mid layer 2: power plane, no thermal connection. The area of the power plane is 74.2 mm x 74.2 mm. Bottom layer: signal layer with small copper pad underneath the driver and thermally connected through via stitching from the TOP and internal GND plane. Bottom layer thermal pad is the same size as the package (3 mm x 3 mm). Bottom pad size remains constant. shows an example of the simulated board for the WQFN package. shows the dimensions of the board that were varied for each simulation. WQFN PCB model top layer Dimension A for 16-pin RTE package Cu area (cm2) Dimension A (mm) 2 14.14 4 20.00 8 28.28 16 40.00 Steady-State Thermal Performance "Steady-state" conditions assume that the motor driver operates with a constant RMS current over a long period of time. The figures in this section show how RθJA and ΨJB (junction-to-board characterization parameter) change depending on copper area, copper thickness, and number of layers of the PCB. More copper area, more layers, and thicker copper planes decrease RθJA and ΨJB, which indicate better thermal performance from the PCB layout. WSON, PCB junction-to-ambient thermal resistance vs copper area WSON, junction-to-board characterization parameter vs copper area WQFN, PCB junction-to-ambient thermal resistance vs copper area WQFN, junction-to-board characterization parameter vs copper area Transient Thermal Performance The motor driver may experience different transient driving conditions that cause large currents to flow for a short duration of time. These may include - Motor start-up when the rotor is initially stationary. Fault conditions when there is a supply or ground short to one of the motor outputs, and the overcurrent protection triggers. Briefly energizing a motor or solenoid for a limited time, then de-energizing. For these transient cases, the duration of drive time is another factor that impacts thermal performance in addition to copper area and thickness. In transient cases, the thermal impedance parameter ZθJA denotes the junction-to-ambient thermal performance. The figures in this section show the simulated thermal impedances for 1-oz and 2-oz copper layouts for the WSON and WQFN packages. These graphs indicate better thermal performance with short current pulses. For short periods of drive time, the device die size and package dominates the thermal performance. For longer drive pulses, board layout has a more significant impact on thermal performance. Both graphs show the curves for thermal impedance split due to number of layers and copper area as the duration of the drive pulse duration increases. Long pulses can be considered steady-state performance. WSON package junction-to-ambient thermal impedance for 1-oz copper layouts WSON package junction-to-ambient thermal impedance for 2-oz copper layouts WQFN package junction-to-ambient thermal impedance for 1-oz copper layouts WQFN package junction-to-ambient thermal impedance for 2-oz copper layouts Typical Application Brushed DC Motor A typical application for the DRV8213 is to drive a brushed DC motor using the full-bridge outputs. shows an example schematic using the DSG package for driving a motor and controlling the driver from a microcontroller (MCU). shows a schematic example using the RTE package with stall detection disabled. The resistor on the IPROPI pin can provide a voltage signal to the microcontroller analog-to-digital converter (ADC). Typical Connections for DSG variant Typical Connections for RTE variant with stall detection disabled Design Requirements #GUID-1DFAB0A4-875D-4F8B-A58B-4A48AAE30D80/TABLE_TLV_MKS_SNB lists example design parameters. Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2.1 A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Detailed Design Procedure Motor Voltage The motor voltage to use depends on the ratings of the motor selected and the desired RPM. A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive motor windings. Motor Current Motors experience large currents at low speed, initial startup, and stalled rotor conditions. The large current at motor startup is sometimes called inrush current. The current regulation feature in the DRV8213 can help to limit these large currents. Alternatively, the microcontroller may limit the inrush current by ramping the PWM duty cycle during the startup time. Stall Detection Some applications require stall detection to notify the microcontroller of a locked-rotor/stall condition. A stall could be caused by one of two things: unintended mechanical blockage or the load reaching an end-stop in a constrained travel path. The DRV8213 supports two methods for determing a stall conditions: hardware stall detection and software stall detection. The RTE package supports hardware stall detection by providing additional pins to configure the response of the device to a stall condition as shown in . Both DSG and RTE packages support software stall detection by providing the IPROPI analog current sense feedback to the ADC of a microcontroller as shown in and . Typical Connections for RTE variant with stall detection enabled Detailed Design Procedure Hardware Stall Detection Application Description The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8213 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The capacitor on the TINRUSH pin sets the timing, tINRUSH, so the DRV8213 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8213 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nSTALL pulls low to indicate the stall event to the microcontroller. provides full details for configuring the stall detection feature. Example timing diagram for hardware stall detection summarizes stall detection configuration. Summary table for hardware stall detection pin configuration nSTALL TINRUSH SMODE Description GND Z X Stall detection disabled. Float TINRUSH. If IMODE = Z, current regulation occurs at all times when VIPROPI ≥ VVREF. Pull-up resistor to VCC GND X TI does not recommend this configuration. tINRUSH corresponds to approximately 6.7s. Device continuously sources 10 uA out of TINRUSH pin into GND. If IMODE = Z, current regulation occurs when VIPROPI ≥ VVREF. Capacitor to GND 0 Latched disable with indication: the OUTx pins disable and the nSTALL pin pulls low after tINRUSH when VIPROPI ≥ VVREF. 1/ Z Indication only: the OUTx pins remain active and the nSTALL pin pulls low after tINRUSH when VIPROPI ≥ VVREF. Z X TI does not recommend this configuration. Floating TINRUSH pin effectively sets tINRUSH = 0 seconds.The device responds according to the settings of SMODE and IMODE at all times when VIPROPI ≥ VVREF. VCC X TI does not recommend this configuration. Tying TINRUSH to a voltage higher than 1 V effectively sets tINRUSH = 0 seconds. The device draws excessive current from the voltage source due to the TINRUSH discharge path being on. Hardware Stall Detection Timing Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8213 integrates a timing circuit in the RTE package variant to ignore the inrush current during the startup time, tINRUSH. The timing circuit is configured using a capactior, CINRUSH, on the TINRUSH pin. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8213 and the system overall. #GUID-4A192769-F52B-4F35-9C38-238F0D2A0D89/EQUATION-BLOCK_F1X_S14_JTB defines the minimum tINRUSH time, tINRUSH_min. The timing tINRUSH_motor should be determined experimentally because it depends on motor parameters, supply voltage, temperature, and mechanical load response times. The ϵTINRUSH term accounts for tolerances in the TINRUSH timing circuit and the CINRUSH capacitor. t I N R U S H _ m i n = t I N R U S H _ m o t o r × 1 + ϵ T I N R U S H #GUID-4A192769-F52B-4F35-9C38-238F0D2A0D89/EQUATION-BLOCK_I54_HB4_JTB shows the expression for finding ϵTINRUSH. The tolerance of the 1-V reference on the TINRUSH pin is ϵVTINRUSH_trip. This tolerance is 3%, as defined by the minimum and maximum specifications for VTINRUSH_trip in the Electrical Characteristics table. The tolerance of the 10-µA current source on the TINRUSH pin is ϵITINRUSH. This tolerance is 20%, as defined by the minimum and maximum specifications for ITINRUSH in the Electrical Characteristics table. The tolerance of the CINRUSH capacitor is ϵCINRUSH. This is a percentage defined by the tolerance of the selected CINRUSH capacitor. ϵ T I N R U S H = ϵ V T I N R U S H _ t r i p 2 + ϵ I T I N R U S H 2 + ϵ C I N R U S H 2 For example, assume tINRUSH_motor = 100 ms and a capacitor with 1% tolerance will be used for CINRUSH. In this case, it can be calculated that the CINRUSH capacitor should be larger than 18.5 nF, so a 22 nF capacitor will be sufficient in this application. Hardware Stall Threshold Selection The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. and provide more details for configuring the voltage on the VREF pin. Software Stall Detection Application Description The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . To implement stall detection, the microcontroller reads the voltage on the IPROPI pin using an ADC and compares it to a stall threshold set in firmware. Alternatively, a comparator peripheral may be used to set this threshold. Motor Current Profile with STALL Signal Software Stall Detection Timing The microcontroller needs to decide whether or not the IPROPI signal indicates a motor stall. Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. Do not mistake the inrush current for a stall condition. One way to do this is for the microcontroller to ignore the IPROPI signal above the firmware stall threshold for the duration of the inrush current, tINRUSH, at startup. The tINRUSH timing is determined experimentally using the motor parameters, supply voltage, and mechanical load response times. When a stall condition occurs, the motor current increases from the average running current level because the back EMF is now 0 V. In some cases, it may be desirable to drive at the stall curent for some time in case the motor can clear the blockage on its own. This might be useful for an unintended stall or high-torque condition on the motor. In this case, the system designer can choose a long stall detection time, tSTALL, before the microcontroller decides to take action. In other cases, like end-stop detection, a faster response might be desired to reduce power or minimize strong motor torque on the gears or end-stop. This corresponds to setting a shorter tSTALL time in the microcontroller. illustrates the tINRUSH and tSTALL timings and how they relate to the motor current waveform. Software Stall Threshold Selection The stall detection threshold in firmware should be chosen at a current level between the maximum stall current and the average running current of the motor as shown in . Application Curves PWM Operation at VM = 1.65 V Traces from top to bottom: IN1 (6 V/div), OUT2 (5 V/div), VIPROPI (600 mV/div), Motor Current (100 mA/div) PWM Operation at VM = 5 V Traces from top to bottom: OUT1 (10 V/div), OUT2 (10 V/div), Motor Current (1 A/div), VIPROPI (50 mV/div) PWM Operation at VM = 11 V Traces from top to bottom: IN1 (7 V/div), OUT2 (6 V/div), Motor Current (200 mA/div), VIPROPI (2 V/div) Stall Detection with IMODE = Hi-Z, SMODE = 1 Traces from top to bottom: nSTALL (4 V/div), TINRUSH (1 V/div), OUT2 (5 V/div), Motor Current (600 mA/div) Thermal Performance The datasheet-specified junction-to-ambient thermal resistance, RθJA, is primarily useful for comparing various drivers or approximating thermal performance. However, the actual system performance may be better or worse than this value depending on PCB stackup, routing, number of vias, and copper area around the thermal pad. The length of time the driver drives a particular current will also impact power dissipation and thermal performance. This section considers how to design for steady-state and transient thermal conditions. The data in this section was simulated using the following criteria: WSON (DSG package) 2-layer PCB (size 114.3 x 76.2 x 1.6 mm), standard FR4, 1-oz (35 mm copper thickness) or 2-oz copper thickness. Thermal vias are only present under the thermal pad (2 vias, 1.2mm spacing, 0.3 mm diameter, 0.025 mm Cu plating). Top layer: DRV8213 WSON package footprint and copper plane heatsink. Top layer copper area is varied in simulation. Bottom layer: ground plane thermally connected through vias under the thermal pad for DRV8213. Bottom layer copper area varies with top copper area. 4-layer PCB (size 114.3 x 76.2 x 1.6 mm), standard FR4. Outer planes are 1-oz (35 mm copper thickness) or 2-oz copper thickness. Inner planes are kept at 1-oz. Thermal vias are only present under the thermal pad (2 vias, 1.2mm spacing, 0.3 mm diameter, 0.025 mm Cu plating). Top layer: DRV8213 WSON package footprint and copper plane heatsink. Top layer copper area is varied in simulation. Mid layer 1: GND plane thermally connected to DRV8213 thermal pad through vias. The area of the ground plane is 74.2 mm x 74.2 mm. Mid layer 2: power plane, no thermal connection. The area of the power plane is 74.2 mm x 74.2 mm. Bottom layer: ground plane thermally connected through via stitching from the TOP and internal GND planes. Bottom layer copper area varies with top copper area. shows an example of the simulated board for the DSG package. shows the dimensions of the board that were varied for each simulation. WSON PCB model top layer Dimension A for 8-pin DSG package Cu area (mm2) Dimension A (mm) 2 15.11 4 20.98 8 29.27 16 40.99 WQFN (RTE package) 2-layer PCB (size 114.3 x 76.2 x 1.6 mm), standard FR4, 1-oz (35 mm copper thickness) or 2-oz copper thickness. Thermal vias are only present under the package footprint (5 vias, 1 mm pitch, 0.2 mm diameter, 0.025 mm Cu plating). Top layer: WQFN package footprint and traces. Bottom layer: ground plane thermally connected through vias under the package footprint. Bottom layer copper area is varied in simulation. 4-layer PCB (size 114.3 x 76.2 x 1.6 mm), standard FR4. Outer planes are 1-oz (35 mm copper thickness) or 2-oz copper thickness. Inner planes are kept at 1-oz. Thermal vias are only present under the package footprint (5 vias, 1 mm pitch, 0.2 mm diameter, 0.025 mm Cu plating). Top layer: WQFN package footprint and traces. Mid layer 1: GND plane thermally connected under package footprint through vias. The area of the ground plane is 74.2 mm x 74.2 mm. Mid layer 2: power plane, no thermal connection. The area of the power plane is 74.2 mm x 74.2 mm. Bottom layer: signal layer with small copper pad underneath the driver and thermally connected through via stitching from the TOP and internal GND plane. Bottom layer thermal pad is the same size as the package (3 mm x 3 mm). Bottom pad size remains constant. shows an example of the simulated board for the WQFN package. shows the dimensions of the board that were varied for each simulation. WQFN PCB model top layer Dimension A for 16-pin RTE package Cu area (cm2) Dimension A (mm) 2 14.14 4 20.00 8 28.28 16 40.00 Steady-State Thermal Performance "Steady-state" conditions assume that the motor driver operates with a constant RMS current over a long period of time. The figures in this section show how RθJA and ΨJB (junction-to-board characterization parameter) change depending on copper area, copper thickness, and number of layers of the PCB. More copper area, more layers, and thicker copper planes decrease RθJA and ΨJB, which indicate better thermal performance from the PCB layout. WSON, PCB junction-to-ambient thermal resistance vs copper area WSON, junction-to-board characterization parameter vs copper area WQFN, PCB junction-to-ambient thermal resistance vs copper area WQFN, junction-to-board characterization parameter vs copper area Transient Thermal Performance The motor driver may experience different transient driving conditions that cause large currents to flow for a short duration of time. These may include - Motor start-up when the rotor is initially stationary. Fault conditions when there is a supply or ground short to one of the motor outputs, and the overcurrent protection triggers. Briefly energizing a motor or solenoid for a limited time, then de-energizing. For these transient cases, the duration of drive time is another factor that impacts thermal performance in addition to copper area and thickness. In transient cases, the thermal impedance parameter ZθJA denotes the junction-to-ambient thermal performance. The figures in this section show the simulated thermal impedances for 1-oz and 2-oz copper layouts for the WSON and WQFN packages. These graphs indicate better thermal performance with short current pulses. For short periods of drive time, the device die size and package dominates the thermal performance. For longer drive pulses, board layout has a more significant impact on thermal performance. Both graphs show the curves for thermal impedance split due to number of layers and copper area as the duration of the drive pulse duration increases. Long pulses can be considered steady-state performance. WSON package junction-to-ambient thermal impedance for 1-oz copper layouts WSON package junction-to-ambient thermal impedance for 2-oz copper layouts WQFN package junction-to-ambient thermal impedance for 1-oz copper layouts WQFN package junction-to-ambient thermal impedance for 2-oz copper layouts Brushed DC Motor A typical application for the DRV8213 is to drive a brushed DC motor using the full-bridge outputs. shows an example schematic using the DSG package for driving a motor and controlling the driver from a microcontroller (MCU). shows a schematic example using the RTE package with stall detection disabled. The resistor on the IPROPI pin can provide a voltage signal to the microcontroller analog-to-digital converter (ADC). Typical Connections for DSG variant Typical Connections for RTE variant with stall detection disabled A typical application for the DRV8213 is to drive a brushed DC motor using the full-bridge outputs. shows an example schematic using the DSG package for driving a motor and controlling the driver from a microcontroller (MCU). shows a schematic example using the RTE package with stall detection disabled. The resistor on the IPROPI pin can provide a voltage signal to the microcontroller analog-to-digital converter (ADC). Typical Connections for DSG variant Typical Connections for RTE variant with stall detection disabled A typical application for the DRV8213 is to drive a brushed DC motor using the full-bridge outputs. shows an example schematic using the DSG package for driving a motor and controlling the driver from a microcontroller (MCU). shows a schematic example using the RTE package with stall detection disabled. The resistor on the IPROPI pin can provide a voltage signal to the microcontroller analog-to-digital converter (ADC). Typical Connections for DSG variant Typical Connections for RTE variant with stall detection disabled Typical Connections for DSG variant Typical Connections for DSG variant Typical Connections for RTE variant with stall detection disabled Typical Connections for RTE variant with stall detection disabled Design Requirements #GUID-1DFAB0A4-875D-4F8B-A58B-4A48AAE30D80/TABLE_TLV_MKS_SNB lists example design parameters. Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2.1 A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Design Requirements #GUID-1DFAB0A4-875D-4F8B-A58B-4A48AAE30D80/TABLE_TLV_MKS_SNB lists example design parameters. Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2.1 A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz #GUID-1DFAB0A4-875D-4F8B-A58B-4A48AAE30D80/TABLE_TLV_MKS_SNB lists example design parameters. Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2.1 A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz #GUID-1DFAB0A4-875D-4F8B-A58B-4A48AAE30D80/TABLE_TLV_MKS_SNB Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2.1 A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2.1 A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz DESIGN PARAMETER REFERENCE EXAMPLE VALUE DESIGN PARAMETER REFERENCE EXAMPLE VALUE DESIGN PARAMETERREFERENCEEXAMPLE VALUE Motor voltage VVM 8 V Average motor current IAVG 0.8 A Motor inrush (startup) current IINRUSH 2.1 A Motor stall current ISTALL 2.1 A Motor current trip point ITRIP 1.9 A VREF voltage VREF 3.3 V IPROPI resistance RIPROPI 8.45 kΩ PWM frequency fPWM 20 kHz Motor voltage VVM 8 V Motor voltageVVM VM 8 V 8 V Average motor current IAVG 0.8 A Average motor currentIAVG AVG 0.8 A 0.8 A Motor inrush (startup) current IINRUSH 2.1 A Motor inrush (startup) currentIINRUSH INRUSH 2.1 A 2.1 A Motor stall current ISTALL 2.1 A Motor stall currentISTALL STALL 2.1 A 2.1 A Motor current trip point ITRIP 1.9 A Motor current trip pointITRIP TRIP 1.9 A 1.9 A VREF voltage VREF 3.3 V VREF voltageVREF 3.3 V 3.3 V IPROPI resistance RIPROPI 8.45 kΩ IPROPI resistanceRIPROPI IPROPI 8.45 kΩ 8.45 kΩ PWM frequency fPWM 20 kHz PWM frequencyfPWM PWM 20 kHz 20 kHz Detailed Design Procedure Motor Voltage The motor voltage to use depends on the ratings of the motor selected and the desired RPM. A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive motor windings. Motor Current Motors experience large currents at low speed, initial startup, and stalled rotor conditions. The large current at motor startup is sometimes called inrush current. The current regulation feature in the DRV8213 can help to limit these large currents. Alternatively, the microcontroller may limit the inrush current by ramping the PWM duty cycle during the startup time. Detailed Design Procedure Motor Voltage The motor voltage to use depends on the ratings of the motor selected and the desired RPM. A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive motor windings. Motor Voltage The motor voltage to use depends on the ratings of the motor selected and the desired RPM. A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive motor windings. The motor voltage to use depends on the ratings of the motor selected and the desired RPM. A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive motor windings. The motor voltage to use depends on the ratings of the motor selected and the desired RPM. A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive motor windings. Motor Current Motors experience large currents at low speed, initial startup, and stalled rotor conditions. The large current at motor startup is sometimes called inrush current. The current regulation feature in the DRV8213 can help to limit these large currents. Alternatively, the microcontroller may limit the inrush current by ramping the PWM duty cycle during the startup time. Motor Current Motors experience large currents at low speed, initial startup, and stalled rotor conditions. The large current at motor startup is sometimes called inrush current. The current regulation feature in the DRV8213 can help to limit these large currents. Alternatively, the microcontroller may limit the inrush current by ramping the PWM duty cycle during the startup time. Motors experience large currents at low speed, initial startup, and stalled rotor conditions. The large current at motor startup is sometimes called inrush current. The current regulation feature in the DRV8213 can help to limit these large currents. Alternatively, the microcontroller may limit the inrush current by ramping the PWM duty cycle during the startup time. Motors experience large currents at low speed, initial startup, and stalled rotor conditions. The large current at motor startup is sometimes called inrush current. The current regulation feature in the DRV8213 can help to limit these large currents. Alternatively, the microcontroller may limit the inrush current by ramping the PWM duty cycle during the startup time.DRV8213 Stall Detection Some applications require stall detection to notify the microcontroller of a locked-rotor/stall condition. A stall could be caused by one of two things: unintended mechanical blockage or the load reaching an end-stop in a constrained travel path. The DRV8213 supports two methods for determing a stall conditions: hardware stall detection and software stall detection. The RTE package supports hardware stall detection by providing additional pins to configure the response of the device to a stall condition as shown in . Both DSG and RTE packages support software stall detection by providing the IPROPI analog current sense feedback to the ADC of a microcontroller as shown in and . Typical Connections for RTE variant with stall detection enabled Detailed Design Procedure Hardware Stall Detection Application Description The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8213 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The capacitor on the TINRUSH pin sets the timing, tINRUSH, so the DRV8213 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8213 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nSTALL pulls low to indicate the stall event to the microcontroller. provides full details for configuring the stall detection feature. Example timing diagram for hardware stall detection summarizes stall detection configuration. Summary table for hardware stall detection pin configuration nSTALL TINRUSH SMODE Description GND Z X Stall detection disabled. Float TINRUSH. If IMODE = Z, current regulation occurs at all times when VIPROPI ≥ VVREF. Pull-up resistor to VCC GND X TI does not recommend this configuration. tINRUSH corresponds to approximately 6.7s. Device continuously sources 10 uA out of TINRUSH pin into GND. If IMODE = Z, current regulation occurs when VIPROPI ≥ VVREF. Capacitor to GND 0 Latched disable with indication: the OUTx pins disable and the nSTALL pin pulls low after tINRUSH when VIPROPI ≥ VVREF. 1/ Z Indication only: the OUTx pins remain active and the nSTALL pin pulls low after tINRUSH when VIPROPI ≥ VVREF. Z X TI does not recommend this configuration. Floating TINRUSH pin effectively sets tINRUSH = 0 seconds.The device responds according to the settings of SMODE and IMODE at all times when VIPROPI ≥ VVREF. VCC X TI does not recommend this configuration. Tying TINRUSH to a voltage higher than 1 V effectively sets tINRUSH = 0 seconds. The device draws excessive current from the voltage source due to the TINRUSH discharge path being on. Hardware Stall Detection Timing Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8213 integrates a timing circuit in the RTE package variant to ignore the inrush current during the startup time, tINRUSH. The timing circuit is configured using a capactior, CINRUSH, on the TINRUSH pin. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8213 and the system overall. #GUID-4A192769-F52B-4F35-9C38-238F0D2A0D89/EQUATION-BLOCK_F1X_S14_JTB defines the minimum tINRUSH time, tINRUSH_min. The timing tINRUSH_motor should be determined experimentally because it depends on motor parameters, supply voltage, temperature, and mechanical load response times. The ϵTINRUSH term accounts for tolerances in the TINRUSH timing circuit and the CINRUSH capacitor. t I N R U S H _ m i n = t I N R U S H _ m o t o r × 1 + ϵ T I N R U S H #GUID-4A192769-F52B-4F35-9C38-238F0D2A0D89/EQUATION-BLOCK_I54_HB4_JTB shows the expression for finding ϵTINRUSH. The tolerance of the 1-V reference on the TINRUSH pin is ϵVTINRUSH_trip. This tolerance is 3%, as defined by the minimum and maximum specifications for VTINRUSH_trip in the Electrical Characteristics table. The tolerance of the 10-µA current source on the TINRUSH pin is ϵITINRUSH. This tolerance is 20%, as defined by the minimum and maximum specifications for ITINRUSH in the Electrical Characteristics table. The tolerance of the CINRUSH capacitor is ϵCINRUSH. This is a percentage defined by the tolerance of the selected CINRUSH capacitor. ϵ T I N R U S H = ϵ V T I N R U S H _ t r i p 2 + ϵ I T I N R U S H 2 + ϵ C I N R U S H 2 For example, assume tINRUSH_motor = 100 ms and a capacitor with 1% tolerance will be used for CINRUSH. In this case, it can be calculated that the CINRUSH capacitor should be larger than 18.5 nF, so a 22 nF capacitor will be sufficient in this application. Hardware Stall Threshold Selection The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. and provide more details for configuring the voltage on the VREF pin. Software Stall Detection Application Description The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . To implement stall detection, the microcontroller reads the voltage on the IPROPI pin using an ADC and compares it to a stall threshold set in firmware. Alternatively, a comparator peripheral may be used to set this threshold. Motor Current Profile with STALL Signal Software Stall Detection Timing The microcontroller needs to decide whether or not the IPROPI signal indicates a motor stall. Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. Do not mistake the inrush current for a stall condition. One way to do this is for the microcontroller to ignore the IPROPI signal above the firmware stall threshold for the duration of the inrush current, tINRUSH, at startup. The tINRUSH timing is determined experimentally using the motor parameters, supply voltage, and mechanical load response times. When a stall condition occurs, the motor current increases from the average running current level because the back EMF is now 0 V. In some cases, it may be desirable to drive at the stall curent for some time in case the motor can clear the blockage on its own. This might be useful for an unintended stall or high-torque condition on the motor. In this case, the system designer can choose a long stall detection time, tSTALL, before the microcontroller decides to take action. In other cases, like end-stop detection, a faster response might be desired to reduce power or minimize strong motor torque on the gears or end-stop. This corresponds to setting a shorter tSTALL time in the microcontroller. illustrates the tINRUSH and tSTALL timings and how they relate to the motor current waveform. Software Stall Threshold Selection The stall detection threshold in firmware should be chosen at a current level between the maximum stall current and the average running current of the motor as shown in . Stall Detection Some applications require stall detection to notify the microcontroller of a locked-rotor/stall condition. A stall could be caused by one of two things: unintended mechanical blockage or the load reaching an end-stop in a constrained travel path. The DRV8213 supports two methods for determing a stall conditions: hardware stall detection and software stall detection. The RTE package supports hardware stall detection by providing additional pins to configure the response of the device to a stall condition as shown in . Both DSG and RTE packages support software stall detection by providing the IPROPI analog current sense feedback to the ADC of a microcontroller as shown in and . Typical Connections for RTE variant with stall detection enabled Some applications require stall detection to notify the microcontroller of a locked-rotor/stall condition. A stall could be caused by one of two things: unintended mechanical blockage or the load reaching an end-stop in a constrained travel path. The DRV8213 supports two methods for determing a stall conditions: hardware stall detection and software stall detection. The RTE package supports hardware stall detection by providing additional pins to configure the response of the device to a stall condition as shown in . Both DSG and RTE packages support software stall detection by providing the IPROPI analog current sense feedback to the ADC of a microcontroller as shown in and . Typical Connections for RTE variant with stall detection enabled Some applications require stall detection to notify the microcontroller of a locked-rotor/stall condition. A stall could be caused by one of two things: unintended mechanical blockage or the load reaching an end-stop in a constrained travel path. The DRV8213 supports two methods for determing a stall conditions: hardware stall detection and software stall detection. The RTE package supports hardware stall detection by providing additional pins to configure the response of the device to a stall condition as shown in . Both DSG and RTE packages support software stall detection by providing the IPROPI analog current sense feedback to the ADC of a microcontroller as shown in and .DRV8213 Typical Connections for RTE variant with stall detection enabled Typical Connections for RTE variant with stall detection enabled Detailed Design Procedure Hardware Stall Detection Application Description The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8213 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The capacitor on the TINRUSH pin sets the timing, tINRUSH, so the DRV8213 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8213 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nSTALL pulls low to indicate the stall event to the microcontroller. provides full details for configuring the stall detection feature. Example timing diagram for hardware stall detection summarizes stall detection configuration. Summary table for hardware stall detection pin configuration nSTALL TINRUSH SMODE Description GND Z X Stall detection disabled. Float TINRUSH. If IMODE = Z, current regulation occurs at all times when VIPROPI ≥ VVREF. Pull-up resistor to VCC GND X TI does not recommend this configuration. tINRUSH corresponds to approximately 6.7s. Device continuously sources 10 uA out of TINRUSH pin into GND. If IMODE = Z, current regulation occurs when VIPROPI ≥ VVREF. Capacitor to GND 0 Latched disable with indication: the OUTx pins disable and the nSTALL pin pulls low after tINRUSH when VIPROPI ≥ VVREF. 1/ Z Indication only: the OUTx pins remain active and the nSTALL pin pulls low after tINRUSH when VIPROPI ≥ VVREF. Z X TI does not recommend this configuration. Floating TINRUSH pin effectively sets tINRUSH = 0 seconds.The device responds according to the settings of SMODE and IMODE at all times when VIPROPI ≥ VVREF. VCC X TI does not recommend this configuration. Tying TINRUSH to a voltage higher than 1 V effectively sets tINRUSH = 0 seconds. The device draws excessive current from the voltage source due to the TINRUSH discharge path being on. Hardware Stall Detection Timing Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8213 integrates a timing circuit in the RTE package variant to ignore the inrush current during the startup time, tINRUSH. The timing circuit is configured using a capactior, CINRUSH, on the TINRUSH pin. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8213 and the system overall. #GUID-4A192769-F52B-4F35-9C38-238F0D2A0D89/EQUATION-BLOCK_F1X_S14_JTB defines the minimum tINRUSH time, tINRUSH_min. The timing tINRUSH_motor should be determined experimentally because it depends on motor parameters, supply voltage, temperature, and mechanical load response times. The ϵTINRUSH term accounts for tolerances in the TINRUSH timing circuit and the CINRUSH capacitor. t I N R U S H _ m i n = t I N R U S H _ m o t o r × 1 + ϵ T I N R U S H #GUID-4A192769-F52B-4F35-9C38-238F0D2A0D89/EQUATION-BLOCK_I54_HB4_JTB shows the expression for finding ϵTINRUSH. The tolerance of the 1-V reference on the TINRUSH pin is ϵVTINRUSH_trip. This tolerance is 3%, as defined by the minimum and maximum specifications for VTINRUSH_trip in the Electrical Characteristics table. The tolerance of the 10-µA current source on the TINRUSH pin is ϵITINRUSH. This tolerance is 20%, as defined by the minimum and maximum specifications for ITINRUSH in the Electrical Characteristics table. The tolerance of the CINRUSH capacitor is ϵCINRUSH. This is a percentage defined by the tolerance of the selected CINRUSH capacitor. ϵ T I N R U S H = ϵ V T I N R U S H _ t r i p 2 + ϵ I T I N R U S H 2 + ϵ C I N R U S H 2 For example, assume tINRUSH_motor = 100 ms and a capacitor with 1% tolerance will be used for CINRUSH. In this case, it can be calculated that the CINRUSH capacitor should be larger than 18.5 nF, so a 22 nF capacitor will be sufficient in this application. Hardware Stall Threshold Selection The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. and provide more details for configuring the voltage on the VREF pin. Software Stall Detection Application Description The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . To implement stall detection, the microcontroller reads the voltage on the IPROPI pin using an ADC and compares it to a stall threshold set in firmware. Alternatively, a comparator peripheral may be used to set this threshold. Motor Current Profile with STALL Signal Software Stall Detection Timing The microcontroller needs to decide whether or not the IPROPI signal indicates a motor stall. Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. Do not mistake the inrush current for a stall condition. One way to do this is for the microcontroller to ignore the IPROPI signal above the firmware stall threshold for the duration of the inrush current, tINRUSH, at startup. The tINRUSH timing is determined experimentally using the motor parameters, supply voltage, and mechanical load response times. When a stall condition occurs, the motor current increases from the average running current level because the back EMF is now 0 V. In some cases, it may be desirable to drive at the stall curent for some time in case the motor can clear the blockage on its own. This might be useful for an unintended stall or high-torque condition on the motor. In this case, the system designer can choose a long stall detection time, tSTALL, before the microcontroller decides to take action. In other cases, like end-stop detection, a faster response might be desired to reduce power or minimize strong motor torque on the gears or end-stop. This corresponds to setting a shorter tSTALL time in the microcontroller. illustrates the tINRUSH and tSTALL timings and how they relate to the motor current waveform. Software Stall Threshold Selection The stall detection threshold in firmware should be chosen at a current level between the maximum stall current and the average running current of the motor as shown in . Detailed Design Procedure Hardware Stall Detection Application Description The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8213 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The capacitor on the TINRUSH pin sets the timing, tINRUSH, so the DRV8213 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8213 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nSTALL pulls low to indicate the stall event to the microcontroller. provides full details for configuring the stall detection feature. Example timing diagram for hardware stall detection summarizes stall detection configuration. Summary table for hardware stall detection pin configuration nSTALL TINRUSH SMODE Description GND Z X Stall detection disabled. Float TINRUSH. If IMODE = Z, current regulation occurs at all times when VIPROPI ≥ VVREF. Pull-up resistor to VCC GND X TI does not recommend this configuration. tINRUSH corresponds to approximately 6.7s. Device continuously sources 10 uA out of TINRUSH pin into GND. If IMODE = Z, current regulation occurs when VIPROPI ≥ VVREF. Capacitor to GND 0 Latched disable with indication: the OUTx pins disable and the nSTALL pin pulls low after tINRUSH when VIPROPI ≥ VVREF. 1/ Z Indication only: the OUTx pins remain active and the nSTALL pin pulls low after tINRUSH when VIPROPI ≥ VVREF. Z X TI does not recommend this configuration. Floating TINRUSH pin effectively sets tINRUSH = 0 seconds.The device responds according to the settings of SMODE and IMODE at all times when VIPROPI ≥ VVREF. VCC X TI does not recommend this configuration. Tying TINRUSH to a voltage higher than 1 V effectively sets tINRUSH = 0 seconds. The device draws excessive current from the voltage source due to the TINRUSH discharge path being on. Hardware Stall Detection Timing Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8213 integrates a timing circuit in the RTE package variant to ignore the inrush current during the startup time, tINRUSH. The timing circuit is configured using a capactior, CINRUSH, on the TINRUSH pin. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8213 and the system overall. #GUID-4A192769-F52B-4F35-9C38-238F0D2A0D89/EQUATION-BLOCK_F1X_S14_JTB defines the minimum tINRUSH time, tINRUSH_min. The timing tINRUSH_motor should be determined experimentally because it depends on motor parameters, supply voltage, temperature, and mechanical load response times. The ϵTINRUSH term accounts for tolerances in the TINRUSH timing circuit and the CINRUSH capacitor. t I N R U S H _ m i n = t I N R U S H _ m o t o r × 1 + ϵ T I N R U S H #GUID-4A192769-F52B-4F35-9C38-238F0D2A0D89/EQUATION-BLOCK_I54_HB4_JTB shows the expression for finding ϵTINRUSH. The tolerance of the 1-V reference on the TINRUSH pin is ϵVTINRUSH_trip. This tolerance is 3%, as defined by the minimum and maximum specifications for VTINRUSH_trip in the Electrical Characteristics table. The tolerance of the 10-µA current source on the TINRUSH pin is ϵITINRUSH. This tolerance is 20%, as defined by the minimum and maximum specifications for ITINRUSH in the Electrical Characteristics table. The tolerance of the CINRUSH capacitor is ϵCINRUSH. This is a percentage defined by the tolerance of the selected CINRUSH capacitor. ϵ T I N R U S H = ϵ V T I N R U S H _ t r i p 2 + ϵ I T I N R U S H 2 + ϵ C I N R U S H 2 For example, assume tINRUSH_motor = 100 ms and a capacitor with 1% tolerance will be used for CINRUSH. In this case, it can be calculated that the CINRUSH capacitor should be larger than 18.5 nF, so a 22 nF capacitor will be sufficient in this application. Hardware Stall Threshold Selection The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. and provide more details for configuring the voltage on the VREF pin. Hardware Stall Detection Application Description The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8213 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The capacitor on the TINRUSH pin sets the timing, tINRUSH, so the DRV8213 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8213 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nSTALL pulls low to indicate the stall event to the microcontroller. provides full details for configuring the stall detection feature. Example timing diagram for hardware stall detection summarizes stall detection configuration. Summary table for hardware stall detection pin configuration nSTALL TINRUSH SMODE Description GND Z X Stall detection disabled. Float TINRUSH. If IMODE = Z, current regulation occurs at all times when VIPROPI ≥ VVREF. Pull-up resistor to VCC GND X TI does not recommend this configuration. tINRUSH corresponds to approximately 6.7s. Device continuously sources 10 uA out of TINRUSH pin into GND. If IMODE = Z, current regulation occurs when VIPROPI ≥ VVREF. Capacitor to GND 0 Latched disable with indication: the OUTx pins disable and the nSTALL pin pulls low after tINRUSH when VIPROPI ≥ VVREF. 1/ Z Indication only: the OUTx pins remain active and the nSTALL pin pulls low after tINRUSH when VIPROPI ≥ VVREF. Z X TI does not recommend this configuration. Floating TINRUSH pin effectively sets tINRUSH = 0 seconds.The device responds according to the settings of SMODE and IMODE at all times when VIPROPI ≥ VVREF. VCC X TI does not recommend this configuration. Tying TINRUSH to a voltage higher than 1 V effectively sets tINRUSH = 0 seconds. The device draws excessive current from the voltage source due to the TINRUSH discharge path being on. The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8213 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The capacitor on the TINRUSH pin sets the timing, tINRUSH, so the DRV8213 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8213 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nSTALL pulls low to indicate the stall event to the microcontroller. provides full details for configuring the stall detection feature. Example timing diagram for hardware stall detection summarizes stall detection configuration. Summary table for hardware stall detection pin configuration nSTALL TINRUSH SMODE Description GND Z X Stall detection disabled. Float TINRUSH. If IMODE = Z, current regulation occurs at all times when VIPROPI ≥ VVREF. Pull-up resistor to VCC GND X TI does not recommend this configuration. tINRUSH corresponds to approximately 6.7s. Device continuously sources 10 uA out of TINRUSH pin into GND. If IMODE = Z, current regulation occurs when VIPROPI ≥ VVREF. Capacitor to GND 0 Latched disable with indication: the OUTx pins disable and the nSTALL pin pulls low after tINRUSH when VIPROPI ≥ VVREF. 1/ Z Indication only: the OUTx pins remain active and the nSTALL pin pulls low after tINRUSH when VIPROPI ≥ VVREF. Z X TI does not recommend this configuration. Floating TINRUSH pin effectively sets tINRUSH = 0 seconds.The device responds according to the settings of SMODE and IMODE at all times when VIPROPI ≥ VVREF. VCC X TI does not recommend this configuration. Tying TINRUSH to a voltage higher than 1 V effectively sets tINRUSH = 0 seconds. The device draws excessive current from the voltage source due to the TINRUSH discharge path being on. The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . The DRV8213 compares the voltage on the IPROPI pin to the voltage on the VREF pin to determine whether a stall condition has occurred. The capacitor on the TINRUSH pin sets the timing, tINRUSH, so the DRV8213 ignores the inrush current at motor startup. The SMODE pin configures how the DRV8213 responds to a stall condition. The IMODE pin configures whether the device regulates current during inrush and stall currents. When a stall condition occures, nSTALL pulls low to indicate the stall event to the microcontroller. provides full details for configuring the stall detection feature.INRUSH Example timing diagram for hardware stall detection Example timing diagram for hardware stall detection summarizes stall detection configuration. Summary table for hardware stall detection pin configuration nSTALL TINRUSH SMODE Description GND Z X Stall detection disabled. Float TINRUSH. If IMODE = Z, current regulation occurs at all times when VIPROPI ≥ VVREF. Pull-up resistor to VCC GND X TI does not recommend this configuration. tINRUSH corresponds to approximately 6.7s. Device continuously sources 10 uA out of TINRUSH pin into GND. If IMODE = Z, current regulation occurs when VIPROPI ≥ VVREF. Capacitor to GND 0 Latched disable with indication: the OUTx pins disable and the nSTALL pin pulls low after tINRUSH when VIPROPI ≥ VVREF. 1/ Z Indication only: the OUTx pins remain active and the nSTALL pin pulls low after tINRUSH when VIPROPI ≥ VVREF. Z X TI does not recommend this configuration. Floating TINRUSH pin effectively sets tINRUSH = 0 seconds.The device responds according to the settings of SMODE and IMODE at all times when VIPROPI ≥ VVREF. VCC X TI does not recommend this configuration. Tying TINRUSH to a voltage higher than 1 V effectively sets tINRUSH = 0 seconds. The device draws excessive current from the voltage source due to the TINRUSH discharge path being on. Summary table for hardware stall detection pin configuration nSTALL TINRUSH SMODE Description GND Z X Stall detection disabled. Float TINRUSH. If IMODE = Z, current regulation occurs at all times when VIPROPI ≥ VVREF. Pull-up resistor to VCC GND X TI does not recommend this configuration. tINRUSH corresponds to approximately 6.7s. Device continuously sources 10 uA out of TINRUSH pin into GND. If IMODE = Z, current regulation occurs when VIPROPI ≥ VVREF. Capacitor to GND 0 Latched disable with indication: the OUTx pins disable and the nSTALL pin pulls low after tINRUSH when VIPROPI ≥ VVREF. 1/ Z Indication only: the OUTx pins remain active and the nSTALL pin pulls low after tINRUSH when VIPROPI ≥ VVREF. Z X TI does not recommend this configuration. Floating TINRUSH pin effectively sets tINRUSH = 0 seconds.The device responds according to the settings of SMODE and IMODE at all times when VIPROPI ≥ VVREF. VCC X TI does not recommend this configuration. Tying TINRUSH to a voltage higher than 1 V effectively sets tINRUSH = 0 seconds. The device draws excessive current from the voltage source due to the TINRUSH discharge path being on. nSTALL TINRUSH SMODE Description nSTALL TINRUSH SMODE Description nSTALLTINRUSHSMODEDescription GND Z X Stall detection disabled. Float TINRUSH. If IMODE = Z, current regulation occurs at all times when VIPROPI ≥ VVREF. Pull-up resistor to VCC GND X TI does not recommend this configuration. tINRUSH corresponds to approximately 6.7s. Device continuously sources 10 uA out of TINRUSH pin into GND. If IMODE = Z, current regulation occurs when VIPROPI ≥ VVREF. Capacitor to GND 0 Latched disable with indication: the OUTx pins disable and the nSTALL pin pulls low after tINRUSH when VIPROPI ≥ VVREF. 1/ Z Indication only: the OUTx pins remain active and the nSTALL pin pulls low after tINRUSH when VIPROPI ≥ VVREF. Z X TI does not recommend this configuration. Floating TINRUSH pin effectively sets tINRUSH = 0 seconds.The device responds according to the settings of SMODE and IMODE at all times when VIPROPI ≥ VVREF. VCC X TI does not recommend this configuration. Tying TINRUSH to a voltage higher than 1 V effectively sets tINRUSH = 0 seconds. The device draws excessive current from the voltage source due to the TINRUSH discharge path being on. GND Z X Stall detection disabled. Float TINRUSH. If IMODE = Z, current regulation occurs at all times when VIPROPI ≥ VVREF. GNDZ X XStall detection disabled. Float TINRUSH. If IMODE = Z, current regulation occurs at all times when VIPROPI ≥ VVREF.IPROPIVREF Pull-up resistor to VCC GND X TI does not recommend this configuration. tINRUSH corresponds to approximately 6.7s. Device continuously sources 10 uA out of TINRUSH pin into GND. If IMODE = Z, current regulation occurs when VIPROPI ≥ VVREF. Pull-up resistor to VCCGNDXTI does not recommend this configuration. tINRUSH corresponds to approximately 6.7s. Device continuously sources 10 uA out of TINRUSH pin into GND. If IMODE = Z, current regulation occurs when VIPROPI ≥ VVREF.INRUSHIPROPIVREF Capacitor to GND 0 Latched disable with indication: the OUTx pins disable and the nSTALL pin pulls low after tINRUSH when VIPROPI ≥ VVREF. Capacitor to GND0Latched disable with indication: the OUTx pins disable and the nSTALL pin pulls low after tINRUSH when VIPROPI ≥ VVREF.INRUSHIPROPIVREF 1/ Z Indication only: the OUTx pins remain active and the nSTALL pin pulls low after tINRUSH when VIPROPI ≥ VVREF. 1/ Z / ZIndication only: the OUTx pins remain active and the nSTALL pin pulls low after tINRUSH when VIPROPI ≥ VVREF.INRUSHIPROPIVREF Z X TI does not recommend this configuration. Floating TINRUSH pin effectively sets tINRUSH = 0 seconds.The device responds according to the settings of SMODE and IMODE at all times when VIPROPI ≥ VVREF. Z Z X XTI does not recommend this configuration. Floating TINRUSH pin effectively sets tINRUSH = 0 seconds.The device responds according to the settings of SMODE and IMODE at all times when VIPROPI ≥ VVREF. INRUSHThe device responds according to the settings of SMODE and IMODE at all times when VIPROPI ≥ VVREF.IPROPIVREF VCC X TI does not recommend this configuration. Tying TINRUSH to a voltage higher than 1 V effectively sets tINRUSH = 0 seconds. The device draws excessive current from the voltage source due to the TINRUSH discharge path being on. VCCXTI does not recommend this configuration. Tying TINRUSH to a voltage higher than 1 V effectively sets tINRUSH = 0 seconds. The device draws excessive current from the voltage source due to the TINRUSH discharge path being on.INRUSH Hardware Stall Detection Timing Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8213 integrates a timing circuit in the RTE package variant to ignore the inrush current during the startup time, tINRUSH. The timing circuit is configured using a capactior, CINRUSH, on the TINRUSH pin. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8213 and the system overall. #GUID-4A192769-F52B-4F35-9C38-238F0D2A0D89/EQUATION-BLOCK_F1X_S14_JTB defines the minimum tINRUSH time, tINRUSH_min. The timing tINRUSH_motor should be determined experimentally because it depends on motor parameters, supply voltage, temperature, and mechanical load response times. The ϵTINRUSH term accounts for tolerances in the TINRUSH timing circuit and the CINRUSH capacitor. t I N R U S H _ m i n = t I N R U S H _ m o t o r × 1 + ϵ T I N R U S H #GUID-4A192769-F52B-4F35-9C38-238F0D2A0D89/EQUATION-BLOCK_I54_HB4_JTB shows the expression for finding ϵTINRUSH. The tolerance of the 1-V reference on the TINRUSH pin is ϵVTINRUSH_trip. This tolerance is 3%, as defined by the minimum and maximum specifications for VTINRUSH_trip in the Electrical Characteristics table. The tolerance of the 10-µA current source on the TINRUSH pin is ϵITINRUSH. This tolerance is 20%, as defined by the minimum and maximum specifications for ITINRUSH in the Electrical Characteristics table. The tolerance of the CINRUSH capacitor is ϵCINRUSH. This is a percentage defined by the tolerance of the selected CINRUSH capacitor. ϵ T I N R U S H = ϵ V T I N R U S H _ t r i p 2 + ϵ I T I N R U S H 2 + ϵ C I N R U S H 2 For example, assume tINRUSH_motor = 100 ms and a capacitor with 1% tolerance will be used for CINRUSH. In this case, it can be calculated that the CINRUSH capacitor should be larger than 18.5 nF, so a 22 nF capacitor will be sufficient in this application. Hardware Stall Detection Timing Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8213 integrates a timing circuit in the RTE package variant to ignore the inrush current during the startup time, tINRUSH. The timing circuit is configured using a capactior, CINRUSH, on the TINRUSH pin. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8213 and the system overall. #GUID-4A192769-F52B-4F35-9C38-238F0D2A0D89/EQUATION-BLOCK_F1X_S14_JTB defines the minimum tINRUSH time, tINRUSH_min. The timing tINRUSH_motor should be determined experimentally because it depends on motor parameters, supply voltage, temperature, and mechanical load response times. The ϵTINRUSH term accounts for tolerances in the TINRUSH timing circuit and the CINRUSH capacitor. t I N R U S H _ m i n = t I N R U S H _ m o t o r × 1 + ϵ T I N R U S H #GUID-4A192769-F52B-4F35-9C38-238F0D2A0D89/EQUATION-BLOCK_I54_HB4_JTB shows the expression for finding ϵTINRUSH. The tolerance of the 1-V reference on the TINRUSH pin is ϵVTINRUSH_trip. This tolerance is 3%, as defined by the minimum and maximum specifications for VTINRUSH_trip in the Electrical Characteristics table. The tolerance of the 10-µA current source on the TINRUSH pin is ϵITINRUSH. This tolerance is 20%, as defined by the minimum and maximum specifications for ITINRUSH in the Electrical Characteristics table. The tolerance of the CINRUSH capacitor is ϵCINRUSH. This is a percentage defined by the tolerance of the selected CINRUSH capacitor. ϵ T I N R U S H = ϵ V T I N R U S H _ t r i p 2 + ϵ I T I N R U S H 2 + ϵ C I N R U S H 2 For example, assume tINRUSH_motor = 100 ms and a capacitor with 1% tolerance will be used for CINRUSH. In this case, it can be calculated that the CINRUSH capacitor should be larger than 18.5 nF, so a 22 nF capacitor will be sufficient in this application. Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8213 integrates a timing circuit in the RTE package variant to ignore the inrush current during the startup time, tINRUSH. The timing circuit is configured using a capactior, CINRUSH, on the TINRUSH pin. describes the overall details for using the stall detection feature. When designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8213 and the system overall. #GUID-4A192769-F52B-4F35-9C38-238F0D2A0D89/EQUATION-BLOCK_F1X_S14_JTB defines the minimum tINRUSH time, tINRUSH_min. The timing tINRUSH_motor should be determined experimentally because it depends on motor parameters, supply voltage, temperature, and mechanical load response times. The ϵTINRUSH term accounts for tolerances in the TINRUSH timing circuit and the CINRUSH capacitor. t I N R U S H _ m i n = t I N R U S H _ m o t o r × 1 + ϵ T I N R U S H #GUID-4A192769-F52B-4F35-9C38-238F0D2A0D89/EQUATION-BLOCK_I54_HB4_JTB shows the expression for finding ϵTINRUSH. The tolerance of the 1-V reference on the TINRUSH pin is ϵVTINRUSH_trip. This tolerance is 3%, as defined by the minimum and maximum specifications for VTINRUSH_trip in the Electrical Characteristics table. The tolerance of the 10-µA current source on the TINRUSH pin is ϵITINRUSH. This tolerance is 20%, as defined by the minimum and maximum specifications for ITINRUSH in the Electrical Characteristics table. The tolerance of the CINRUSH capacitor is ϵCINRUSH. This is a percentage defined by the tolerance of the selected CINRUSH capacitor. ϵ T I N R U S H = ϵ V T I N R U S H _ t r i p 2 + ϵ I T I N R U S H 2 + ϵ C I N R U S H 2 For example, assume tINRUSH_motor = 100 ms and a capacitor with 1% tolerance will be used for CINRUSH. In this case, it can be calculated that the CINRUSH capacitor should be larger than 18.5 nF, so a 22 nF capacitor will be sufficient in this application. Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. The inrush current should not be mistaken for a stall condition, so the DRV8213 integrates a timing circuit in the RTE package variant to ignore the inrush current during the startup time, tINRUSH. The timing circuit is configured using a capactior, CINRUSH, on the TINRUSH pin. describes the overall details for using the stall detection feature.INRUSHINRUSHWhen designing for the tINRUSH time, it is important to include enough margin to account for tolerances and variation in the DRV8213 and the system overall. #GUID-4A192769-F52B-4F35-9C38-238F0D2A0D89/EQUATION-BLOCK_F1X_S14_JTB defines the minimum tINRUSH time, tINRUSH_min. The timing tINRUSH_motor should be determined experimentally because it depends on motor parameters, supply voltage, temperature, and mechanical load response times. The ϵTINRUSH term accounts for tolerances in the TINRUSH timing circuit and the CINRUSH capacitor.INRUSH#GUID-4A192769-F52B-4F35-9C38-238F0D2A0D89/EQUATION-BLOCK_F1X_S14_JTBINRUSHINRUSH_minINRUSH_motorTINRUSHINRUSH t I N R U S H _ m i n = t I N R U S H _ m o t o r × 1 + ϵ T I N R U S H t I N R U S H _ m i n = t I N R U S H _ m o t o r × 1 + ϵ T I N R U S H t I N R U S H _ m i n = t I N R U S H _ m o t o r × 1 + ϵ T I N R U S H t I N R U S H _ m i n t t I N R U S H _ m i n INRUSH_min= t I N R U S H _ m o t o r t t I N R U S H _ m o t o r INRUSH_motor× 1 + ϵ T I N R U S H 1 + ϵ T I N R U S H 1+ ϵ T I N R U S H ϵ ϵ T I N R U S H TINRUSH #GUID-4A192769-F52B-4F35-9C38-238F0D2A0D89/EQUATION-BLOCK_I54_HB4_JTB shows the expression for finding ϵTINRUSH. The tolerance of the 1-V reference on the TINRUSH pin is ϵVTINRUSH_trip. This tolerance is 3%, as defined by the minimum and maximum specifications for VTINRUSH_trip in the Electrical Characteristics table. The tolerance of the 10-µA current source on the TINRUSH pin is ϵITINRUSH. This tolerance is 20%, as defined by the minimum and maximum specifications for ITINRUSH in the Electrical Characteristics table. The tolerance of the CINRUSH capacitor is ϵCINRUSH. This is a percentage defined by the tolerance of the selected CINRUSH capacitor.#GUID-4A192769-F52B-4F35-9C38-238F0D2A0D89/EQUATION-BLOCK_I54_HB4_JTBTINRUSHVTINRUSH_tripTINRUSH_tripITINRUSHTINRUSHINRUSHCINRUSHINRUSH ϵ T I N R U S H = ϵ V T I N R U S H _ t r i p 2 + ϵ I T I N R U S H 2 + ϵ C I N R U S H 2 ϵ T I N R U S H = ϵ V T I N R U S H _ t r i p 2 + ϵ I T I N R U S H 2 + ϵ C I N R U S H 2 ϵ T I N R U S H = ϵ V T I N R U S H _ t r i p 2 + ϵ I T I N R U S H 2 + ϵ C I N R U S H 2 ϵ T I N R U S H ϵ ϵ T I N R U S H TINRUSH= ϵ V T I N R U S H _ t r i p 2 + ϵ I T I N R U S H 2 + ϵ C I N R U S H 2 ϵ V T I N R U S H _ t r i p 2 ϵ ϵ V T I N R U S H _ t r i p VTINRUSH_trip 2 2+ ϵ I T I N R U S H 2 ϵ ϵ I T I N R U S H ITINRUSH 2 2+ ϵ C I N R U S H 2 ϵ ϵ C I N R U S H CINRUSH 2 2For example, assume tINRUSH_motor = 100 ms and a capacitor with 1% tolerance will be used for CINRUSH. In this case, it can be calculated that the CINRUSH capacitor should be larger than 18.5 nF, so a 22 nF capacitor will be sufficient in this application.tINRUSH_motor = 100 msINRUSH_motorINRUSHINRUSH Hardware Stall Threshold Selection The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. and provide more details for configuring the voltage on the VREF pin. Hardware Stall Threshold Selection The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. and provide more details for configuring the voltage on the VREF pin. The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. and provide more details for configuring the voltage on the VREF pin. The voltage on the VREF pin selects ITRIP threshold which sets the current level for stall detection and current regulation. This threshold should be chosen such that ITRIP is less than the stall current of the motor when current regulation is not used. It should also be set low enough to account for variation in the stall current due to changes in the motor supply voltage, VVM, and temperature. and provide more details for configuring the voltage on the VREF pin.TRIPTRIPVM Software Stall Detection Application Description The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . To implement stall detection, the microcontroller reads the voltage on the IPROPI pin using an ADC and compares it to a stall threshold set in firmware. Alternatively, a comparator peripheral may be used to set this threshold. Motor Current Profile with STALL Signal Software Stall Detection Timing The microcontroller needs to decide whether or not the IPROPI signal indicates a motor stall. Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. Do not mistake the inrush current for a stall condition. One way to do this is for the microcontroller to ignore the IPROPI signal above the firmware stall threshold for the duration of the inrush current, tINRUSH, at startup. The tINRUSH timing is determined experimentally using the motor parameters, supply voltage, and mechanical load response times. When a stall condition occurs, the motor current increases from the average running current level because the back EMF is now 0 V. In some cases, it may be desirable to drive at the stall curent for some time in case the motor can clear the blockage on its own. This might be useful for an unintended stall or high-torque condition on the motor. In this case, the system designer can choose a long stall detection time, tSTALL, before the microcontroller decides to take action. In other cases, like end-stop detection, a faster response might be desired to reduce power or minimize strong motor torque on the gears or end-stop. This corresponds to setting a shorter tSTALL time in the microcontroller. illustrates the tINRUSH and tSTALL timings and how they relate to the motor current waveform. Software Stall Threshold Selection The stall detection threshold in firmware should be chosen at a current level between the maximum stall current and the average running current of the motor as shown in . Software Stall Detection Application Description The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . To implement stall detection, the microcontroller reads the voltage on the IPROPI pin using an ADC and compares it to a stall threshold set in firmware. Alternatively, a comparator peripheral may be used to set this threshold. Motor Current Profile with STALL Signal The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . To implement stall detection, the microcontroller reads the voltage on the IPROPI pin using an ADC and compares it to a stall threshold set in firmware. Alternatively, a comparator peripheral may be used to set this threshold. Motor Current Profile with STALL Signal The principle of this stall detection scheme relies on the fact that motor current increases during stall conditions as shown in . To implement stall detection, the microcontroller reads the voltage on the IPROPI pin using an ADC and compares it to a stall threshold set in firmware. Alternatively, a comparator peripheral may be used to set this threshold. Motor Current Profile with STALL Signal Motor Current Profile with STALL Signal Software Stall Detection Timing The microcontroller needs to decide whether or not the IPROPI signal indicates a motor stall. Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. Do not mistake the inrush current for a stall condition. One way to do this is for the microcontroller to ignore the IPROPI signal above the firmware stall threshold for the duration of the inrush current, tINRUSH, at startup. The tINRUSH timing is determined experimentally using the motor parameters, supply voltage, and mechanical load response times. When a stall condition occurs, the motor current increases from the average running current level because the back EMF is now 0 V. In some cases, it may be desirable to drive at the stall curent for some time in case the motor can clear the blockage on its own. This might be useful for an unintended stall or high-torque condition on the motor. In this case, the system designer can choose a long stall detection time, tSTALL, before the microcontroller decides to take action. In other cases, like end-stop detection, a faster response might be desired to reduce power or minimize strong motor torque on the gears or end-stop. This corresponds to setting a shorter tSTALL time in the microcontroller. illustrates the tINRUSH and tSTALL timings and how they relate to the motor current waveform. Software Stall Detection Timing The microcontroller needs to decide whether or not the IPROPI signal indicates a motor stall. Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. Do not mistake the inrush current for a stall condition. One way to do this is for the microcontroller to ignore the IPROPI signal above the firmware stall threshold for the duration of the inrush current, tINRUSH, at startup. The tINRUSH timing is determined experimentally using the motor parameters, supply voltage, and mechanical load response times. When a stall condition occurs, the motor current increases from the average running current level because the back EMF is now 0 V. In some cases, it may be desirable to drive at the stall curent for some time in case the motor can clear the blockage on its own. This might be useful for an unintended stall or high-torque condition on the motor. In this case, the system designer can choose a long stall detection time, tSTALL, before the microcontroller decides to take action. In other cases, like end-stop detection, a faster response might be desired to reduce power or minimize strong motor torque on the gears or end-stop. This corresponds to setting a shorter tSTALL time in the microcontroller. illustrates the tINRUSH and tSTALL timings and how they relate to the motor current waveform. The microcontroller needs to decide whether or not the IPROPI signal indicates a motor stall. Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. Do not mistake the inrush current for a stall condition. One way to do this is for the microcontroller to ignore the IPROPI signal above the firmware stall threshold for the duration of the inrush current, tINRUSH, at startup. The tINRUSH timing is determined experimentally using the motor parameters, supply voltage, and mechanical load response times. When a stall condition occurs, the motor current increases from the average running current level because the back EMF is now 0 V. In some cases, it may be desirable to drive at the stall curent for some time in case the motor can clear the blockage on its own. This might be useful for an unintended stall or high-torque condition on the motor. In this case, the system designer can choose a long stall detection time, tSTALL, before the microcontroller decides to take action. In other cases, like end-stop detection, a faster response might be desired to reduce power or minimize strong motor torque on the gears or end-stop. This corresponds to setting a shorter tSTALL time in the microcontroller. illustrates the tINRUSH and tSTALL timings and how they relate to the motor current waveform. The microcontroller needs to decide whether or not the IPROPI signal indicates a motor stall. Large inrush current occurs during motor start up because motor speed is low. As the motor accelerates, the motor current drops to an average level because the back electromotive force (EMF) in the motor increases with speed. Do not mistake the inrush current for a stall condition. One way to do this is for the microcontroller to ignore the IPROPI signal above the firmware stall threshold for the duration of the inrush current, tINRUSH, at startup. The tINRUSH timing is determined experimentally using the motor parameters, supply voltage, and mechanical load response times.INRUSHINRUSHWhen a stall condition occurs, the motor current increases from the average running current level because the back EMF is now 0 V. In some cases, it may be desirable to drive at the stall curent for some time in case the motor can clear the blockage on its own. This might be useful for an unintended stall or high-torque condition on the motor. In this case, the system designer can choose a long stall detection time, tSTALL, before the microcontroller decides to take action. In other cases, like end-stop detection, a faster response might be desired to reduce power or minimize strong motor torque on the gears or end-stop. This corresponds to setting a shorter tSTALL time in the microcontroller.STALLSTALL illustrates the tINRUSH and tSTALL timings and how they relate to the motor current waveform.INRUSHSTALL Software Stall Threshold Selection The stall detection threshold in firmware should be chosen at a current level between the maximum stall current and the average running current of the motor as shown in . Software Stall Threshold Selection The stall detection threshold in firmware should be chosen at a current level between the maximum stall current and the average running current of the motor as shown in . The stall detection threshold in firmware should be chosen at a current level between the maximum stall current and the average running current of the motor as shown in . The stall detection threshold in firmware should be chosen at a current level between the maximum stall current and the average running current of the motor as shown in . Application Curves PWM Operation at VM = 1.65 V Traces from top to bottom: IN1 (6 V/div), OUT2 (5 V/div), VIPROPI (600 mV/div), Motor Current (100 mA/div) PWM Operation at VM = 5 V Traces from top to bottom: OUT1 (10 V/div), OUT2 (10 V/div), Motor Current (1 A/div), VIPROPI (50 mV/div) PWM Operation at VM = 11 V Traces from top to bottom: IN1 (7 V/div), OUT2 (6 V/div), Motor Current (200 mA/div), VIPROPI (2 V/div) Stall Detection with IMODE = Hi-Z, SMODE = 1 Traces from top to bottom: nSTALL (4 V/div), TINRUSH (1 V/div), OUT2 (5 V/div), Motor Current (600 mA/div) Application Curves PWM Operation at VM = 1.65 V Traces from top to bottom: IN1 (6 V/div), OUT2 (5 V/div), VIPROPI (600 mV/div), Motor Current (100 mA/div) PWM Operation at VM = 5 V Traces from top to bottom: OUT1 (10 V/div), OUT2 (10 V/div), Motor Current (1 A/div), VIPROPI (50 mV/div) PWM Operation at VM = 11 V Traces from top to bottom: IN1 (7 V/div), OUT2 (6 V/div), Motor Current (200 mA/div), VIPROPI (2 V/div) Stall Detection with IMODE = Hi-Z, SMODE = 1 Traces from top to bottom: nSTALL (4 V/div), TINRUSH (1 V/div), OUT2 (5 V/div), Motor Current (600 mA/div) PWM Operation at VM = 1.65 V Traces from top to bottom: IN1 (6 V/div), OUT2 (5 V/div), VIPROPI (600 mV/div), Motor Current (100 mA/div) PWM Operation at VM = 5 V Traces from top to bottom: OUT1 (10 V/div), OUT2 (10 V/div), Motor Current (1 A/div), VIPROPI (50 mV/div) PWM Operation at VM = 11 V Traces from top to bottom: IN1 (7 V/div), OUT2 (6 V/div), Motor Current (200 mA/div), VIPROPI (2 V/div) Stall Detection with IMODE = Hi-Z, SMODE = 1 Traces from top to bottom: nSTALL (4 V/div), TINRUSH (1 V/div), OUT2 (5 V/div), Motor Current (600 mA/div) PWM Operation at VM = 1.65 V Traces from top to bottom: IN1 (6 V/div), OUT2 (5 V/div), VIPROPI (600 mV/div), Motor Current (100 mA/div) PWM Operation at VM = 1.65 VTraces from top to bottom: IN1 (6 V/div), OUT2 (5 V/div), VIPROPI (600 mV/div), Motor Current (100 mA/div)IPROPI PWM Operation at VM = 5 V Traces from top to bottom: OUT1 (10 V/div), OUT2 (10 V/div), Motor Current (1 A/div), VIPROPI (50 mV/div) PWM Operation at VM = 5 VTraces from top to bottom: OUT1 (10 V/div), OUT2 (10 V/div), Motor Current (1 A/div), VIPROPI (50 mV/div)IPROPI PWM Operation at VM = 11 V Traces from top to bottom: IN1 (7 V/div), OUT2 (6 V/div), Motor Current (200 mA/div), VIPROPI (2 V/div) PWM Operation at VM = 11 VTraces from top to bottom: IN1 (7 V/div), OUT2 (6 V/div), Motor Current (200 mA/div), VIPROPI (2 V/div)IPROPI Stall Detection with IMODE = Hi-Z, SMODE = 1 Traces from top to bottom: nSTALL (4 V/div), TINRUSH (1 V/div), OUT2 (5 V/div), Motor Current (600 mA/div) Stall Detection with IMODE = Hi-Z, SMODE = 1Traces from top to bottom: nSTALL (4 V/div), TINRUSH (1 V/div), OUT2 (5 V/div), Motor Current (600 mA/div) Thermal Performance The datasheet-specified junction-to-ambient thermal resistance, RθJA, is primarily useful for comparing various drivers or approximating thermal performance. However, the actual system performance may be better or worse than this value depending on PCB stackup, routing, number of vias, and copper area around the thermal pad. The length of time the driver drives a particular current will also impact power dissipation and thermal performance. This section considers how to design for steady-state and transient thermal conditions. The data in this section was simulated using the following criteria: WSON (DSG package) 2-layer PCB (size 114.3 x 76.2 x 1.6 mm), standard FR4, 1-oz (35 mm copper thickness) or 2-oz copper thickness. Thermal vias are only present under the thermal pad (2 vias, 1.2mm spacing, 0.3 mm diameter, 0.025 mm Cu plating). Top layer: DRV8213 WSON package footprint and copper plane heatsink. Top layer copper area is varied in simulation. Bottom layer: ground plane thermally connected through vias under the thermal pad for DRV8213. Bottom layer copper area varies with top copper area. 4-layer PCB (size 114.3 x 76.2 x 1.6 mm), standard FR4. Outer planes are 1-oz (35 mm copper thickness) or 2-oz copper thickness. Inner planes are kept at 1-oz. Thermal vias are only present under the thermal pad (2 vias, 1.2mm spacing, 0.3 mm diameter, 0.025 mm Cu plating). Top layer: DRV8213 WSON package footprint and copper plane heatsink. Top layer copper area is varied in simulation. Mid layer 1: GND plane thermally connected to DRV8213 thermal pad through vias. The area of the ground plane is 74.2 mm x 74.2 mm. Mid layer 2: power plane, no thermal connection. The area of the power plane is 74.2 mm x 74.2 mm. Bottom layer: ground plane thermally connected through via stitching from the TOP and internal GND planes. Bottom layer copper area varies with top copper area. shows an example of the simulated board for the DSG package. shows the dimensions of the board that were varied for each simulation. WSON PCB model top layer Dimension A for 8-pin DSG package Cu area (mm2) Dimension A (mm) 2 15.11 4 20.98 8 29.27 16 40.99 WQFN (RTE package) 2-layer PCB (size 114.3 x 76.2 x 1.6 mm), standard FR4, 1-oz (35 mm copper thickness) or 2-oz copper thickness. Thermal vias are only present under the package footprint (5 vias, 1 mm pitch, 0.2 mm diameter, 0.025 mm Cu plating). Top layer: WQFN package footprint and traces. Bottom layer: ground plane thermally connected through vias under the package footprint. Bottom layer copper area is varied in simulation. 4-layer PCB (size 114.3 x 76.2 x 1.6 mm), standard FR4. Outer planes are 1-oz (35 mm copper thickness) or 2-oz copper thickness. Inner planes are kept at 1-oz. Thermal vias are only present under the package footprint (5 vias, 1 mm pitch, 0.2 mm diameter, 0.025 mm Cu plating). Top layer: WQFN package footprint and traces. Mid layer 1: GND plane thermally connected under package footprint through vias. The area of the ground plane is 74.2 mm x 74.2 mm. Mid layer 2: power plane, no thermal connection. The area of the power plane is 74.2 mm x 74.2 mm. Bottom layer: signal layer with small copper pad underneath the driver and thermally connected through via stitching from the TOP and internal GND plane. Bottom layer thermal pad is the same size as the package (3 mm x 3 mm). Bottom pad size remains constant. shows an example of the simulated board for the WQFN package. shows the dimensions of the board that were varied for each simulation. WQFN PCB model top layer Dimension A for 16-pin RTE package Cu area (cm2) Dimension A (mm) 2 14.14 4 20.00 8 28.28 16 40.00 Steady-State Thermal Performance "Steady-state" conditions assume that the motor driver operates with a constant RMS current over a long period of time. The figures in this section show how RθJA and ΨJB (junction-to-board characterization parameter) change depending on copper area, copper thickness, and number of layers of the PCB. More copper area, more layers, and thicker copper planes decrease RθJA and ΨJB, which indicate better thermal performance from the PCB layout. WSON, PCB junction-to-ambient thermal resistance vs copper area WSON, junction-to-board characterization parameter vs copper area WQFN, PCB junction-to-ambient thermal resistance vs copper area WQFN, junction-to-board characterization parameter vs copper area Transient Thermal Performance The motor driver may experience different transient driving conditions that cause large currents to flow for a short duration of time. These may include - Motor start-up when the rotor is initially stationary. Fault conditions when there is a supply or ground short to one of the motor outputs, and the overcurrent protection triggers. Briefly energizing a motor or solenoid for a limited time, then de-energizing. For these transient cases, the duration of drive time is another factor that impacts thermal performance in addition to copper area and thickness. In transient cases, the thermal impedance parameter ZθJA denotes the junction-to-ambient thermal performance. The figures in this section show the simulated thermal impedances for 1-oz and 2-oz copper layouts for the WSON and WQFN packages. These graphs indicate better thermal performance with short current pulses. For short periods of drive time, the device die size and package dominates the thermal performance. For longer drive pulses, board layout has a more significant impact on thermal performance. Both graphs show the curves for thermal impedance split due to number of layers and copper area as the duration of the drive pulse duration increases. Long pulses can be considered steady-state performance. WSON package junction-to-ambient thermal impedance for 1-oz copper layouts WSON package junction-to-ambient thermal impedance for 2-oz copper layouts WQFN package junction-to-ambient thermal impedance for 1-oz copper layouts WQFN package junction-to-ambient thermal impedance for 2-oz copper layouts Thermal Performance The datasheet-specified junction-to-ambient thermal resistance, RθJA, is primarily useful for comparing various drivers or approximating thermal performance. However, the actual system performance may be better or worse than this value depending on PCB stackup, routing, number of vias, and copper area around the thermal pad. The length of time the driver drives a particular current will also impact power dissipation and thermal performance. This section considers how to design for steady-state and transient thermal conditions. The data in this section was simulated using the following criteria: WSON (DSG package) 2-layer PCB (size 114.3 x 76.2 x 1.6 mm), standard FR4, 1-oz (35 mm copper thickness) or 2-oz copper thickness. Thermal vias are only present under the thermal pad (2 vias, 1.2mm spacing, 0.3 mm diameter, 0.025 mm Cu plating). Top layer: DRV8213 WSON package footprint and copper plane heatsink. Top layer copper area is varied in simulation. Bottom layer: ground plane thermally connected through vias under the thermal pad for DRV8213. Bottom layer copper area varies with top copper area. 4-layer PCB (size 114.3 x 76.2 x 1.6 mm), standard FR4. Outer planes are 1-oz (35 mm copper thickness) or 2-oz copper thickness. Inner planes are kept at 1-oz. Thermal vias are only present under the thermal pad (2 vias, 1.2mm spacing, 0.3 mm diameter, 0.025 mm Cu plating). Top layer: DRV8213 WSON package footprint and copper plane heatsink. Top layer copper area is varied in simulation. Mid layer 1: GND plane thermally connected to DRV8213 thermal pad through vias. The area of the ground plane is 74.2 mm x 74.2 mm. Mid layer 2: power plane, no thermal connection. The area of the power plane is 74.2 mm x 74.2 mm. Bottom layer: ground plane thermally connected through via stitching from the TOP and internal GND planes. Bottom layer copper area varies with top copper area. shows an example of the simulated board for the DSG package. shows the dimensions of the board that were varied for each simulation. WSON PCB model top layer Dimension A for 8-pin DSG package Cu area (mm2) Dimension A (mm) 2 15.11 4 20.98 8 29.27 16 40.99 WQFN (RTE package) 2-layer PCB (size 114.3 x 76.2 x 1.6 mm), standard FR4, 1-oz (35 mm copper thickness) or 2-oz copper thickness. Thermal vias are only present under the package footprint (5 vias, 1 mm pitch, 0.2 mm diameter, 0.025 mm Cu plating). Top layer: WQFN package footprint and traces. Bottom layer: ground plane thermally connected through vias under the package footprint. Bottom layer copper area is varied in simulation. 4-layer PCB (size 114.3 x 76.2 x 1.6 mm), standard FR4. Outer planes are 1-oz (35 mm copper thickness) or 2-oz copper thickness. Inner planes are kept at 1-oz. Thermal vias are only present under the package footprint (5 vias, 1 mm pitch, 0.2 mm diameter, 0.025 mm Cu plating). Top layer: WQFN package footprint and traces. Mid layer 1: GND plane thermally connected under package footprint through vias. The area of the ground plane is 74.2 mm x 74.2 mm. Mid layer 2: power plane, no thermal connection. The area of the power plane is 74.2 mm x 74.2 mm. Bottom layer: signal layer with small copper pad underneath the driver and thermally connected through via stitching from the TOP and internal GND plane. Bottom layer thermal pad is the same size as the package (3 mm x 3 mm). Bottom pad size remains constant. shows an example of the simulated board for the WQFN package. shows the dimensions of the board that were varied for each simulation. WQFN PCB model top layer Dimension A for 16-pin RTE package Cu area (cm2) Dimension A (mm) 2 14.14 4 20.00 8 28.28 16 40.00 The datasheet-specified junction-to-ambient thermal resistance, RθJA, is primarily useful for comparing various drivers or approximating thermal performance. However, the actual system performance may be better or worse than this value depending on PCB stackup, routing, number of vias, and copper area around the thermal pad. The length of time the driver drives a particular current will also impact power dissipation and thermal performance. This section considers how to design for steady-state and transient thermal conditions. The data in this section was simulated using the following criteria: WSON (DSG package) 2-layer PCB (size 114.3 x 76.2 x 1.6 mm), standard FR4, 1-oz (35 mm copper thickness) or 2-oz copper thickness. Thermal vias are only present under the thermal pad (2 vias, 1.2mm spacing, 0.3 mm diameter, 0.025 mm Cu plating). Top layer: DRV8213 WSON package footprint and copper plane heatsink. Top layer copper area is varied in simulation. Bottom layer: ground plane thermally connected through vias under the thermal pad for DRV8213. Bottom layer copper area varies with top copper area. 4-layer PCB (size 114.3 x 76.2 x 1.6 mm), standard FR4. Outer planes are 1-oz (35 mm copper thickness) or 2-oz copper thickness. Inner planes are kept at 1-oz. Thermal vias are only present under the thermal pad (2 vias, 1.2mm spacing, 0.3 mm diameter, 0.025 mm Cu plating). Top layer: DRV8213 WSON package footprint and copper plane heatsink. Top layer copper area is varied in simulation. Mid layer 1: GND plane thermally connected to DRV8213 thermal pad through vias. The area of the ground plane is 74.2 mm x 74.2 mm. Mid layer 2: power plane, no thermal connection. The area of the power plane is 74.2 mm x 74.2 mm. Bottom layer: ground plane thermally connected through via stitching from the TOP and internal GND planes. Bottom layer copper area varies with top copper area. shows an example of the simulated board for the DSG package. shows the dimensions of the board that were varied for each simulation. WSON PCB model top layer Dimension A for 8-pin DSG package Cu area (mm2) Dimension A (mm) 2 15.11 4 20.98 8 29.27 16 40.99 WQFN (RTE package) 2-layer PCB (size 114.3 x 76.2 x 1.6 mm), standard FR4, 1-oz (35 mm copper thickness) or 2-oz copper thickness. Thermal vias are only present under the package footprint (5 vias, 1 mm pitch, 0.2 mm diameter, 0.025 mm Cu plating). Top layer: WQFN package footprint and traces. Bottom layer: ground plane thermally connected through vias under the package footprint. Bottom layer copper area is varied in simulation. 4-layer PCB (size 114.3 x 76.2 x 1.6 mm), standard FR4. Outer planes are 1-oz (35 mm copper thickness) or 2-oz copper thickness. Inner planes are kept at 1-oz. Thermal vias are only present under the package footprint (5 vias, 1 mm pitch, 0.2 mm diameter, 0.025 mm Cu plating). Top layer: WQFN package footprint and traces. Mid layer 1: GND plane thermally connected under package footprint through vias. The area of the ground plane is 74.2 mm x 74.2 mm. Mid layer 2: power plane, no thermal connection. The area of the power plane is 74.2 mm x 74.2 mm. Bottom layer: signal layer with small copper pad underneath the driver and thermally connected through via stitching from the TOP and internal GND plane. Bottom layer thermal pad is the same size as the package (3 mm x 3 mm). Bottom pad size remains constant. shows an example of the simulated board for the WQFN package. shows the dimensions of the board that were varied for each simulation. WQFN PCB model top layer Dimension A for 16-pin RTE package Cu area (cm2) Dimension A (mm) 2 14.14 4 20.00 8 28.28 16 40.00 The datasheet-specified junction-to-ambient thermal resistance, RθJA, is primarily useful for comparing various drivers or approximating thermal performance. However, the actual system performance may be better or worse than this value depending on PCB stackup, routing, number of vias, and copper area around the thermal pad. The length of time the driver drives a particular current will also impact power dissipation and thermal performance. This section considers how to design for steady-state and transient thermal conditions.θJAThe data in this section was simulated using the following criteria: WSON (DSG package) WSON (DSG package) 2-layer PCB (size 114.3 x 76.2 x 1.6 mm), standard FR4, 1-oz (35 mm copper thickness) or 2-oz copper thickness. Thermal vias are only present under the thermal pad (2 vias, 1.2mm spacing, 0.3 mm diameter, 0.025 mm Cu plating). Top layer: DRV8213 WSON package footprint and copper plane heatsink. Top layer copper area is varied in simulation. Bottom layer: ground plane thermally connected through vias under the thermal pad for DRV8213. Bottom layer copper area varies with top copper area. 4-layer PCB (size 114.3 x 76.2 x 1.6 mm), standard FR4. Outer planes are 1-oz (35 mm copper thickness) or 2-oz copper thickness. Inner planes are kept at 1-oz. Thermal vias are only present under the thermal pad (2 vias, 1.2mm spacing, 0.3 mm diameter, 0.025 mm Cu plating). Top layer: DRV8213 WSON package footprint and copper plane heatsink. Top layer copper area is varied in simulation. Mid layer 1: GND plane thermally connected to DRV8213 thermal pad through vias. The area of the ground plane is 74.2 mm x 74.2 mm. Mid layer 2: power plane, no thermal connection. The area of the power plane is 74.2 mm x 74.2 mm. Bottom layer: ground plane thermally connected through via stitching from the TOP and internal GND planes. Bottom layer copper area varies with top copper area. 2-layer PCB (size 114.3 x 76.2 x 1.6 mm), standard FR4, 1-oz (35 mm copper thickness) or 2-oz copper thickness. Thermal vias are only present under the thermal pad (2 vias, 1.2mm spacing, 0.3 mm diameter, 0.025 mm Cu plating). Top layer: DRV8213 WSON package footprint and copper plane heatsink. Top layer copper area is varied in simulation. Bottom layer: ground plane thermally connected through vias under the thermal pad for DRV8213. Bottom layer copper area varies with top copper area. Top layer: DRV8213 WSON package footprint and copper plane heatsink. Top layer copper area is varied in simulation. Bottom layer: ground plane thermally connected through vias under the thermal pad for DRV8213. Bottom layer copper area varies with top copper area. Top layer: DRV8213 WSON package footprint and copper plane heatsink. Top layer copper area is varied in simulation.Bottom layer: ground plane thermally connected through vias under the thermal pad for DRV8213. Bottom layer copper area varies with top copper area.4-layer PCB (size 114.3 x 76.2 x 1.6 mm), standard FR4. Outer planes are 1-oz (35 mm copper thickness) or 2-oz copper thickness. Inner planes are kept at 1-oz. Thermal vias are only present under the thermal pad (2 vias, 1.2mm spacing, 0.3 mm diameter, 0.025 mm Cu plating). Top layer: DRV8213 WSON package footprint and copper plane heatsink. Top layer copper area is varied in simulation. Mid layer 1: GND plane thermally connected to DRV8213 thermal pad through vias. The area of the ground plane is 74.2 mm x 74.2 mm. Mid layer 2: power plane, no thermal connection. The area of the power plane is 74.2 mm x 74.2 mm. Bottom layer: ground plane thermally connected through via stitching from the TOP and internal GND planes. Bottom layer copper area varies with top copper area. Top layer: DRV8213 WSON package footprint and copper plane heatsink. Top layer copper area is varied in simulation. Mid layer 1: GND plane thermally connected to DRV8213 thermal pad through vias. The area of the ground plane is 74.2 mm x 74.2 mm. Mid layer 2: power plane, no thermal connection. The area of the power plane is 74.2 mm x 74.2 mm. Bottom layer: ground plane thermally connected through via stitching from the TOP and internal GND planes. Bottom layer copper area varies with top copper area. Top layer: DRV8213 WSON package footprint and copper plane heatsink. Top layer copper area is varied in simulation.Mid layer 1: GND plane thermally connected to DRV8213 thermal pad through vias. The area of the ground plane is 74.2 mm x 74.2 mm.Mid layer 2: power plane, no thermal connection. The area of the power plane is 74.2 mm x 74.2 mm.Bottom layer: ground plane thermally connected through via stitching from the TOP and internal GND planes. Bottom layer copper area varies with top copper area. shows an example of the simulated board for the DSG package. shows the dimensions of the board that were varied for each simulation. WSON PCB model top layer WSON PCB model top layer Dimension A for 8-pin DSG package Cu area (mm2) Dimension A (mm) 2 15.11 4 20.98 8 29.27 16 40.99 Dimension A for 8-pin DSG package Cu area (mm2) Dimension A (mm) 2 15.11 4 20.98 8 29.27 16 40.99 Cu area (mm2) Dimension A (mm) Cu area (mm2) Dimension A (mm) Cu area (mm2)2Dimension A (mm) 2 15.11 4 20.98 8 29.27 16 40.99 2 15.11 215.11 4 20.98 420.98 8 29.27 829.27 16 40.99 1640.99 WQFN (RTE package) 2-layer PCB (size 114.3 x 76.2 x 1.6 mm), standard FR4, 1-oz (35 mm copper thickness) or 2-oz copper thickness. Thermal vias are only present under the package footprint (5 vias, 1 mm pitch, 0.2 mm diameter, 0.025 mm Cu plating). Top layer: WQFN package footprint and traces. Bottom layer: ground plane thermally connected through vias under the package footprint. Bottom layer copper area is varied in simulation. 4-layer PCB (size 114.3 x 76.2 x 1.6 mm), standard FR4. Outer planes are 1-oz (35 mm copper thickness) or 2-oz copper thickness. Inner planes are kept at 1-oz. Thermal vias are only present under the package footprint (5 vias, 1 mm pitch, 0.2 mm diameter, 0.025 mm Cu plating). Top layer: WQFN package footprint and traces. Mid layer 1: GND plane thermally connected under package footprint through vias. The area of the ground plane is 74.2 mm x 74.2 mm. Mid layer 2: power plane, no thermal connection. The area of the power plane is 74.2 mm x 74.2 mm. Bottom layer: signal layer with small copper pad underneath the driver and thermally connected through via stitching from the TOP and internal GND plane. Bottom layer thermal pad is the same size as the package (3 mm x 3 mm). Bottom pad size remains constant. shows an example of the simulated board for the WQFN package. shows the dimensions of the board that were varied for each simulation. WQFN PCB model top layer Dimension A for 16-pin RTE package Cu area (cm2) Dimension A (mm) 2 14.14 4 20.00 8 28.28 16 40.00 WQFN (RTE package) WQFN (RTE package) 2-layer PCB (size 114.3 x 76.2 x 1.6 mm), standard FR4, 1-oz (35 mm copper thickness) or 2-oz copper thickness. Thermal vias are only present under the package footprint (5 vias, 1 mm pitch, 0.2 mm diameter, 0.025 mm Cu plating). Top layer: WQFN package footprint and traces. Bottom layer: ground plane thermally connected through vias under the package footprint. Bottom layer copper area is varied in simulation. 4-layer PCB (size 114.3 x 76.2 x 1.6 mm), standard FR4. Outer planes are 1-oz (35 mm copper thickness) or 2-oz copper thickness. Inner planes are kept at 1-oz. Thermal vias are only present under the package footprint (5 vias, 1 mm pitch, 0.2 mm diameter, 0.025 mm Cu plating). Top layer: WQFN package footprint and traces. Mid layer 1: GND plane thermally connected under package footprint through vias. The area of the ground plane is 74.2 mm x 74.2 mm. Mid layer 2: power plane, no thermal connection. The area of the power plane is 74.2 mm x 74.2 mm. Bottom layer: signal layer with small copper pad underneath the driver and thermally connected through via stitching from the TOP and internal GND plane. Bottom layer thermal pad is the same size as the package (3 mm x 3 mm). Bottom pad size remains constant. 2-layer PCB (size 114.3 x 76.2 x 1.6 mm), standard FR4, 1-oz (35 mm copper thickness) or 2-oz copper thickness. Thermal vias are only present under the package footprint (5 vias, 1 mm pitch, 0.2 mm diameter, 0.025 mm Cu plating). Top layer: WQFN package footprint and traces. Bottom layer: ground plane thermally connected through vias under the package footprint. Bottom layer copper area is varied in simulation. Top layer: WQFN package footprint and traces. Bottom layer: ground plane thermally connected through vias under the package footprint. Bottom layer copper area is varied in simulation. Top layer: WQFN package footprint and traces.Bottom layer: ground plane thermally connected through vias under the package footprint. Bottom layer copper area is varied in simulation.4-layer PCB (size 114.3 x 76.2 x 1.6 mm), standard FR4. Outer planes are 1-oz (35 mm copper thickness) or 2-oz copper thickness. Inner planes are kept at 1-oz. Thermal vias are only present under the package footprint (5 vias, 1 mm pitch, 0.2 mm diameter, 0.025 mm Cu plating). Top layer: WQFN package footprint and traces. Mid layer 1: GND plane thermally connected under package footprint through vias. The area of the ground plane is 74.2 mm x 74.2 mm. Mid layer 2: power plane, no thermal connection. The area of the power plane is 74.2 mm x 74.2 mm. Bottom layer: signal layer with small copper pad underneath the driver and thermally connected through via stitching from the TOP and internal GND plane. Bottom layer thermal pad is the same size as the package (3 mm x 3 mm). Bottom pad size remains constant. Top layer: WQFN package footprint and traces. Mid layer 1: GND plane thermally connected under package footprint through vias. The area of the ground plane is 74.2 mm x 74.2 mm. Mid layer 2: power plane, no thermal connection. The area of the power plane is 74.2 mm x 74.2 mm. Bottom layer: signal layer with small copper pad underneath the driver and thermally connected through via stitching from the TOP and internal GND plane. Bottom layer thermal pad is the same size as the package (3 mm x 3 mm). Bottom pad size remains constant. Top layer: WQFN package footprint and traces.Mid layer 1: GND plane thermally connected under package footprint through vias. The area of the ground plane is 74.2 mm x 74.2 mm.Mid layer 2: power plane, no thermal connection. The area of the power plane is 74.2 mm x 74.2 mm.Bottom layer: signal layer with small copper pad underneath the driver and thermally connected through via stitching from the TOP and internal GND plane. Bottom layer thermal pad is the same size as the package (3 mm x 3 mm). Bottom pad size remains constant. shows an example of the simulated board for the WQFN package. shows the dimensions of the board that were varied for each simulation. WQFN PCB model top layer WQFN PCB model top layer Dimension A for 16-pin RTE package Cu area (cm2) Dimension A (mm) 2 14.14 4 20.00 8 28.28 16 40.00 Dimension A for 16-pin RTE package Cu area (cm2) Dimension A (mm) 2 14.14 4 20.00 8 28.28 16 40.00 Cu area (cm2) Dimension A (mm) Cu area (cm2) Dimension A (mm) Cu area (cm2)2Dimension A (mm) 2 14.14 4 20.00 8 28.28 16 40.00 2 14.14 214.14 4 20.00 420.00 8 28.28 828.28 16 40.00 1640.00 Steady-State Thermal Performance "Steady-state" conditions assume that the motor driver operates with a constant RMS current over a long period of time. The figures in this section show how RθJA and ΨJB (junction-to-board characterization parameter) change depending on copper area, copper thickness, and number of layers of the PCB. More copper area, more layers, and thicker copper planes decrease RθJA and ΨJB, which indicate better thermal performance from the PCB layout. WSON, PCB junction-to-ambient thermal resistance vs copper area WSON, junction-to-board characterization parameter vs copper area WQFN, PCB junction-to-ambient thermal resistance vs copper area WQFN, junction-to-board characterization parameter vs copper area Steady-State Thermal Performance "Steady-state" conditions assume that the motor driver operates with a constant RMS current over a long period of time. The figures in this section show how RθJA and ΨJB (junction-to-board characterization parameter) change depending on copper area, copper thickness, and number of layers of the PCB. More copper area, more layers, and thicker copper planes decrease RθJA and ΨJB, which indicate better thermal performance from the PCB layout. WSON, PCB junction-to-ambient thermal resistance vs copper area WSON, junction-to-board characterization parameter vs copper area WQFN, PCB junction-to-ambient thermal resistance vs copper area WQFN, junction-to-board characterization parameter vs copper area "Steady-state" conditions assume that the motor driver operates with a constant RMS current over a long period of time. The figures in this section show how RθJA and ΨJB (junction-to-board characterization parameter) change depending on copper area, copper thickness, and number of layers of the PCB. More copper area, more layers, and thicker copper planes decrease RθJA and ΨJB, which indicate better thermal performance from the PCB layout. WSON, PCB junction-to-ambient thermal resistance vs copper area WSON, junction-to-board characterization parameter vs copper area WQFN, PCB junction-to-ambient thermal resistance vs copper area WQFN, junction-to-board characterization parameter vs copper area "Steady-state" conditions assume that the motor driver operates with a constant RMS current over a long period of time. The figures in this section show how RθJA and ΨJB (junction-to-board characterization parameter) change depending on copper area, copper thickness, and number of layers of the PCB. More copper area, more layers, and thicker copper planes decrease RθJA and ΨJB, which indicate better thermal performance from the PCB layout.θJAJBθJAJB WSON, PCB junction-to-ambient thermal resistance vs copper area WSON, PCB junction-to-ambient thermal resistance vs copper area WSON, junction-to-board characterization parameter vs copper area WSON, junction-to-board characterization parameter vs copper area WQFN, PCB junction-to-ambient thermal resistance vs copper area WQFN, PCB junction-to-ambient thermal resistance vs copper area WQFN, junction-to-board characterization parameter vs copper area WQFN, junction-to-board characterization parameter vs copper area Transient Thermal Performance The motor driver may experience different transient driving conditions that cause large currents to flow for a short duration of time. These may include - Motor start-up when the rotor is initially stationary. Fault conditions when there is a supply or ground short to one of the motor outputs, and the overcurrent protection triggers. Briefly energizing a motor or solenoid for a limited time, then de-energizing. For these transient cases, the duration of drive time is another factor that impacts thermal performance in addition to copper area and thickness. In transient cases, the thermal impedance parameter ZθJA denotes the junction-to-ambient thermal performance. The figures in this section show the simulated thermal impedances for 1-oz and 2-oz copper layouts for the WSON and WQFN packages. These graphs indicate better thermal performance with short current pulses. For short periods of drive time, the device die size and package dominates the thermal performance. For longer drive pulses, board layout has a more significant impact on thermal performance. Both graphs show the curves for thermal impedance split due to number of layers and copper area as the duration of the drive pulse duration increases. Long pulses can be considered steady-state performance. WSON package junction-to-ambient thermal impedance for 1-oz copper layouts WSON package junction-to-ambient thermal impedance for 2-oz copper layouts WQFN package junction-to-ambient thermal impedance for 1-oz copper layouts WQFN package junction-to-ambient thermal impedance for 2-oz copper layouts Transient Thermal Performance The motor driver may experience different transient driving conditions that cause large currents to flow for a short duration of time. These may include - Motor start-up when the rotor is initially stationary. Fault conditions when there is a supply or ground short to one of the motor outputs, and the overcurrent protection triggers. Briefly energizing a motor or solenoid for a limited time, then de-energizing. For these transient cases, the duration of drive time is another factor that impacts thermal performance in addition to copper area and thickness. In transient cases, the thermal impedance parameter ZθJA denotes the junction-to-ambient thermal performance. The figures in this section show the simulated thermal impedances for 1-oz and 2-oz copper layouts for the WSON and WQFN packages. These graphs indicate better thermal performance with short current pulses. For short periods of drive time, the device die size and package dominates the thermal performance. For longer drive pulses, board layout has a more significant impact on thermal performance. Both graphs show the curves for thermal impedance split due to number of layers and copper area as the duration of the drive pulse duration increases. Long pulses can be considered steady-state performance. WSON package junction-to-ambient thermal impedance for 1-oz copper layouts WSON package junction-to-ambient thermal impedance for 2-oz copper layouts WQFN package junction-to-ambient thermal impedance for 1-oz copper layouts WQFN package junction-to-ambient thermal impedance for 2-oz copper layouts The motor driver may experience different transient driving conditions that cause large currents to flow for a short duration of time. These may include - Motor start-up when the rotor is initially stationary. Fault conditions when there is a supply or ground short to one of the motor outputs, and the overcurrent protection triggers. Briefly energizing a motor or solenoid for a limited time, then de-energizing. For these transient cases, the duration of drive time is another factor that impacts thermal performance in addition to copper area and thickness. In transient cases, the thermal impedance parameter ZθJA denotes the junction-to-ambient thermal performance. The figures in this section show the simulated thermal impedances for 1-oz and 2-oz copper layouts for the WSON and WQFN packages. These graphs indicate better thermal performance with short current pulses. For short periods of drive time, the device die size and package dominates the thermal performance. For longer drive pulses, board layout has a more significant impact on thermal performance. Both graphs show the curves for thermal impedance split due to number of layers and copper area as the duration of the drive pulse duration increases. Long pulses can be considered steady-state performance. WSON package junction-to-ambient thermal impedance for 1-oz copper layouts WSON package junction-to-ambient thermal impedance for 2-oz copper layouts WQFN package junction-to-ambient thermal impedance for 1-oz copper layouts WQFN package junction-to-ambient thermal impedance for 2-oz copper layouts The motor driver may experience different transient driving conditions that cause large currents to flow for a short duration of time. These may include - Motor start-up when the rotor is initially stationary. Fault conditions when there is a supply or ground short to one of the motor outputs, and the overcurrent protection triggers. Briefly energizing a motor or solenoid for a limited time, then de-energizing. Motor start-up when the rotor is initially stationary.Fault conditions when there is a supply or ground short to one of the motor outputs, and the overcurrent protection triggers.Briefly energizing a motor or solenoid for a limited time, then de-energizing.For these transient cases, the duration of drive time is another factor that impacts thermal performance in addition to copper area and thickness. In transient cases, the thermal impedance parameter ZθJA denotes the junction-to-ambient thermal performance. The figures in this section show the simulated thermal impedances for 1-oz and 2-oz copper layouts for the WSON and WQFN packages. These graphs indicate better thermal performance with short current pulses. For short periods of drive time, the device die size and package dominates the thermal performance. For longer drive pulses, board layout has a more significant impact on thermal performance. Both graphs show the curves for thermal impedance split due to number of layers and copper area as the duration of the drive pulse duration increases. Long pulses can be considered steady-state performance.θJA WSON package junction-to-ambient thermal impedance for 1-oz copper layouts WSON package junction-to-ambient thermal impedance for 1-oz copper layouts WSON package junction-to-ambient thermal impedance for 2-oz copper layouts WSON package junction-to-ambient thermal impedance for 2-oz copper layouts WQFN package junction-to-ambient thermal impedance for 1-oz copper layouts WQFN package junction-to-ambient thermal impedance for 1-oz copper layouts WQFN package junction-to-ambient thermal impedance for 2-oz copper layouts WQFN package junction-to-ambient thermal impedance for 2-oz copper layouts Power Supply Recommendations Bulk Capacitance Having appropriate local bulk capacitance is an important factor in motor drive system design. Having more bulk capacitance is generally beneficial, while the disadvantages are increased cost and physical size. The amount of local capacitance needed depends on a variety of factors, including: The highest current required by the motor system The capacitance of the power supply and ability to source current The amount of parasitic inductance between the power supply and motor system The acceptable voltage ripple The type of motor used (brushed DC, brushless DC, stepper) The motor braking method The inductance between the power supply and motor drive system limits how the rate current can change from the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage remains stable and high current can be quickly supplied. The data sheet generally provides a recommended value, but system-level testing is required to determine the appropriate sized bulk capacitor. Example Setup of Motor Drive System With External Power Supply The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases when the motor transfers energy to the supply. Power Supply Recommendations Bulk Capacitance Having appropriate local bulk capacitance is an important factor in motor drive system design. Having more bulk capacitance is generally beneficial, while the disadvantages are increased cost and physical size. The amount of local capacitance needed depends on a variety of factors, including: The highest current required by the motor system The capacitance of the power supply and ability to source current The amount of parasitic inductance between the power supply and motor system The acceptable voltage ripple The type of motor used (brushed DC, brushless DC, stepper) The motor braking method The inductance between the power supply and motor drive system limits how the rate current can change from the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage remains stable and high current can be quickly supplied. The data sheet generally provides a recommended value, but system-level testing is required to determine the appropriate sized bulk capacitor. Example Setup of Motor Drive System With External Power Supply The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases when the motor transfers energy to the supply. Bulk Capacitance Having appropriate local bulk capacitance is an important factor in motor drive system design. Having more bulk capacitance is generally beneficial, while the disadvantages are increased cost and physical size. The amount of local capacitance needed depends on a variety of factors, including: The highest current required by the motor system The capacitance of the power supply and ability to source current The amount of parasitic inductance between the power supply and motor system The acceptable voltage ripple The type of motor used (brushed DC, brushless DC, stepper) The motor braking method The inductance between the power supply and motor drive system limits how the rate current can change from the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage remains stable and high current can be quickly supplied. The data sheet generally provides a recommended value, but system-level testing is required to determine the appropriate sized bulk capacitor. Example Setup of Motor Drive System With External Power Supply The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases when the motor transfers energy to the supply. Having appropriate local bulk capacitance is an important factor in motor drive system design. Having more bulk capacitance is generally beneficial, while the disadvantages are increased cost and physical size. The amount of local capacitance needed depends on a variety of factors, including: The highest current required by the motor system The capacitance of the power supply and ability to source current The amount of parasitic inductance between the power supply and motor system The acceptable voltage ripple The type of motor used (brushed DC, brushless DC, stepper) The motor braking method The inductance between the power supply and motor drive system limits how the rate current can change from the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage remains stable and high current can be quickly supplied. The data sheet generally provides a recommended value, but system-level testing is required to determine the appropriate sized bulk capacitor. Example Setup of Motor Drive System With External Power Supply The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases when the motor transfers energy to the supply. Having appropriate local bulk capacitance is an important factor in motor drive system design. Having more bulk capacitance is generally beneficial, while the disadvantages are increased cost and physical size.The amount of local capacitance needed depends on a variety of factors, including: The highest current required by the motor system The capacitance of the power supply and ability to source current The amount of parasitic inductance between the power supply and motor system The acceptable voltage ripple The type of motor used (brushed DC, brushless DC, stepper) The motor braking method The highest current required by the motor systemThe capacitance of the power supply and ability to source currentThe amount of parasitic inductance between the power supply and motor systemThe acceptable voltage rippleThe type of motor used (brushed DC, brushless DC, stepper)The motor braking methodThe inductance between the power supply and motor drive system limits how the rate current can change from the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage remains stable and high current can be quickly supplied.The data sheet generally provides a recommended value, but system-level testing is required to determine the appropriate sized bulk capacitor. Example Setup of Motor Drive System With External Power Supply Example Setup of Motor Drive System With External Power SupplyThe voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases when the motor transfers energy to the supply. Layout Layout Guidelines Since the DRV8213 integrates power MOSFETs capable of driving high current, careful attention should be paid to the layout design and external component placement. Some design and layout guidelines are provided below. Low ESR ceramic capacitors should be utilized for the VM to GND bypass capacitor. X5R and X7R types are recommended. The VM power supply capacitors should be placed as close to the device as possible to minimize the loop inductance. The VM power supply bulk capacitor can be of ceramic or electrolytic type, but should also be placed as close as possible to the device to minimize the loop inductance. VM, OUT1, OUT2, and GND carry the high current from the power supply to the outputs and back to ground. Thick metal routing should be utilized for these traces as is feasible. The device thermal pad should be attached to the PCB top layer ground plane and internal ground plane (when available) through thermal vias to maximize the PCB heat sinking. A recommended land pattern for the thermal vias is provided in the package drawing section. The copper plane area attached to the thermal pad should be maximized to ensure optimal heat sinking. Layout Layout Guidelines Since the DRV8213 integrates power MOSFETs capable of driving high current, careful attention should be paid to the layout design and external component placement. Some design and layout guidelines are provided below. Low ESR ceramic capacitors should be utilized for the VM to GND bypass capacitor. X5R and X7R types are recommended. The VM power supply capacitors should be placed as close to the device as possible to minimize the loop inductance. The VM power supply bulk capacitor can be of ceramic or electrolytic type, but should also be placed as close as possible to the device to minimize the loop inductance. VM, OUT1, OUT2, and GND carry the high current from the power supply to the outputs and back to ground. Thick metal routing should be utilized for these traces as is feasible. The device thermal pad should be attached to the PCB top layer ground plane and internal ground plane (when available) through thermal vias to maximize the PCB heat sinking. A recommended land pattern for the thermal vias is provided in the package drawing section. The copper plane area attached to the thermal pad should be maximized to ensure optimal heat sinking. Layout Guidelines Since the DRV8213 integrates power MOSFETs capable of driving high current, careful attention should be paid to the layout design and external component placement. Some design and layout guidelines are provided below. Low ESR ceramic capacitors should be utilized for the VM to GND bypass capacitor. X5R and X7R types are recommended. The VM power supply capacitors should be placed as close to the device as possible to minimize the loop inductance. The VM power supply bulk capacitor can be of ceramic or electrolytic type, but should also be placed as close as possible to the device to minimize the loop inductance. VM, OUT1, OUT2, and GND carry the high current from the power supply to the outputs and back to ground. Thick metal routing should be utilized for these traces as is feasible. The device thermal pad should be attached to the PCB top layer ground plane and internal ground plane (when available) through thermal vias to maximize the PCB heat sinking. A recommended land pattern for the thermal vias is provided in the package drawing section. The copper plane area attached to the thermal pad should be maximized to ensure optimal heat sinking. Since the DRV8213 integrates power MOSFETs capable of driving high current, careful attention should be paid to the layout design and external component placement. Some design and layout guidelines are provided below. Low ESR ceramic capacitors should be utilized for the VM to GND bypass capacitor. X5R and X7R types are recommended. The VM power supply capacitors should be placed as close to the device as possible to minimize the loop inductance. The VM power supply bulk capacitor can be of ceramic or electrolytic type, but should also be placed as close as possible to the device to minimize the loop inductance. VM, OUT1, OUT2, and GND carry the high current from the power supply to the outputs and back to ground. Thick metal routing should be utilized for these traces as is feasible. The device thermal pad should be attached to the PCB top layer ground plane and internal ground plane (when available) through thermal vias to maximize the PCB heat sinking. A recommended land pattern for the thermal vias is provided in the package drawing section. The copper plane area attached to the thermal pad should be maximized to ensure optimal heat sinking. Since the DRV8213 integrates power MOSFETs capable of driving high current, careful attention should be paid to the layout design and external component placement. Some design and layout guidelines are provided below.DRV8213 Low ESR ceramic capacitors should be utilized for the VM to GND bypass capacitor. X5R and X7R types are recommended. The VM power supply capacitors should be placed as close to the device as possible to minimize the loop inductance. The VM power supply bulk capacitor can be of ceramic or electrolytic type, but should also be placed as close as possible to the device to minimize the loop inductance. VM, OUT1, OUT2, and GND carry the high current from the power supply to the outputs and back to ground. Thick metal routing should be utilized for these traces as is feasible. The device thermal pad should be attached to the PCB top layer ground plane and internal ground plane (when available) through thermal vias to maximize the PCB heat sinking. A recommended land pattern for the thermal vias is provided in the package drawing section. The copper plane area attached to the thermal pad should be maximized to ensure optimal heat sinking. Low ESR ceramic capacitors should be utilized for the VM to GND bypass capacitor. X5R and X7R types are recommended.The VM power supply capacitors should be placed as close to the device as possible to minimize the loop inductance.The VM power supply bulk capacitor can be of ceramic or electrolytic type, but should also be placed as close as possible to the device to minimize the loop inductance.VM, OUT1, OUT2, and GND carry the high current from the power supply to the outputs and back to ground. Thick metal routing should be utilized for these traces as is feasible.GNDThe device thermal pad should be attached to the PCB top layer ground plane and internal ground plane (when available) through thermal vias to maximize the PCB heat sinking.A recommended land pattern for the thermal vias is provided in the package drawing section.The copper plane area attached to the thermal pad should be maximized to ensure optimal heat sinking. Device and Documentation Support Documentation Support Related Documentation For related documentation, see the following: Texas Instruments, Calculating Motor Driver Power Dissipation application report Texas Instruments, Current Recirculation and Decay Modes application report Texas Instruments, PowerPAD™ Made Easy application report Texas Instruments, PowerPAD™ Thermally Enhanced Package application report Texas Instruments, Understanding Motor Driver Current Ratings application report Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. Community Resources Trademarks Device and Documentation Support Documentation Support Related Documentation For related documentation, see the following: Texas Instruments, Calculating Motor Driver Power Dissipation application report Texas Instruments, Current Recirculation and Decay Modes application report Texas Instruments, PowerPAD™ Made Easy application report Texas Instruments, PowerPAD™ Thermally Enhanced Package application report Texas Instruments, Understanding Motor Driver Current Ratings application report Documentation Support Related Documentation For related documentation, see the following: Texas Instruments, Calculating Motor Driver Power Dissipation application report Texas Instruments, Current Recirculation and Decay Modes application report Texas Instruments, PowerPAD™ Made Easy application report Texas Instruments, PowerPAD™ Thermally Enhanced Package application report Texas Instruments, Understanding Motor Driver Current Ratings application report Related Documentation For related documentation, see the following: Texas Instruments, Calculating Motor Driver Power Dissipation application report Texas Instruments, Current Recirculation and Decay Modes application report Texas Instruments, PowerPAD™ Made Easy application report Texas Instruments, PowerPAD™ Thermally Enhanced Package application report Texas Instruments, Understanding Motor Driver Current Ratings application report For related documentation, see the following: Texas Instruments, Calculating Motor Driver Power Dissipation application report Texas Instruments, Current Recirculation and Decay Modes application report Texas Instruments, PowerPAD™ Made Easy application report Texas Instruments, PowerPAD™ Thermally Enhanced Package application report Texas Instruments, Understanding Motor Driver Current Ratings application report For related documentation, see the following: Texas Instruments, Calculating Motor Driver Power Dissipation application report Texas Instruments, Current Recirculation and Decay Modes application report Texas Instruments, PowerPAD™ Made Easy application report Texas Instruments, PowerPAD™ Thermally Enhanced Package application report Texas Instruments, Understanding Motor Driver Current Ratings application report Texas Instruments, Calculating Motor Driver Power Dissipation application report Calculating Motor Driver Power Dissipation application reportCalculating Motor Driver Power DissipationTexas Instruments, Current Recirculation and Decay Modes application report Current Recirculation and Decay Modes application reportCurrent Recirculation and Decay ModesTexas Instruments, PowerPAD™ Made Easy application report PowerPAD™ Made Easy application reportPowerPAD™ Made EasyTexas Instruments, PowerPAD™ Thermally Enhanced Package application report PowerPAD™ Thermally Enhanced Package application reportPowerPAD™ Thermally Enhanced PackageTexas Instruments, Understanding Motor Driver Current Ratings application report Understanding Motor Driver Current Ratings application reportUnderstanding Motor Driver Current Ratings Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.Alert me Community Resources Community Resources Trademarks Trademarks Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Tape and Reel Information Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant DRV8213DSGR WSON DSG 8 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2 DRV8213RTER WQFN RTE 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DRV8213DSGR WSON DSG 8 3000 2.0 2.0 0.8 DRV8213RTER WQFN RTE 16 3000 3.0 3.0 0.8 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Tape and Reel Information Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant DRV8213DSGR WSON DSG 8 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2 DRV8213RTER WQFN RTE 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DRV8213DSGR WSON DSG 8 3000 2.0 2.0 0.8 DRV8213RTER WQFN RTE 16 3000 3.0 3.0 0.8 Tape and Reel Information Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant DRV8213DSGR WSON DSG 8 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2 DRV8213RTER WQFN RTE 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DRV8213DSGR WSON DSG 8 3000 2.0 2.0 0.8 DRV8213RTER WQFN RTE 16 3000 3.0 3.0 0.8 Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant DRV8213DSGR WSON DSG 8 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2 DRV8213RTER WQFN RTE 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DRV8213DSGR WSON DSG 8 3000 2.0 2.0 0.8 DRV8213RTER WQFN RTE 16 3000 3.0 3.0 0.8 Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant DRV8213DSGR WSON DSG 8 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2 DRV8213RTER WQFN RTE 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant DRV8213DSGR WSON DSG 8 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2 DRV8213RTER WQFN RTE 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant DevicePackage TypePackage DrawingPinsSPQReel Diameter (mm)Reel Width W1 (mm)A0 (mm)B0 (mm)K0 (mm)P1 (mm)W (mm)Pin1 Quadrant DRV8213DSGR WSON DSG 8 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2 DRV8213RTER WQFN RTE 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 DRV8213DSGR WSON DSG 8 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2 DRV8213DSGRWSONDSG83000180.08.42.32.31.154.08.0Q2 DRV8213RTER WQFN RTE 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 DRV8213RTERWQFNRTE163000330.012.43.33.31.18.012.0Q2 Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DRV8213DSGR WSON DSG 8 3000 2.0 2.0 0.8 DRV8213RTER WQFN RTE 16 3000 3.0 3.0 0.8 Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DRV8213DSGR WSON DSG 8 3000 2.0 2.0 0.8 DRV8213RTER WQFN RTE 16 3000 3.0 3.0 0.8 Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DevicePackage TypePackage DrawingPinsSPQLength (mm)Width (mm)Height (mm) DRV8213DSGR WSON DSG 8 3000 2.0 2.0 0.8 DRV8213RTER WQFN RTE 16 3000 3.0 3.0 0.8 DRV8213DSGR WSON DSG 8 3000 2.0 2.0 0.8 DRV8213DSGRWSONDSG830002.02.00.8 DRV8213RTER WQFN RTE 16 3000 3.0 3.0 0.8 DRV8213RTERWQFNRTE1630003.03.00.8 IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. 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IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2023, Texas Instruments Incorporated TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. 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IMPORTANT NOTICE TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. 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IMPORTANT NOTICE TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. 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TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products.TI’s Terms of Saleti.com TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2023, Texas Instruments Incorporated Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2023, Texas Instruments Incorporated Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2023, Texas Instruments Incorporated Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2023, Texas Instruments Incorporated Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2023, Texas Instruments Incorporated Copyright © 2023, Texas Instruments Incorporated), the IPROPI output disables with the input logic signal. Although the low-side MOSFETs still conduct current as the MOSFETs disable according to the device slew rate (noted in the Electrical Characteristics table by t_RISE time), IPROPI does not represent the current in the low-side MOSFETs during this turnoff time.