SLVSGV9 august   2023 DRV8213

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Diagrams
    7. 7.7 Typical Operating Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 External Components
    4. 8.4 Feature Description
      1. 8.4.1 Bridge Control
      2. 8.4.2 Current Sense and Regulation (IPROPI)
        1. 8.4.2.1 Current Sensing and Current Mirror Gain Selection
        2. 8.4.2.2 Current Regulation
      3. 8.4.3 Hardware Stall Detection
      4. 8.4.4 Protection Circuits
        1. 8.4.4.1 Overcurrent Protection (OCP)
        2. 8.4.4.2 Thermal Shutdown (TSD)
        3. 8.4.4.3 VM Undervoltage Lockout (UVLO)
    5. 8.5 Device Functional Modes
      1. 8.5.1 Active Mode
      2. 8.5.2 Low-Power Sleep Mode
      3. 8.5.3 Fault Mode
    6. 8.6 Pin Diagrams
      1. 8.6.1 Logic-Level Inputs
      2. 8.6.2 Tri-Level Input
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Brushed DC Motor
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Motor Voltage
          2. 9.2.1.2.2 Motor Current
        3. 9.2.1.3 Stall Detection
          1. 9.2.1.3.1 Detailed Design Procedure
            1. 9.2.1.3.1.1 Hardware Stall Detection Application Description
              1. 9.2.1.3.1.1.1 Hardware Stall Detection Timing
              2. 9.2.1.3.1.1.2 Hardware Stall Threshold Selection
            2. 9.2.1.3.1.2 Software Stall Detection Application Description
              1. 9.2.1.3.1.2.1 Software Stall Detection Timing
              2. 9.2.1.3.1.2.2 Software Stall Threshold Selection
        4. 9.2.1.4 Application Curves
        5. 9.2.1.5 Thermal Performance
          1. 9.2.1.5.1 Steady-State Thermal Performance
          2. 9.2.1.5.2 Transient Thermal Performance
  11. 10Power Supply Recommendations
    1. 10.1 Bulk Capacitance
  12. 11Layout
    1. 11.1 Layout Guidelines
  13. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
  14. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.2.1.5 Thermal Performance

The datasheet-specified junction-to-ambient thermal resistance, RθJA, is primarily useful for comparing various drivers or approximating thermal performance. However, the actual system performance may be better or worse than this value depending on PCB stackup, routing, number of vias, and copper area around the thermal pad. The length of time the driver drives a particular current will also impact power dissipation and thermal performance. This section considers how to design for steady-state and transient thermal conditions.

The data in this section was simulated using the following criteria:

WSON (DSG package)

  • 2-layer PCB (size 114.3 x 76.2 x 1.6 mm), standard FR4, 1-oz (35 mm copper thickness) or 2-oz copper thickness. Thermal vias are only present under the thermal pad (2 vias, 1.2mm spacing, 0.3 mm diameter, 0.025 mm Cu plating).
    • Top layer: DRV8213 WSON package footprint and copper plane heatsink. Top layer copper area is varied in simulation.
    • Bottom layer: ground plane thermally connected through vias under the thermal pad for DRV8213. Bottom layer copper area varies with top copper area.
  • 4-layer PCB (size 114.3 x 76.2 x 1.6 mm), standard FR4. Outer planes are 1-oz (35 mm copper thickness) or 2-oz copper thickness. Inner planes are kept at 1-oz. Thermal vias are only present under the thermal pad (2 vias, 1.2mm spacing, 0.3 mm diameter, 0.025 mm Cu plating).
    • Top layer: DRV8213 WSON package footprint and copper plane heatsink. Top layer copper area is varied in simulation.
    • Mid layer 1: GND plane thermally connected to DRV8213 thermal pad through vias. The area of the ground plane is 74.2 mm x 74.2 mm.
    • Mid layer 2: power plane, no thermal connection. The area of the power plane is 74.2 mm x 74.2 mm.
    • Bottom layer: ground plane thermally connected through via stitching from the TOP and internal GND planes. Bottom layer copper area varies with top copper area.

Figure 9-10 shows an example of the simulated board for the DSG package. Table 9-3 shows the dimensions of the board that were varied for each simulation.

GUID-20201208-CA0I-WKBX-LK2B-8SX5VSFGVQVN-low.gifFigure 9-10 WSON PCB model top layer
Table 9-3 Dimension A for 8-pin DSG package
Cu area (mm2)Dimension A (mm)
215.11
420.98
829.27
1640.99

WQFN (RTE package)

  • 2-layer PCB (size 114.3 x 76.2 x 1.6 mm), standard FR4, 1-oz (35 mm copper thickness) or 2-oz copper thickness. Thermal vias are only present under the package footprint (5 vias, 1 mm pitch, 0.2 mm diameter, 0.025 mm Cu plating).
    • Top layer: WQFN package footprint and traces.
    • Bottom layer: ground plane thermally connected through vias under the package footprint. Bottom layer copper area is varied in simulation.
  • 4-layer PCB (size 114.3 x 76.2 x 1.6 mm), standard FR4. Outer planes are 1-oz (35 mm copper thickness) or 2-oz copper thickness. Inner planes are kept at 1-oz. Thermal vias are only present under the package footprint (5 vias, 1 mm pitch, 0.2 mm diameter, 0.025 mm Cu plating).
    • Top layer: WQFN package footprint and traces.
    • Mid layer 1: GND plane thermally connected under package footprint through vias. The area of the ground plane is 74.2 mm x 74.2 mm.
    • Mid layer 2: power plane, no thermal connection. The area of the power plane is 74.2 mm x 74.2 mm.
    • Bottom layer: signal layer with small copper pad underneath the driver and thermally connected through via stitching from the TOP and internal GND plane. Bottom layer thermal pad is the same size as the package (3 mm x 3 mm). Bottom pad size remains constant.

Figure 9-11 shows an example of the simulated board for the WQFN package. Table 9-4 shows the dimensions of the board that were varied for each simulation.

GUID-20230530-SS0I-7RLL-LVMZ-HR0BB51VFS8G-low.pngFigure 9-11 WQFN PCB model top layer
Table 9-4 Dimension A for 16-pin RTE package
Cu area (cm2)Dimension A (mm)
214.14
420.00
828.28
1640.00