SLVSFV5A july   2023  – july 2023 DRV8262

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
      1. 6.4.1 Transient Thermal Impedance & Current Capability
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1  Overview
    2. 7.2  Functional Block Diagram
    3. 7.3  Feature Description
    4. 7.4  Device Operational Modes
      1. 7.4.1 Dual H-Bridge Mode (MODE1 = 0)
      2. 7.4.2 Single H-Bridge Mode (MODE1 = 1)
    5. 7.5  Current Sensing and Regulation
      1. 7.5.1 Current Sensing and Feedback
      2. 7.5.2 Current Regulation
        1. 7.5.2.1 Mixed Decay
        2. 7.5.2.2 Smart tune Dynamic Decay
      3. 7.5.3 Current Sensing with External Resistor
    6. 7.6  Charge Pump
    7. 7.7  Linear Voltage Regulator
    8. 7.8  VCC Voltage Supply
    9. 7.9  Logic Level, Tri-Level and Quad-Level Pin Diagrams
    10. 7.10 Protection Circuits
      1. 7.10.1 VM Undervoltage Lockout (UVLO)
      2. 7.10.2 VCP Undervoltage Lockout (CPUV)
      3. 7.10.3 Logic Supply Power on Reset (POR)
      4. 7.10.4 Overcurrent Protection (OCP)
      5. 7.10.5 Thermal Shutdown (OTSD)
      6. 7.10.6 nFAULT Output
      7. 7.10.7 Fault Condition Summary
    11. 7.11 Device Functional Modes
      1. 7.11.1 Sleep Mode
      2. 7.11.2 Operating Mode
      3. 7.11.3 nSLEEP Reset Pulse
      4. 7.11.4 Functional Modes Summary
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Driving Brushed-DC Motors
        1. 8.1.1.1 Brushed-DC Motor Driver Typical Application
        2. 8.1.1.2 Power Loss Calculations - Dual H-bridge
        3. 8.1.1.3 Power Loss Calculations - Single H-bridge
        4. 8.1.1.4 Junction Temperature Estimation
        5. 8.1.1.5 Application Performance Plots
      2. 8.1.2 Driving Stepper Motors
        1. 8.1.2.1 Stepper Driver Typical Application
        2. 8.1.2.2 Power Loss Calculations
        3. 8.1.2.3 Junction Temperature Estimation
      3. 8.1.3 Driving Thermoelectric Coolers (TEC)
  10. 9 Package Thermal Considerations
    1. 9.1 DDW Package
      1. 9.1.1 Thermal Performance
        1. 9.1.1.1 Steady-State Thermal Performance
        2. 9.1.1.2 Transient Thermal Performance
    2. 9.2 DDV Package
    3. 9.3 PCB Material Recommendation
  11. 10Power Supply Recommendations
    1. 10.1 Bulk Capacitance
    2. 10.2 Power Supplies
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  14. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

The DRV8262 is available in thermally-enhanced, 44-Pin HTSSOP packages.
  • The DDW package contains a PowerPAD™ on the bottom side of the device.
  • The DDV package contains a PowerPAD™ on the top side of the device for thermal coupling to a heatsink.
GUID-20220608-SS0I-RPKQ-7DK9-TSVF9BSXLHMC-low.svg Figure 5-1 Single H-bridge Mode, DDW Package, Top View
GUID-20220608-SS0I-ZCNR-M6HZ-4MZRVKX3XZ2C-low.svg Figure 5-2 Single H-bridge Mode, DDV Package, Top View
GUID-20220608-SS0I-D2WZ-0VS9-WM7FWTFR8NPF-low.svg Figure 5-3 Dual H-bridge Mode, DDW Package, Top View
GUID-20220608-SS0I-SPQX-X29D-Z9G2W2KGMC9Q-low.svg Figure 5-4 Dual H-bridge Mode, DDV Package, Top View
Table 5-1 Pin Configuration
PIN TYPE DESCRIPTION
NAME DDW DDV

Single H-Bridge

Dual H-Bridge

RSVD

IN4

38

29

 Input PWM input for H-bridge 2 in dual H-bridge mode. Leave this pin unconnected in single H-bridge mode.

RSVD

IN3

39

28

Input

 PWM input for H-bridge 2 in dual H-bridge mode. Leave this pin unconnected in single H-bridge mode.

IPROPI

 IPROPI2

30

37

Output

 Analog current output for H-bridge 2 in dual H-bridge mode. Connect to the other IPROPI pin in single H-bridge mode.
IPROPI IPROPI1

31

36

Output

 Analog current output for H-bridge 1 in dual H-bridge mode. Connect to the other IPROPI pin in single H-bridge mode.

VREF

VREF2

33

34

Input

 Reference input to set current for H-bridge 2 in dual H-bridge mode. Tie to the other VREF pin in single H-bridge mode. DVDD can be used to provide VREF through a resistor divider.

VREF

VREF1

34

33

Input

 Reference input to set current for H-bridge 1 in dual H-bridge mode. Tie to the other VREF pin in single H-bridge mode. DVDD can be used to provide VREF through a resistor divider.

OUT1

OUT1

4, 5, 6

 17, 18, 19

Output

 Winding output. Connect to motor terminal.

OUT2

OUT2

7, 8, 9

 14, 15, 16 Output Winding output. Connect to motor terminal.

OUT1

OUT3

17, 18, 19

 4, 5, 6 Output Winding output. Connect to motor terminal.

OUT2

OUT4

14, 15, 16

 7, 8, 9 Output Winding output. Connect to motor terminal.

PGND

PGND12

3, 10

 13, 20 Power Power ground for H-bridge. Connect to system ground.

PGND

PGND34

13, 20

 3, 10 Power Power ground for H-bridge. Connect to system ground.

IN2

40

27

 Input PWM input for H-bridge 1.

IN1

41

26

 Input PWM input for H-bridge 1.

RSVD

36

31

-

Reserved. Leave Unconnected.

DECAY

37

30

Input

 Decay setting pin.

TOFF

35

32

Input

PWM OFF time setting pin.

OCPM

27

40

Input

Determines the fault recovery method. Depending on the OCPM voltage, fault recovery can be either latch-off or auto-retry.
VCP 1

22

Power

Charge pump output. Connect a X7R, 1-μF, 16-V ceramic capacitor to VM.
VM

2, 11, 12, 21

2, 11, 12, 21

Power

 Power supply. Connect to supply voltage and bypass to PGND with two 0.01-μF ceramic capacitors plus a bulk capacitor rated for VM.
GND

22, 23

1, 44

Power

 Device ground. Connect to system ground.
CPH

44

23

 Power Charge pump switching node. Connect a X7R, 0.022-μF, VM rated ceramic capacitor from CPH to CPL.
CPL

43

24
DVDD

24

43

 Power Internal LDO output. Connect a X7R, 0.47-μF to 1-μF, 6.3-V or 10-V rated ceramic capacitor to GND.
VCC

25

42

Power

 Supply voltage for internal logic blocks. When no separate supply voltage is available, tie the VCC pin to the DVDD output.
nFAULT

26

41

 Open Drain Fault indication. Pulled logic low with fault condition; open drain output requires an external pullup resistor.
MODE1

28

39

Input

 This pin selects between dual H-bridge and single H-bridge modes of operation.
MODE2

29

38

 Input This pin selects the interface - between Phase/Enable (PH/EN) and PWM (IN/IN).

When this pin is grounded, the device operates with PH/EN interface. To configure PWM interface, see Section 7.4 for details.

nSLEEP

42

25

Input

Sleep mode input. Logic high to enable device; logic low to enter low-power sleep mode. An nSLEEP low pulse clears latched faults.

RSVD

32

35

-

Reserved. Leave Unconnected.
PAD - - - Thermal pad.