SLVSFV5C July   2023  – July 2025 DRV8262

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
      1. 5.4.1 Transient Thermal Impedance & Current Capability
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1  Overview
    2. 6.2  Functional Block Diagram
    3. 6.3  Feature Description
      1. 6.3.1 Spread Spectrum
    4. 6.4  Device Operational Modes
      1. 6.4.1 Dual H-Bridge Mode (MODE1 = 0)
      2. 6.4.2 Single H-Bridge Mode (MODE1 = 1)
    5. 6.5  Current Sensing and Regulation
      1. 6.5.1 Current Sensing and Feedback
      2. 6.5.2 Current Regulation
        1. 6.5.2.1 Mixed Decay
        2. 6.5.2.2 Smart tune Dynamic Decay
      3. 6.5.3 Current Sensing with External Resistor
    6. 6.6  Charge Pump
    7. 6.7  Linear Voltage Regulator
    8. 6.8  VCC Voltage Supply
    9. 6.9  Logic Level, Tri-Level and Quad-Level Pin Diagrams
    10. 6.10 Protection Circuits
      1. 6.10.1 VM Undervoltage Lockout (UVLO)
      2. 6.10.2 VCP Undervoltage Lockout (CPUV)
      3. 6.10.3 Logic Supply Power on Reset (POR)
      4. 6.10.4 Overcurrent Protection (OCP)
      5. 6.10.5 Thermal Shutdown (OTSD)
      6. 6.10.6 nFAULT Output
      7. 6.10.7 Fault Condition Summary
    11. 6.11 Device Functional Modes
      1. 6.11.1 Sleep Mode
      2. 6.11.2 Operating Mode
      3. 6.11.3 nSLEEP Reset Pulse
      4. 6.11.4 Functional Modes Summary
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Driving Brushed-DC Motors
        1. 7.1.1.1 Brushed-DC Motor Driver Typical Application
        2. 7.1.1.2 Power Loss Calculations - Dual H-bridge
        3. 7.1.1.3 Power Loss Calculations - Single H-bridge
        4. 7.1.1.4 Junction Temperature Estimation
        5. 7.1.1.5 Application Performance Plots
      2. 7.1.2 Driving Stepper Motors
        1. 7.1.2.1 Stepper Driver Typical Application
        2. 7.1.2.2 Power Loss Calculations
        3. 7.1.2.3 Junction Temperature Estimation
      3. 7.1.3 Driving Thermoelectric Coolers (TEC)
    2. 7.2 Power Supply Recommendations
      1. 7.2.1 Bulk Capacitance
      2. 7.2.2 Power Supplies
    3. 7.3 Layout
      1. 7.3.1 Layout Guidelines
      2. 7.3.2 Layout Example
  9. 8 Package Thermal Considerations
    1. 8.1 DDW Package
      1. 8.1.1 Thermal Performance
        1. 8.1.1.1 Steady-State Thermal Performance
        2. 8.1.1.2 Transient Thermal Performance
    2. 8.2 DDV Package
    3. 8.3 PCB Material Recommendation
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.5 Electrical Characteristics

Typical values are at TA = 25°C. All limits are over recommended operating conditions, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLIES (VM, DVDD)
IVM VM operating supply current nSLEEP = 1, No load, VCC = External 5V

5

8

 mA
nSLEEP = 1, No motor load, VCC = DVDD

8.5

13
IVMQ VM sleep mode supply current nSLEEP = 0 3

8

 μA
tSLEEP Sleep time nSLEEP = 0 to sleep-mode 120 μs
tRESET nSLEEP reset pulse nSLEEP low to clear fault 20 40 μs
tWAKE Wake-up time nSLEEP = 1 to output transition 0.75 1 ms
tON Turn-on time VM > UVLO to output transition 0.8 1.3 ms
VDVDD Internal regulator voltage No external load, 6V < VVM < 60V 4.75 5 5.25 V
No external load, VVM = 4.5V

4.3

4.45

V
CHARGE PUMP (VCP, CPH, CPL)
VVCP VCP operating voltage 6V < VVM < 60V VVM + 5 V
f(VCP) Charge pump switching frequency VVM > UVLO; nSLEEP = 1 360 kHz
LOGIC-LEVEL INPUTS (IN1, IN2, IN3, IN4, OCPM, MODE1, MODE2, nSLEEP)
VIL Input logic-low voltage 0 0.6 V
VIH Input logic-high voltage 1.5 5.5 V
VHYS Input logic hysteresis 100 mV
VHYS

_nSLEEP

 nSLEEP logic hysteresis

300

mV
IIL Input logic-low current (except MODE2) VIN = 0V –1 1 μA
IIH Input logic-high current (except MODE2) VIN = 5V 50 μA
RPU MODE2 internal pull-up resistor

220

 kΩ

tPDH1

INx high to OUTx high propagation delay

600

ns

tPDL1

 INx low to OUTx low propagation delay

600

ns
TRI-LEVEL INPUTS (DECAY)
VI1 Input logic-low voltage Tied to GND

0

0.6

V
VI2 Input Hi-Z voltage Hi-Z (>500kΩ to GND)

1.8

2

2.2

V
VI3 Input logic-high voltage Tied to DVDD

2.7

5.5

V
IO Output pull-up current

10.5

 μA
QUAD-LEVEL INPUTS (TOFF)
VI1 Input logic-low voltage Tied to GND 0 0.6 V
VI2 330kΩ ± 5% to GND 1 1.25 1.4 V
VI3 Input Hi-Z voltage Hi-Z (>500kΩ to GND) 1.8 2 2.2 V
VI4 Input logic-high voltage Tied to DVDD 2.7 5.5 V
IO Output pull-up current 10.5 μA
CONTROL OUTPUTS (nFAULT)
VOL Output logic-low voltage IO = 5mA 0.3 V
IOH Output logic-high leakage –1 1 μA
MOTOR DRIVER OUTPUTS (OUT1, OUT2, OUT3, OUT4)
RDS(ONH_DUAL) Dual H-bridge, High-side FET on resistance

TJ = 25 °C, IO = -5A

50

60

 mΩ
TJ = 125 °C, IO = -5A

75

94

 mΩ
TJ = 150 °C, IO = -5A

85

 107 mΩ
RDS(ONL_DUAL) Dual H-bridge, Low-side FET on resistance TJ = 25 °C, IO = 5A

50

60

 mΩ
TJ = 125 °C, IO = 5A

72

90

 mΩ
TJ = 150 °C, IO = 5A

80

 100 mΩ
RDS(ONH_SINGLE) Single H-bridge, High-side FET on resistance TJ = 25 °C, IO = -5A

25

 30 mΩ
TJ = 125 °C, IO = -5A 38

47

 mΩ
TJ = 150 °C, IO = -5 A

43

54

 mΩ
RDS(ONL_SINGLE) Single H-bridge, Low-side FET on resistance TJ = 25 °C, IO = 5A

25

 30 mΩ
TJ = 125 °C, IO = 5A

36

45

 mΩ
TJ = 150 °C, IO = 5A

40

50

 mΩ

ILEAK

Output leakage current to GND

Sleep-mode, H-bridges are Hi-Z, VVM = 60V

300

 μA
tRF Output rise/fall time IO = 5A, between 10% and 90%

110

 ns

tD

Output dead time

 VM = 24V, IO = 5A

300

ns
CURRENT SENSE AND REGULATION (IPROPI, VREF)

AIPROPI

Current mirror gain

212

 μA/A

AERR

Current mirror scaling error

10% to 20% rated current

-12

12

%

20% to 40% rated current

-7

7

40% to 100% rated current

-4

4

IVREF

VREF Leakage Current

VREF = 3.3V

30

 nA
tOFF PWM off-time TOFF = 0 7 μs
TOFF = 1 16
TOFF = Hi-Z 24
TOFF = 330kΩ to GND 32

tDEG

 Current regulation deglitch time

0.5

 μs

tBLK

Current Regulation Blanking time

1.5

 μs
PROTECTION CIRCUITS
VUVLO VM UVLO lockout VM falling 4.1 4.25 4.35 V
VM rising 4.2 4.35 4.45
VCCUVLO VCC UVLO lockout

VCC falling

2.7

2.8

2.9

V

VCC rising

2.8

2.9

3.05
VUVLO,HYS Undervoltage hysteresis Rising to falling threshold 100 mV
VCPUV Charge pump undervoltage VCP falling VVM + 2 V
IOCP Overcurrent protection, DDW Package Dual H-bridge, Current through any FET, DDW Package

8

 A
Single H-bridge, Current through any FET, DDW Package

16

 A
IOCP Overcurrent protection, DDV Package Dual H-bridge, Current through any FET, DDV Package

16

A
Single H-bridge, Current through any FET, DDV Package

32

A
tOCP Overcurrent detection delay

2.1

 μs

tRETRY

Overcurrent retry time

4.1

ms
TOTSD Thermal shutdown Die temperature TJ 150 165 180 °C
THYS_OTSD Thermal shutdown hysteresis Die temperature TJ 20 °C
(1) Verified by design.
DRV8262 IPROPI Timing Diagram Figure 5-1 IPROPI Timing Diagram