SLVSFV5A july   2023  – july 2023 DRV8262

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
      1. 6.4.1 Transient Thermal Impedance & Current Capability
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1  Overview
    2. 7.2  Functional Block Diagram
    3. 7.3  Feature Description
    4. 7.4  Device Operational Modes
      1. 7.4.1 Dual H-Bridge Mode (MODE1 = 0)
      2. 7.4.2 Single H-Bridge Mode (MODE1 = 1)
    5. 7.5  Current Sensing and Regulation
      1. 7.5.1 Current Sensing and Feedback
      2. 7.5.2 Current Regulation
        1. 7.5.2.1 Mixed Decay
        2. 7.5.2.2 Smart tune Dynamic Decay
      3. 7.5.3 Current Sensing with External Resistor
    6. 7.6  Charge Pump
    7. 7.7  Linear Voltage Regulator
    8. 7.8  VCC Voltage Supply
    9. 7.9  Logic Level, Tri-Level and Quad-Level Pin Diagrams
    10. 7.10 Protection Circuits
      1. 7.10.1 VM Undervoltage Lockout (UVLO)
      2. 7.10.2 VCP Undervoltage Lockout (CPUV)
      3. 7.10.3 Logic Supply Power on Reset (POR)
      4. 7.10.4 Overcurrent Protection (OCP)
      5. 7.10.5 Thermal Shutdown (OTSD)
      6. 7.10.6 nFAULT Output
      7. 7.10.7 Fault Condition Summary
    11. 7.11 Device Functional Modes
      1. 7.11.1 Sleep Mode
      2. 7.11.2 Operating Mode
      3. 7.11.3 nSLEEP Reset Pulse
      4. 7.11.4 Functional Modes Summary
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Driving Brushed-DC Motors
        1. 8.1.1.1 Brushed-DC Motor Driver Typical Application
        2. 8.1.1.2 Power Loss Calculations - Dual H-bridge
        3. 8.1.1.3 Power Loss Calculations - Single H-bridge
        4. 8.1.1.4 Junction Temperature Estimation
        5. 8.1.1.5 Application Performance Plots
      2. 8.1.2 Driving Stepper Motors
        1. 8.1.2.1 Stepper Driver Typical Application
        2. 8.1.2.2 Power Loss Calculations
        3. 8.1.2.3 Junction Temperature Estimation
      3. 8.1.3 Driving Thermoelectric Coolers (TEC)
  10. 9 Package Thermal Considerations
    1. 9.1 DDW Package
      1. 9.1.1 Thermal Performance
        1. 9.1.1.1 Steady-State Thermal Performance
        2. 9.1.1.2 Transient Thermal Performance
    2. 9.2 DDV Package
    3. 9.3 PCB Material Recommendation
  11. 10Power Supply Recommendations
    1. 10.1 Bulk Capacitance
    2. 10.2 Power Supplies
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  14. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.7 Linear Voltage Regulator

A linear voltage regulator is integrated in the device. When the VCC pin is connected to DVDD, the DVDD regulator provides power to the low-side gate driver and all the internal circuits. For proper operation, bypass the DVDD pin to GND using a 1 μF ceramic capacitor. The DVDD output is nominally 5-V.

GUID-20220519-SS0I-KJ74-7HD5-SCVPZVPMZV1V-low.svgFigure 7-11 Linear Voltage Regulator Block Diagram

If a digital input must be tied permanently high, tying the input to the DVDD pin instead of an external regulator is preferred. This method saves power when the VM pin is not applied or in sleep mode: the DVDD regulator is disabled and current does not flow through the input pulldown resistors. For reference, logic level inputs have a typical pulldown of 200 kΩ.

The nSLEEP pin cannot be tied to DVDD, else the device will never exit sleep mode.