SLLSFB6A May   2020  – April 2021 DRV8705-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Descriptions
  4. 4 Revision History
  5. 5 Pin Configuration
    1.     DRV8705-Q1_RHB Package (VQFN) Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 External Components
      2. 7.3.2 Device Interface Variants
        1. 7.3.2.1 Serial Peripheral Interface (SPI)
        2. 7.3.2.2 Hardware (H/W)
      3. 7.3.3 Input PWM Modes
        1. 7.3.3.1 Half-Bridge Control
        2. 7.3.3.2 H-Bridge Control
        3. 7.3.3.3 Split HS and LS Solenoid Control
      4. 7.3.4 Smart Gate Driver
        1. 7.3.4.1 Functional Block Diagram
        2. 7.3.4.2 Slew Rate Control (IDRIVE)
        3. 7.3.4.3 Gate Drive State Machine (TDRIVE)
      5. 7.3.5 Doubler (Single-Stage) Charge Pump
      6. 7.3.6 Low-Side Differential Current Shunt Amplifier
      7. 7.3.7 Pin Diagrams
        1. 7.3.7.1 Logic Level Input Pin (DRVOFF, IN1/EN, IN2/PH, nHIZx, nSLEEP, nSCS, SCLK, SDI)
        2. 7.3.7.2 Logic Level Push Pull Output (SDO)
        3. 7.3.7.3 Logic Level Open Drain Output (nFAULT)
        4. 7.3.7.4 Quad-Level Input (GAIN)
        5. 7.3.7.5 Six-Level Input (IDRIVE, VDS)
      8. 7.3.8 Protection and Diagnostics
        1. 7.3.8.1  Gate Driver Disable and Enable (DRVOFF and EN_DRV)
        2. 7.3.8.2  Fault Reset (CLR_FLT)
        3. 7.3.8.3  DVDD Logic Supply Power on Reset (DVDD_POR)
        4. 7.3.8.4  PVDD Supply Undervoltage Monitor (PVDD_UV)
        5. 7.3.8.5  PVDD Supply Overvoltage Monitor (PVDD_OV)
        6. 7.3.8.6  VCP Charge Pump Undervoltage Lockout (VCP_UV)
        7. 7.3.8.7  MOSFET VDS Overcurrent Protection (VDS_OCP)
        8. 7.3.8.8  Gate Driver Fault (VGS_GDF)
        9. 7.3.8.9  Thermal Warning (OTW)
        10. 7.3.8.10 Thermal Shutdown (OTSD)
        11. 7.3.8.11 Offline Short Circuit and Open Load Detection (OOL and OSC)
        12. 7.3.8.12 Fault Detection and Response Summary Table
    4. 7.4 Device Function Modes
      1. 7.4.1 Inactive or Sleep State
      2. 7.4.2 Standby State
      3. 7.4.3 Operating State
    5. 7.5 Programming
      1. 7.5.1 SPI Interface
      2. 7.5.2 SPI Format
      3. 7.5.3 SPI Interface for Multiple Slaves
        1. 7.5.3.1 SPI Interface for Multiple Slaves in Daisy Chain
    6. 7.6 Register Maps
      1. 7.6.1 STATUS Registers
      2. 7.6.2 CONTROL Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Gate Driver Configuration
          1. 8.2.2.1.1 VCP Load Calculation Example
          2. 8.2.2.1.2 IDRIVE Calculation Example
        2. 8.2.2.2 Current Shunt Amplifier Configuration
        3. 8.2.2.3 Power Dissipation
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
      2. 11.1.2 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RHB|32
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.6 Low-Side Differential Current Shunt Amplifier

The DRV8705-Q1 integrates a high-performance, low-side, bidirectional, current-shunt amplifier for current measurements using a shunt resistor in the external half-bridge. Current measurements are commonly used to implement overcurrent protection, external torque control, or commutation with an external controller. The current shunt amplifiers include features such as programmable gain, unidirectional and bidirectional support, output blanking and sample and hold switch, and a dedicated voltage reference pin (AREF) to set a mid point bias voltage for the amplifier output. A simplified block diagram is shown in Figure 7-10. SP should connect to the positive terminal of the shunt resistor and SN should connect to the negative terminal of the shunt resistor. If the amplifier is not utilized, the AREF, SN, SP inputs can be tied to AGND, AGND to PCB GND and the SO output left floating.

GUID-713838A6-8588-4A66-9034-811571A270B4-low.gifFigure 7-10 Amplifier Simplified Block Diagram

The amplifier can generate an output voltage bias through the AREF pin. The AREF pin goes to a divider network, a buffer, and then sets the output voltage bias for the differential amplifier. On SPI device variants, the gain is configured through the register setting CSA_GAIN and the reference division ratio through CSA_DIV. On H/W device variants, the reference division ratio is fixed to VAREF / 2. The gain is configured through the GAIN pin.

Lastly, the amplifier has an output blanking or sample and hold switch. This option is only available on SPI device variants. The output switch can be used to disconnect the amplifier output during PWM switching to reduce output noise (blanking) or during motor braking to maintain the output value if the shunt is used in high-side or low-side configuration (sample and hold). The blanking circuit can be set trigger on the active half-bridge (half-bridge 1 or half-bridge 2) through the CSA_BLK_SEL register setting. The blanking period can be configured through the CSA_BLK register setting. The sample and hold circuit can be enabled with the CSA_SH_EN register setting. When active, the sample and hold will trigger whenever the driver enters high-side or low-side braking. To utilize either the blanking or sample and hold functions an output hold up capacitor will be required to stabilize the amplifier output when it is disconnected. Typically it is recommended, that this capacitor be after a series resistor in a RC filter configuration to limit direct capacitance seen directly at the amplifier output.

GUID-96CDD1BA-EB44-4841-87FA-58192EAF1E01-low.gifFigure 7-11 DRV8705-Q1 Amplifier Blanking Example

Figure 7-11 shows an example of the amplifier blanking function. This function can be utilized to hi-Z the amplifier output during a switching transition, but is not required by default. This function can be beneficial if noise due to wide-common mode swings or ground shifts are occurring during the PWM switching transition and interfering with the amplifier output. As shown in the image, the blanking function operates by disabling the amplifier output for a period of time after a transition on either GHx or GLx. This period of time is determined by the tBLK setting configured through the CSA_BLK register setting.

GUID-FE723989-3FAE-49F3-A339-03308C66D808-low.gifFigure 7-12 DRV8705-Q1 Amplifier Sample & Hold Example

Figure 7-12 show an example of the amplifier sample and hold function. This function can be utilized to hi-Z the amplifier output when the current is recirculating in the H-bridge, but is not required by default. The function can be beneficial if the shunt resistor is configured into the low-side or the high-side of the H-bridge in which during current recirculation the current information is lost. As shown in the image, the sample and hold function will hold the previous state of the amplifier output since the output capacitor will remain charged. The amplifier will resume operation when the H-bridge leaves the recirculation state.