SLLSFB6B May 2020 – May 2024 DRV8705-Q1
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
When the nSLEEP pin is logic high and DVDD input has crossed the VDVDD_POR threshold, the device enters a power on standby state after tWAKE delay. The digital core and SPI communication will be active but the charge pump and gate drivers will remain disabled until the PVDD input has cross the VPVDD_UV threshold. In this state, the SPI registers can be programmed and faults reported, but no gate driver operation is possible.